2 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
4 * Author: Tony Li <tony.li@freescale.com>
5 * Jason Jin <Jason.jin@freescale.com>
7 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 of the
15 #include <linux/irq.h>
16 #include <linux/msi.h>
17 #include <linux/pci.h>
18 #include <linux/slab.h>
19 #include <linux/of_platform.h>
20 #include <linux/interrupt.h>
21 #include <linux/seq_file.h>
22 #include <sysdev/fsl_soc.h>
24 #include <asm/hw_irq.h>
25 #include <asm/ppc-pci.h>
27 #include <asm/fsl_hcalls.h>
32 #define MSIIR_OFFSET_MASK 0xfffff
33 #define MSIIR_IBS_SHIFT 0
34 #define MSIIR_SRS_SHIFT 5
35 #define MSIIR1_IBS_SHIFT 4
36 #define MSIIR1_SRS_SHIFT 0
37 #define MSI_SRS_MASK 0xf
38 #define MSI_IBS_MASK 0x1f
40 #define msi_hwirq(msi, msir_index, intr_index) \
41 ((msir_index) << (msi)->srs_shift | \
42 ((intr_index) << (msi)->ibs_shift))
44 static LIST_HEAD(msi_head);
46 struct fsl_msi_feature {
48 u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
51 struct fsl_msi_cascade_data {
52 struct fsl_msi *msi_data;
57 static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
59 return in_be32(base + (reg >> 2));
63 * We do not need this actually. The MSIR register has been read once
64 * in the cascade interrupt. So, this MSI interrupt has been acked
66 static void fsl_msi_end_irq(struct irq_data *d)
70 static void fsl_msi_print_chip(struct irq_data *irqd, struct seq_file *p)
72 struct fsl_msi *msi_data = irqd->domain->host_data;
73 irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
74 int cascade_virq, srs;
76 srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK;
77 cascade_virq = msi_data->cascade_array[srs]->virq;
79 seq_printf(p, " fsl-msi-%d", cascade_virq);
83 static struct irq_chip fsl_msi_chip = {
84 .irq_mask = pci_msi_mask_irq,
85 .irq_unmask = pci_msi_unmask_irq,
86 .irq_ack = fsl_msi_end_irq,
87 .irq_print_chip = fsl_msi_print_chip,
90 static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq,
93 struct fsl_msi *msi_data = h->host_data;
94 struct irq_chip *chip = &fsl_msi_chip;
96 irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
98 irq_set_chip_data(virq, msi_data);
99 irq_set_chip_and_handler(virq, chip, handle_edge_irq);
104 static const struct irq_domain_ops fsl_msi_host_ops = {
105 .map = fsl_msi_host_map,
108 static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
112 rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS_MAX,
113 msi_data->irqhost->of_node);
118 * Reserve all the hwirqs
119 * The available hwirqs will be released in fsl_msi_setup_hwirq()
121 for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++)
122 msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq);
127 static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
129 struct msi_desc *entry;
130 struct fsl_msi *msi_data;
132 list_for_each_entry(entry, &pdev->msi_list, list) {
133 if (entry->irq == NO_IRQ)
135 msi_data = irq_get_chip_data(entry->irq);
136 irq_set_msi_desc(entry->irq, NULL);
137 msi_bitmap_free_hwirqs(&msi_data->bitmap,
138 virq_to_hw(entry->irq), 1);
139 irq_dispose_mapping(entry->irq);
145 static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
147 struct fsl_msi *fsl_msi_data)
149 struct fsl_msi *msi_data = fsl_msi_data;
150 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
151 u64 address; /* Physical address of the MSIIR */
155 /* If the msi-address-64 property exists, then use it */
156 reg = of_get_property(hose->dn, "msi-address-64", &len);
157 if (reg && (len == sizeof(u64)))
158 address = be64_to_cpup(reg);
160 address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset;
162 msg->address_lo = lower_32_bits(address);
163 msg->address_hi = upper_32_bits(address);
166 * MPIC version 2.0 has erratum PIC1. It causes
167 * that neither MSI nor MSI-X can work fine.
168 * This is a workaround to allow MSI-X to function
169 * properly. It only works for MSI-X, we prevent
170 * MSI on buggy chips in fsl_setup_msi_irqs().
172 if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
173 msg->data = __swab32(hwirq);
177 pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__,
178 (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK,
179 (hwirq >> msi_data->ibs_shift) & MSI_IBS_MASK);
182 static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
184 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
185 struct device_node *np;
187 int rc, hwirq = -ENOMEM;
189 struct msi_desc *entry;
191 struct fsl_msi *msi_data;
193 if (type == PCI_CAP_ID_MSI) {
195 * MPIC version 2.0 has erratum PIC1. For now MSI
196 * could not work. So check to prevent MSI from
197 * being used on the board with this erratum.
199 list_for_each_entry(msi_data, &msi_head, list)
200 if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
205 * If the PCI node has an fsl,msi property, then we need to use it
206 * to find the specific MSI.
208 np = of_parse_phandle(hose->dn, "fsl,msi", 0);
210 if (of_device_is_compatible(np, "fsl,mpic-msi") ||
211 of_device_is_compatible(np, "fsl,vmpic-msi") ||
212 of_device_is_compatible(np, "fsl,vmpic-msi-v4.3"))
213 phandle = np->phandle;
216 "node %s has an invalid fsl,msi phandle %u\n",
217 hose->dn->full_name, np->phandle);
222 list_for_each_entry(entry, &pdev->msi_list, list) {
224 * Loop over all the MSI devices until we find one that has an
225 * available interrupt.
227 list_for_each_entry(msi_data, &msi_head, list) {
229 * If the PCI node has an fsl,msi property, then we
230 * restrict our search to the corresponding MSI node.
231 * The simplest way is to skip over MSI nodes with the
232 * wrong phandle. Under the Freescale hypervisor, this
233 * has the additional benefit of skipping over MSI
234 * nodes that are not mapped in the PAMU.
236 if (phandle && (phandle != msi_data->phandle))
239 hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
246 dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
250 virq = irq_create_mapping(msi_data->irqhost, hwirq);
252 if (virq == NO_IRQ) {
253 dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
254 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
258 /* chip_data is msi_data via host->hostdata in host->map() */
259 irq_set_msi_desc(virq, entry);
261 fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
262 pci_write_msi_msg(virq, &msg);
267 /* free by the caller of this function */
271 static irqreturn_t fsl_msi_cascade(int irq, void *data)
273 unsigned int cascade_irq;
274 struct fsl_msi *msi_data;
279 struct fsl_msi_cascade_data *cascade_data = data;
280 irqreturn_t ret = IRQ_NONE;
282 msi_data = cascade_data->msi_data;
284 msir_index = cascade_data->index;
286 if (msir_index >= NR_MSI_REG_MAX)
287 cascade_irq = NO_IRQ;
289 switch (msi_data->feature & FSL_PIC_IP_MASK) {
290 case FSL_PIC_IP_MPIC:
291 msir_value = fsl_msi_read(msi_data->msi_regs,
294 case FSL_PIC_IP_IPIC:
295 msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
297 #ifdef CONFIG_EPAPR_PARAVIRT
298 case FSL_PIC_IP_VMPIC: {
300 ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
302 pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
303 "irq %u (ret=%u)\n", irq, ret);
312 intr_index = ffs(msir_value) - 1;
314 cascade_irq = irq_linear_revmap(msi_data->irqhost,
315 msi_hwirq(msi_data, msir_index,
316 intr_index + have_shift));
317 if (cascade_irq != NO_IRQ) {
318 generic_handle_irq(cascade_irq);
321 have_shift += intr_index + 1;
322 msir_value = msir_value >> (intr_index + 1);
328 static int fsl_of_msi_remove(struct platform_device *ofdev)
330 struct fsl_msi *msi = platform_get_drvdata(ofdev);
333 if (msi->list.prev != NULL)
334 list_del(&msi->list);
335 for (i = 0; i < NR_MSI_REG_MAX; i++) {
336 if (msi->cascade_array[i]) {
337 virq = msi->cascade_array[i]->virq;
339 BUG_ON(virq == NO_IRQ);
341 free_irq(virq, msi->cascade_array[i]);
342 kfree(msi->cascade_array[i]);
343 irq_dispose_mapping(virq);
346 if (msi->bitmap.bitmap)
347 msi_bitmap_free(&msi->bitmap);
348 if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
349 iounmap(msi->msi_regs);
355 static struct lock_class_key fsl_msi_irq_class;
357 static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
358 int offset, int irq_index)
360 struct fsl_msi_cascade_data *cascade_data = NULL;
361 int virt_msir, i, ret;
363 virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
364 if (virt_msir == NO_IRQ) {
365 dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
366 __func__, irq_index);
370 cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
372 dev_err(&dev->dev, "No memory for MSI cascade data\n");
375 irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class);
376 cascade_data->index = offset;
377 cascade_data->msi_data = msi;
378 cascade_data->virq = virt_msir;
379 msi->cascade_array[irq_index] = cascade_data;
381 ret = request_irq(virt_msir, fsl_msi_cascade, IRQF_NO_THREAD,
382 "fsl-msi-cascade", cascade_data);
384 dev_err(&dev->dev, "failed to request_irq(%d), ret = %d\n",
389 /* Release the hwirqs corresponding to this MSI register */
390 for (i = 0; i < IRQS_PER_MSI_REG; i++)
391 msi_bitmap_free_hwirqs(&msi->bitmap,
392 msi_hwirq(msi, offset, i), 1);
397 static const struct of_device_id fsl_of_msi_ids[];
398 static int fsl_of_msi_probe(struct platform_device *dev)
400 const struct of_device_id *match;
402 struct resource res, msiir;
403 int err, i, j, irq_index, count;
405 const struct fsl_msi_feature *features;
409 match = of_match_device(fsl_of_msi_ids, &dev->dev);
412 features = match->data;
414 printk(KERN_DEBUG "Setting up Freescale MSI support\n");
416 msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
418 dev_err(&dev->dev, "No memory for MSI structure\n");
421 platform_set_drvdata(dev, msi);
423 msi->irqhost = irq_domain_add_linear(dev->dev.of_node,
424 NR_MSI_IRQS_MAX, &fsl_msi_host_ops, msi);
426 if (msi->irqhost == NULL) {
427 dev_err(&dev->dev, "No memory for MSI irqhost\n");
433 * Under the Freescale hypervisor, the msi nodes don't have a 'reg'
434 * property. Instead, we use hypercalls to access the MSI.
436 if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
437 err = of_address_to_resource(dev->dev.of_node, 0, &res);
439 dev_err(&dev->dev, "invalid resource for node %s\n",
440 dev->dev.of_node->full_name);
444 msi->msi_regs = ioremap(res.start, resource_size(&res));
445 if (!msi->msi_regs) {
447 dev_err(&dev->dev, "could not map node %s\n",
448 dev->dev.of_node->full_name);
452 features->msiir_offset + (res.start & 0xfffff);
455 * First read the MSIIR/MSIIR1 offset from dts
456 * On failure use the hardcode MSIIR offset
458 if (of_address_to_resource(dev->dev.of_node, 1, &msiir))
459 msi->msiir_offset = features->msiir_offset +
460 (res.start & MSIIR_OFFSET_MASK);
462 msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK;
465 msi->feature = features->fsl_pic_ip;
467 /* For erratum PIC1 on MPIC version 2.0*/
468 if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) == FSL_PIC_IP_MPIC
469 && (fsl_mpic_primary_get_version() == 0x0200))
470 msi->feature |= MSI_HW_ERRATA_ENDIAN;
473 * Remember the phandle, so that we can match with any PCI nodes
474 * that have an "fsl,msi" property.
476 msi->phandle = dev->dev.of_node->phandle;
478 err = fsl_msi_init_allocator(msi);
480 dev_err(&dev->dev, "Error allocating MSI bitmap\n");
484 p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
486 if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3") ||
487 of_device_is_compatible(dev->dev.of_node, "fsl,vmpic-msi-v4.3")) {
488 msi->srs_shift = MSIIR1_SRS_SHIFT;
489 msi->ibs_shift = MSIIR1_IBS_SHIFT;
491 dev_warn(&dev->dev, "%s: dose not support msi-available-ranges property\n",
494 for (irq_index = 0; irq_index < NR_MSI_REG_MSIIR1;
496 err = fsl_msi_setup_hwirq(msi, dev,
497 irq_index, irq_index);
502 static const u32 all_avail[] =
503 { 0, NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG };
505 msi->srs_shift = MSIIR_SRS_SHIFT;
506 msi->ibs_shift = MSIIR_IBS_SHIFT;
508 if (p && len % (2 * sizeof(u32)) != 0) {
509 dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
517 len = sizeof(all_avail);
520 for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
521 if (p[i * 2] % IRQS_PER_MSI_REG ||
522 p[i * 2 + 1] % IRQS_PER_MSI_REG) {
523 pr_warn("%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
524 __func__, dev->dev.of_node->full_name,
525 p[i * 2 + 1], p[i * 2]);
530 offset = p[i * 2] / IRQS_PER_MSI_REG;
531 count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
533 for (j = 0; j < count; j++, irq_index++) {
534 err = fsl_msi_setup_hwirq(msi, dev, offset + j,
542 list_add_tail(&msi->list, &msi_head);
544 /* The multiple setting ppc_md.setup_msi_irqs will not harm things */
545 if (!ppc_md.setup_msi_irqs) {
546 ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
547 ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
548 } else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
549 dev_err(&dev->dev, "Different MSI driver already installed!\n");
555 fsl_of_msi_remove(dev);
559 static const struct fsl_msi_feature mpic_msi_feature = {
560 .fsl_pic_ip = FSL_PIC_IP_MPIC,
561 .msiir_offset = 0x140,
564 static const struct fsl_msi_feature ipic_msi_feature = {
565 .fsl_pic_ip = FSL_PIC_IP_IPIC,
566 .msiir_offset = 0x38,
569 static const struct fsl_msi_feature vmpic_msi_feature = {
570 .fsl_pic_ip = FSL_PIC_IP_VMPIC,
574 static const struct of_device_id fsl_of_msi_ids[] = {
576 .compatible = "fsl,mpic-msi",
577 .data = &mpic_msi_feature,
580 .compatible = "fsl,mpic-msi-v4.3",
581 .data = &mpic_msi_feature,
584 .compatible = "fsl,ipic-msi",
585 .data = &ipic_msi_feature,
587 #ifdef CONFIG_EPAPR_PARAVIRT
589 .compatible = "fsl,vmpic-msi",
590 .data = &vmpic_msi_feature,
593 .compatible = "fsl,vmpic-msi-v4.3",
594 .data = &vmpic_msi_feature,
600 static struct platform_driver fsl_of_msi_driver = {
603 .of_match_table = fsl_of_msi_ids,
605 .probe = fsl_of_msi_probe,
606 .remove = fsl_of_msi_remove,
609 static __init int fsl_of_msi_init(void)
611 return platform_driver_register(&fsl_of_msi_driver);
614 subsys_initcall(fsl_of_msi_init);