2 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
4 * Author: Tony Li <tony.li@freescale.com>
5 * Jason Jin <Jason.jin@freescale.com>
7 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 of the
15 #include <linux/irq.h>
16 #include <linux/bootmem.h>
17 #include <linux/msi.h>
18 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/of_platform.h>
21 #include <sysdev/fsl_soc.h>
23 #include <asm/hw_irq.h>
24 #include <asm/ppc-pci.h>
28 struct fsl_msi_feature {
33 struct fsl_msi_cascade_data {
34 struct fsl_msi *msi_data;
38 static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
40 return in_be32(base + (reg >> 2));
44 * We do not need this actually. The MSIR register has been read once
45 * in the cascade interrupt. So, this MSI interrupt has been acked
47 static void fsl_msi_end_irq(unsigned int virq)
51 static struct irq_chip fsl_msi_chip = {
53 .unmask = unmask_msi_irq,
54 .ack = fsl_msi_end_irq,
58 static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
61 struct fsl_msi *msi_data = h->host_data;
62 struct irq_chip *chip = &fsl_msi_chip;
64 irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
66 set_irq_chip_data(virq, msi_data);
67 set_irq_chip_and_handler(virq, chip, handle_edge_irq);
72 static struct irq_host_ops fsl_msi_host_ops = {
73 .map = fsl_msi_host_map,
76 static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
80 rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
81 msi_data->irqhost->of_node);
85 rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
87 msi_bitmap_free(&msi_data->bitmap);
94 static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
96 if (type == PCI_CAP_ID_MSIX)
97 pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
102 static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
104 struct msi_desc *entry;
105 struct fsl_msi *msi_data;
107 list_for_each_entry(entry, &pdev->msi_list, list) {
108 if (entry->irq == NO_IRQ)
110 msi_data = get_irq_data(entry->irq);
111 set_irq_msi(entry->irq, NULL);
112 msi_bitmap_free_hwirqs(&msi_data->bitmap,
113 virq_to_hw(entry->irq), 1);
114 irq_dispose_mapping(entry->irq);
120 static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
122 struct fsl_msi *fsl_msi_data)
124 struct fsl_msi *msi_data = fsl_msi_data;
125 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
128 pci_bus_read_config_dword(hose->bus,
129 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
131 msg->address_lo = msi_data->msi_addr_lo + base;
132 msg->address_hi = msi_data->msi_addr_hi;
135 pr_debug("%s: allocated srs: %d, ibs: %d\n",
136 __func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
139 static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
141 int rc, hwirq = NO_IRQ;
143 struct msi_desc *entry;
145 struct fsl_msi *msi_data;
147 list_for_each_entry(entry, &pdev->msi_list, list) {
148 msi_data = get_irq_chip_data(entry->irq);
150 hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
153 pr_debug("%s: fail allocating msi interrupt\n",
158 virq = irq_create_mapping(msi_data->irqhost, hwirq);
160 if (virq == NO_IRQ) {
161 pr_debug("%s: fail mapping hwirq 0x%x\n",
163 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
167 set_irq_data(virq, msi_data);
168 set_irq_msi(virq, entry);
170 fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
171 write_msi_msg(virq, &msg);
179 static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
181 unsigned int cascade_irq;
182 struct fsl_msi *msi_data;
187 struct fsl_msi_cascade_data *cascade_data;
189 cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq);
190 msi_data = cascade_data->msi_data;
192 raw_spin_lock(&desc->lock);
193 if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
194 if (desc->chip->mask_ack)
195 desc->chip->mask_ack(irq);
197 desc->chip->mask(irq);
198 desc->chip->ack(irq);
202 if (unlikely(desc->status & IRQ_INPROGRESS))
205 msir_index = cascade_data->index;
207 if (msir_index >= NR_MSI_REG)
208 cascade_irq = NO_IRQ;
210 desc->status |= IRQ_INPROGRESS;
211 switch (msi_data->feature & FSL_PIC_IP_MASK) {
212 case FSL_PIC_IP_MPIC:
213 msir_value = fsl_msi_read(msi_data->msi_regs,
216 case FSL_PIC_IP_IPIC:
217 msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
222 intr_index = ffs(msir_value) - 1;
224 cascade_irq = irq_linear_revmap(msi_data->irqhost,
225 msir_index * IRQS_PER_MSI_REG +
226 intr_index + have_shift);
227 if (cascade_irq != NO_IRQ)
228 generic_handle_irq(cascade_irq);
229 have_shift += intr_index + 1;
230 msir_value = msir_value >> (intr_index + 1);
232 desc->status &= ~IRQ_INPROGRESS;
234 switch (msi_data->feature & FSL_PIC_IP_MASK) {
235 case FSL_PIC_IP_MPIC:
236 desc->chip->eoi(irq);
238 case FSL_PIC_IP_IPIC:
239 if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
240 desc->chip->unmask(irq);
244 raw_spin_unlock(&desc->lock);
247 static int __devinit fsl_of_msi_probe(struct of_device *dev,
248 const struct of_device_id *match)
256 struct fsl_msi_feature *features = match->data;
257 struct fsl_msi_cascade_data *cascade_data = NULL;
259 printk(KERN_DEBUG "Setting up Freescale MSI support\n");
261 msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
263 dev_err(&dev->dev, "No memory for MSI structure\n");
268 msi->irqhost = irq_alloc_host(dev->node, IRQ_HOST_MAP_LINEAR,
269 NR_MSI_IRQS, &fsl_msi_host_ops, 0);
271 if (msi->irqhost == NULL) {
272 dev_err(&dev->dev, "No memory for MSI irqhost\n");
277 /* Get the MSI reg base */
278 err = of_address_to_resource(dev->node, 0, &res);
280 dev_err(&dev->dev, "%s resource error!\n",
281 dev->node->full_name);
285 msi->msi_regs = ioremap(res.start, res.end - res.start + 1);
286 if (!msi->msi_regs) {
287 dev_err(&dev->dev, "ioremap problem failed\n");
291 msi->feature = features->fsl_pic_ip;
293 msi->irqhost->host_data = msi;
295 msi->msi_addr_hi = 0x0;
296 msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff);
298 rc = fsl_msi_init_allocator(msi);
300 dev_err(&dev->dev, "Error allocating MSI bitmap\n");
304 p = of_get_property(dev->node, "interrupts", &count);
306 dev_err(&dev->dev, "no interrupts property found on %s\n",
307 dev->node->full_name);
311 if (count % 8 != 0) {
312 dev_err(&dev->dev, "Malformed interrupts property on %s\n",
313 dev->node->full_name);
318 count /= sizeof(u32);
319 for (i = 0; i < count / 2; i++) {
322 virt_msir = irq_of_parse_and_map(dev->node, i);
323 if (virt_msir != NO_IRQ) {
324 cascade_data = kzalloc(
325 sizeof(struct fsl_msi_cascade_data),
329 "No memory for MSI cascade data\n");
333 cascade_data->index = i;
334 cascade_data->msi_data = msi;
335 set_irq_data(virt_msir, (void *)cascade_data);
336 set_irq_chained_handler(virt_msir, fsl_msi_cascade);
340 /* The multiple setting ppc_md.setup_msi_irqs will not harm things */
341 if (!ppc_md.setup_msi_irqs) {
342 ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
343 ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
344 ppc_md.msi_check_device = fsl_msi_check_device;
345 } else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
346 dev_err(&dev->dev, "Different MSI driver already installed!\n");
356 static const struct fsl_msi_feature mpic_msi_feature = {
357 .fsl_pic_ip = FSL_PIC_IP_MPIC,
358 .msiir_offset = 0x140,
361 static const struct fsl_msi_feature ipic_msi_feature = {
362 .fsl_pic_ip = FSL_PIC_IP_IPIC,
363 .msiir_offset = 0x38,
366 static const struct of_device_id fsl_of_msi_ids[] = {
368 .compatible = "fsl,mpic-msi",
369 .data = (void *)&mpic_msi_feature,
372 .compatible = "fsl,ipic-msi",
373 .data = (void *)&ipic_msi_feature,
378 static struct of_platform_driver fsl_of_msi_driver = {
380 .match_table = fsl_of_msi_ids,
381 .probe = fsl_of_msi_probe,
384 static __init int fsl_of_msi_init(void)
386 return of_register_platform_driver(&fsl_of_msi_driver);
389 subsys_initcall(fsl_of_msi_init);