2 * arch/powerpc/kernel/mpic.c
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 * Copyright 2010-2011 Freescale Semiconductor, Inc.
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive
21 #include <linux/types.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/irq.h>
25 #include <linux/smp.h>
26 #include <linux/interrupt.h>
27 #include <linux/bootmem.h>
28 #include <linux/spinlock.h>
29 #include <linux/pci.h>
30 #include <linux/slab.h>
31 #include <linux/syscore_ops.h>
32 #include <linux/ratelimit.h>
34 #include <asm/ptrace.h>
35 #include <asm/signal.h>
37 #include <asm/pgtable.h>
39 #include <asm/machdep.h>
46 #define DBG(fmt...) printk(fmt)
51 static struct mpic *mpics;
52 static struct mpic *mpic_primary;
53 static DEFINE_RAW_SPINLOCK(mpic_lock);
55 #ifdef CONFIG_PPC32 /* XXX for now */
56 #ifdef CONFIG_IRQ_ALL_CPUS
57 #define distribute_irqs (1)
59 #define distribute_irqs (0)
63 #ifdef CONFIG_MPIC_WEIRD
64 static u32 mpic_infos[][MPIC_IDX_END] = {
65 [0] = { /* Original OpenPIC compatible MPIC */
68 MPIC_GREG_GLOBAL_CONF_0,
70 MPIC_GREG_IPI_VECTOR_PRI_0,
77 MPIC_TIMER_CURRENT_CNT,
79 MPIC_TIMER_VECTOR_PRI,
80 MPIC_TIMER_DESTINATION,
84 MPIC_CPU_IPI_DISPATCH_0,
85 MPIC_CPU_IPI_DISPATCH_STRIDE,
86 MPIC_CPU_CURRENT_TASK_PRI,
95 MPIC_VECPRI_VECTOR_MASK,
96 MPIC_VECPRI_POLARITY_POSITIVE,
97 MPIC_VECPRI_POLARITY_NEGATIVE,
98 MPIC_VECPRI_SENSE_LEVEL,
99 MPIC_VECPRI_SENSE_EDGE,
100 MPIC_VECPRI_POLARITY_MASK,
101 MPIC_VECPRI_SENSE_MASK,
104 [1] = { /* Tsi108/109 PIC */
106 TSI108_GREG_FEATURE_0,
107 TSI108_GREG_GLOBAL_CONF_0,
108 TSI108_GREG_VENDOR_ID,
109 TSI108_GREG_IPI_VECTOR_PRI_0,
110 TSI108_GREG_IPI_STRIDE,
111 TSI108_GREG_SPURIOUS,
112 TSI108_GREG_TIMER_FREQ,
116 TSI108_TIMER_CURRENT_CNT,
117 TSI108_TIMER_BASE_CNT,
118 TSI108_TIMER_VECTOR_PRI,
119 TSI108_TIMER_DESTINATION,
123 TSI108_CPU_IPI_DISPATCH_0,
124 TSI108_CPU_IPI_DISPATCH_STRIDE,
125 TSI108_CPU_CURRENT_TASK_PRI,
133 TSI108_IRQ_VECTOR_PRI,
134 TSI108_VECPRI_VECTOR_MASK,
135 TSI108_VECPRI_POLARITY_POSITIVE,
136 TSI108_VECPRI_POLARITY_NEGATIVE,
137 TSI108_VECPRI_SENSE_LEVEL,
138 TSI108_VECPRI_SENSE_EDGE,
139 TSI108_VECPRI_POLARITY_MASK,
140 TSI108_VECPRI_SENSE_MASK,
141 TSI108_IRQ_DESTINATION
145 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
147 #else /* CONFIG_MPIC_WEIRD */
149 #define MPIC_INFO(name) MPIC_##name
151 #endif /* CONFIG_MPIC_WEIRD */
153 static inline unsigned int mpic_processor_id(struct mpic *mpic)
155 unsigned int cpu = 0;
157 if (!(mpic->flags & MPIC_SECONDARY))
158 cpu = hard_smp_processor_id();
164 * Register accessor functions
168 static inline u32 _mpic_read(enum mpic_reg_type type,
169 struct mpic_reg_bank *rb,
173 #ifdef CONFIG_PPC_DCR
174 case mpic_access_dcr:
175 return dcr_read(rb->dhost, reg);
177 case mpic_access_mmio_be:
178 return in_be32(rb->base + (reg >> 2));
179 case mpic_access_mmio_le:
181 return in_le32(rb->base + (reg >> 2));
185 static inline void _mpic_write(enum mpic_reg_type type,
186 struct mpic_reg_bank *rb,
187 unsigned int reg, u32 value)
190 #ifdef CONFIG_PPC_DCR
191 case mpic_access_dcr:
192 dcr_write(rb->dhost, reg, value);
195 case mpic_access_mmio_be:
196 out_be32(rb->base + (reg >> 2), value);
198 case mpic_access_mmio_le:
200 out_le32(rb->base + (reg >> 2), value);
205 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
207 enum mpic_reg_type type = mpic->reg_type;
208 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
209 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
211 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
212 type = mpic_access_mmio_be;
213 return _mpic_read(type, &mpic->gregs, offset);
216 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
218 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
219 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
221 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
224 static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
226 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
227 ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
230 offset += 0x1000 / 4;
232 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
235 static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
237 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
238 ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
241 offset += 0x1000 / 4;
243 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
246 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
248 unsigned int cpu = mpic_processor_id(mpic);
250 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
253 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
255 unsigned int cpu = mpic_processor_id(mpic);
257 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
260 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
262 unsigned int isu = src_no >> mpic->isu_shift;
263 unsigned int idx = src_no & mpic->isu_mask;
266 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
267 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
268 #ifdef CONFIG_MPIC_BROKEN_REGREAD
270 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
271 mpic->isu_reg0_shadow[src_no];
276 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
277 unsigned int reg, u32 value)
279 unsigned int isu = src_no >> mpic->isu_shift;
280 unsigned int idx = src_no & mpic->isu_mask;
282 _mpic_write(mpic->reg_type, &mpic->isus[isu],
283 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
285 #ifdef CONFIG_MPIC_BROKEN_REGREAD
287 mpic->isu_reg0_shadow[src_no] =
288 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
292 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
293 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
294 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
295 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
296 #define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
297 #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
298 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
299 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
300 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
301 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
305 * Low level utility functions
309 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
310 struct mpic_reg_bank *rb, unsigned int offset,
313 rb->base = ioremap(phys_addr + offset, size);
314 BUG_ON(rb->base == NULL);
317 #ifdef CONFIG_PPC_DCR
318 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
319 unsigned int offset, unsigned int size)
321 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
322 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
323 BUG_ON(!DCR_MAP_OK(rb->dhost));
326 static inline void mpic_map(struct mpic *mpic,
327 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
328 unsigned int offset, unsigned int size)
330 if (mpic->flags & MPIC_USES_DCR)
331 _mpic_map_dcr(mpic, rb, offset, size);
333 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
335 #else /* CONFIG_PPC_DCR */
336 #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
337 #endif /* !CONFIG_PPC_DCR */
341 /* Check if we have one of those nice broken MPICs with a flipped endian on
342 * reads from IPI registers
344 static void __init mpic_test_broken_ipi(struct mpic *mpic)
348 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
349 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
351 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
352 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
353 mpic->flags |= MPIC_BROKEN_IPI;
357 #ifdef CONFIG_MPIC_U3_HT_IRQS
359 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
360 * to force the edge setting on the MPIC and do the ack workaround.
362 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
364 if (source >= 128 || !mpic->fixups)
366 return mpic->fixups[source].base != NULL;
370 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
372 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
374 if (fixup->applebase) {
375 unsigned int soff = (fixup->index >> 3) & ~3;
376 unsigned int mask = 1U << (fixup->index & 0x1f);
377 writel(mask, fixup->applebase + soff);
379 raw_spin_lock(&mpic->fixup_lock);
380 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
381 writel(fixup->data, fixup->base + 4);
382 raw_spin_unlock(&mpic->fixup_lock);
386 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
389 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
393 if (fixup->base == NULL)
396 DBG("startup_ht_interrupt(0x%x) index: %d\n",
397 source, fixup->index);
398 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
399 /* Enable and configure */
400 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
401 tmp = readl(fixup->base + 4);
405 writel(tmp, fixup->base + 4);
406 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
409 /* use the lowest bit inverted to the actual HW,
410 * set if this fixup was enabled, clear otherwise */
411 mpic->save_data[source].fixup_data = tmp | 1;
415 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
417 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
421 if (fixup->base == NULL)
424 DBG("shutdown_ht_interrupt(0x%x)\n", source);
427 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
428 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
429 tmp = readl(fixup->base + 4);
431 writel(tmp, fixup->base + 4);
432 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
435 /* use the lowest bit inverted to the actual HW,
436 * set if this fixup was enabled, clear otherwise */
437 mpic->save_data[source].fixup_data = tmp & ~1;
441 #ifdef CONFIG_PCI_MSI
442 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
449 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
450 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
451 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
452 if (id == PCI_CAP_ID_HT) {
453 id = readb(devbase + pos + 3);
454 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
462 base = devbase + pos;
464 flags = readb(base + HT_MSI_FLAGS);
465 if (!(flags & HT_MSI_FLAGS_FIXED)) {
466 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
467 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
470 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
471 PCI_SLOT(devfn), PCI_FUNC(devfn),
472 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
474 if (!(flags & HT_MSI_FLAGS_ENABLE))
475 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
478 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
485 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
486 unsigned int devfn, u32 vdid)
493 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
494 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
495 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
496 if (id == PCI_CAP_ID_HT) {
497 id = readb(devbase + pos + 3);
498 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
505 base = devbase + pos;
506 writeb(0x01, base + 2);
507 n = (readl(base + 4) >> 16) & 0xff;
509 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
511 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
513 for (i = 0; i <= n; i++) {
514 writeb(0x10 + 2 * i, base + 2);
515 tmp = readl(base + 4);
516 irq = (tmp >> 16) & 0xff;
517 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
518 /* mask it , will be unmasked later */
520 writel(tmp, base + 4);
521 mpic->fixups[irq].index = i;
522 mpic->fixups[irq].base = base;
523 /* Apple HT PIC has a non-standard way of doing EOIs */
524 if ((vdid & 0xffff) == 0x106b)
525 mpic->fixups[irq].applebase = devbase + 0x60;
527 mpic->fixups[irq].applebase = NULL;
528 writeb(0x11 + 2 * i, base + 2);
529 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
534 static void __init mpic_scan_ht_pics(struct mpic *mpic)
537 u8 __iomem *cfgspace;
539 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
541 /* Allocate fixups array */
542 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
543 BUG_ON(mpic->fixups == NULL);
546 raw_spin_lock_init(&mpic->fixup_lock);
548 /* Map U3 config space. We assume all IO-APICs are on the primary bus
549 * so we only need to map 64kB.
551 cfgspace = ioremap(0xf2000000, 0x10000);
552 BUG_ON(cfgspace == NULL);
554 /* Now we scan all slots. We do a very quick scan, we read the header
555 * type, vendor ID and device ID only, that's plenty enough
557 for (devfn = 0; devfn < 0x100; devfn++) {
558 u8 __iomem *devbase = cfgspace + (devfn << 8);
559 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
560 u32 l = readl(devbase + PCI_VENDOR_ID);
563 DBG("devfn %x, l: %x\n", devfn, l);
565 /* If no device, skip */
566 if (l == 0xffffffff || l == 0x00000000 ||
567 l == 0x0000ffff || l == 0xffff0000)
569 /* Check if is supports capability lists */
570 s = readw(devbase + PCI_STATUS);
571 if (!(s & PCI_STATUS_CAP_LIST))
574 mpic_scan_ht_pic(mpic, devbase, devfn, l);
575 mpic_scan_ht_msi(mpic, devbase, devfn);
578 /* next device, if function 0 */
579 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
584 #else /* CONFIG_MPIC_U3_HT_IRQS */
586 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
591 static void __init mpic_scan_ht_pics(struct mpic *mpic)
595 #endif /* CONFIG_MPIC_U3_HT_IRQS */
597 /* Find an mpic associated with a given linux interrupt */
598 static struct mpic *mpic_find(unsigned int irq)
600 if (irq < NUM_ISA_INTERRUPTS)
603 return irq_get_chip_data(irq);
606 /* Determine if the linux irq is an IPI */
607 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
609 unsigned int src = virq_to_hw(irq);
611 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
614 /* Determine if the linux irq is a timer */
615 static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
617 unsigned int src = virq_to_hw(irq);
619 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
622 /* Convert a cpu mask from logical to physical cpu numbers. */
623 static inline u32 mpic_physmask(u32 cpumask)
628 for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
629 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
634 /* Get the mpic structure from the IPI number */
635 static inline struct mpic * mpic_from_ipi(struct irq_data *d)
637 return irq_data_get_irq_chip_data(d);
641 /* Get the mpic structure from the irq number */
642 static inline struct mpic * mpic_from_irq(unsigned int irq)
644 return irq_get_chip_data(irq);
647 /* Get the mpic structure from the irq data */
648 static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
650 return irq_data_get_irq_chip_data(d);
654 static inline void mpic_eoi(struct mpic *mpic)
656 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
657 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
661 * Linux descriptor level callbacks
665 void mpic_unmask_irq(struct irq_data *d)
667 unsigned int loops = 100000;
668 struct mpic *mpic = mpic_from_irq_data(d);
669 unsigned int src = irqd_to_hwirq(d);
671 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
673 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
674 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
676 /* make sure mask gets to controller before we return to user */
679 printk(KERN_ERR "%s: timeout on hwirq %u\n",
683 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
686 void mpic_mask_irq(struct irq_data *d)
688 unsigned int loops = 100000;
689 struct mpic *mpic = mpic_from_irq_data(d);
690 unsigned int src = irqd_to_hwirq(d);
692 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
694 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
695 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
698 /* make sure mask gets to controller before we return to user */
701 printk(KERN_ERR "%s: timeout on hwirq %u\n",
705 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
708 void mpic_end_irq(struct irq_data *d)
710 struct mpic *mpic = mpic_from_irq_data(d);
713 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
715 /* We always EOI on end_irq() even for edge interrupts since that
716 * should only lower the priority, the MPIC should have properly
717 * latched another edge interrupt coming in anyway
723 #ifdef CONFIG_MPIC_U3_HT_IRQS
725 static void mpic_unmask_ht_irq(struct irq_data *d)
727 struct mpic *mpic = mpic_from_irq_data(d);
728 unsigned int src = irqd_to_hwirq(d);
732 if (irqd_is_level_type(d))
733 mpic_ht_end_irq(mpic, src);
736 static unsigned int mpic_startup_ht_irq(struct irq_data *d)
738 struct mpic *mpic = mpic_from_irq_data(d);
739 unsigned int src = irqd_to_hwirq(d);
742 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
747 static void mpic_shutdown_ht_irq(struct irq_data *d)
749 struct mpic *mpic = mpic_from_irq_data(d);
750 unsigned int src = irqd_to_hwirq(d);
752 mpic_shutdown_ht_interrupt(mpic, src);
756 static void mpic_end_ht_irq(struct irq_data *d)
758 struct mpic *mpic = mpic_from_irq_data(d);
759 unsigned int src = irqd_to_hwirq(d);
762 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
764 /* We always EOI on end_irq() even for edge interrupts since that
765 * should only lower the priority, the MPIC should have properly
766 * latched another edge interrupt coming in anyway
769 if (irqd_is_level_type(d))
770 mpic_ht_end_irq(mpic, src);
773 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
777 static void mpic_unmask_ipi(struct irq_data *d)
779 struct mpic *mpic = mpic_from_ipi(d);
780 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
782 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
783 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
786 static void mpic_mask_ipi(struct irq_data *d)
788 /* NEVER disable an IPI... that's just plain wrong! */
791 static void mpic_end_ipi(struct irq_data *d)
793 struct mpic *mpic = mpic_from_ipi(d);
796 * IPIs are marked IRQ_PER_CPU. This has the side effect of
797 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
798 * applying to them. We EOI them late to avoid re-entering.
803 #endif /* CONFIG_SMP */
805 static void mpic_unmask_tm(struct irq_data *d)
807 struct mpic *mpic = mpic_from_irq_data(d);
808 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
810 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
811 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
815 static void mpic_mask_tm(struct irq_data *d)
817 struct mpic *mpic = mpic_from_irq_data(d);
818 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
820 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
824 int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
827 struct mpic *mpic = mpic_from_irq_data(d);
828 unsigned int src = irqd_to_hwirq(d);
830 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
831 int cpuid = irq_choose_cpu(cpumask);
833 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
835 u32 mask = cpumask_bits(cpumask)[0];
837 mask &= cpumask_bits(cpu_online_mask)[0];
839 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
840 mpic_physmask(mask));
846 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
848 /* Now convert sense value */
849 switch(type & IRQ_TYPE_SENSE_MASK) {
850 case IRQ_TYPE_EDGE_RISING:
851 return MPIC_INFO(VECPRI_SENSE_EDGE) |
852 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
853 case IRQ_TYPE_EDGE_FALLING:
854 case IRQ_TYPE_EDGE_BOTH:
855 return MPIC_INFO(VECPRI_SENSE_EDGE) |
856 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
857 case IRQ_TYPE_LEVEL_HIGH:
858 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
859 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
860 case IRQ_TYPE_LEVEL_LOW:
862 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
863 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
867 int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
869 struct mpic *mpic = mpic_from_irq_data(d);
870 unsigned int src = irqd_to_hwirq(d);
871 unsigned int vecpri, vold, vnew;
873 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
874 mpic, d->irq, src, flow_type);
876 if (src >= mpic->num_sources)
879 if (flow_type == IRQ_TYPE_NONE)
880 if (mpic->senses && src < mpic->senses_count)
881 flow_type = mpic->senses[src];
882 if (flow_type == IRQ_TYPE_NONE)
883 flow_type = IRQ_TYPE_LEVEL_LOW;
885 irqd_set_trigger_type(d, flow_type);
887 if (mpic_is_ht_interrupt(mpic, src))
888 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
889 MPIC_VECPRI_SENSE_EDGE;
891 vecpri = mpic_type_to_vecpri(mpic, flow_type);
893 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
894 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
895 MPIC_INFO(VECPRI_SENSE_MASK));
898 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
900 return IRQ_SET_MASK_OK_NOCOPY;
903 void mpic_set_vector(unsigned int virq, unsigned int vector)
905 struct mpic *mpic = mpic_from_irq(virq);
906 unsigned int src = virq_to_hw(virq);
909 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
910 mpic, virq, src, vector);
912 if (src >= mpic->num_sources)
915 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
916 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
918 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
921 void mpic_set_destination(unsigned int virq, unsigned int cpuid)
923 struct mpic *mpic = mpic_from_irq(virq);
924 unsigned int src = virq_to_hw(virq);
926 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
927 mpic, virq, src, cpuid);
929 if (src >= mpic->num_sources)
932 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
935 static struct irq_chip mpic_irq_chip = {
936 .irq_mask = mpic_mask_irq,
937 .irq_unmask = mpic_unmask_irq,
938 .irq_eoi = mpic_end_irq,
939 .irq_set_type = mpic_set_irq_type,
943 static struct irq_chip mpic_ipi_chip = {
944 .irq_mask = mpic_mask_ipi,
945 .irq_unmask = mpic_unmask_ipi,
946 .irq_eoi = mpic_end_ipi,
948 #endif /* CONFIG_SMP */
950 static struct irq_chip mpic_tm_chip = {
951 .irq_mask = mpic_mask_tm,
952 .irq_unmask = mpic_unmask_tm,
953 .irq_eoi = mpic_end_irq,
956 #ifdef CONFIG_MPIC_U3_HT_IRQS
957 static struct irq_chip mpic_irq_ht_chip = {
958 .irq_startup = mpic_startup_ht_irq,
959 .irq_shutdown = mpic_shutdown_ht_irq,
960 .irq_mask = mpic_mask_irq,
961 .irq_unmask = mpic_unmask_ht_irq,
962 .irq_eoi = mpic_end_ht_irq,
963 .irq_set_type = mpic_set_irq_type,
965 #endif /* CONFIG_MPIC_U3_HT_IRQS */
968 static int mpic_host_match(struct irq_domain *h, struct device_node *node)
970 /* Exact match, unless mpic node is NULL */
971 return h->of_node == NULL || h->of_node == node;
974 static int mpic_host_map(struct irq_domain *h, unsigned int virq,
977 struct mpic *mpic = h->host_data;
978 struct irq_chip *chip;
980 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
982 if (hw == mpic->spurious_vec)
984 if (mpic->protected && test_bit(hw, mpic->protected))
988 else if (hw >= mpic->ipi_vecs[0]) {
989 WARN_ON(mpic->flags & MPIC_SECONDARY);
991 DBG("mpic: mapping as IPI\n");
992 irq_set_chip_data(virq, mpic);
993 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
997 #endif /* CONFIG_SMP */
999 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1000 WARN_ON(mpic->flags & MPIC_SECONDARY);
1002 DBG("mpic: mapping as timer\n");
1003 irq_set_chip_data(virq, mpic);
1004 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1005 handle_fasteoi_irq);
1009 if (hw >= mpic->num_sources)
1012 mpic_msi_reserve_hwirq(mpic, hw);
1015 chip = &mpic->hc_irq;
1017 #ifdef CONFIG_MPIC_U3_HT_IRQS
1018 /* Check for HT interrupts, override vecpri */
1019 if (mpic_is_ht_interrupt(mpic, hw))
1020 chip = &mpic->hc_ht_irq;
1021 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1023 DBG("mpic: mapping to irq chip @%p\n", chip);
1025 irq_set_chip_data(virq, mpic);
1026 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1028 /* Set default irq type */
1029 irq_set_irq_type(virq, IRQ_TYPE_NONE);
1031 /* If the MPIC was reset, then all vectors have already been
1032 * initialized. Otherwise, a per source lazy initialization
1035 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1036 mpic_set_vector(virq, hw);
1037 mpic_set_destination(virq, mpic_processor_id(mpic));
1038 mpic_irq_set_priority(virq, 8);
1044 static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
1045 const u32 *intspec, unsigned int intsize,
1046 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1049 struct mpic *mpic = h->host_data;
1050 static unsigned char map_mpic_senses[4] = {
1051 IRQ_TYPE_EDGE_RISING,
1053 IRQ_TYPE_LEVEL_HIGH,
1054 IRQ_TYPE_EDGE_FALLING,
1057 *out_hwirq = intspec[0];
1058 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1060 * Freescale MPIC with extended intspec:
1061 * First two cells are as usual. Third specifies
1062 * an "interrupt type". Fourth is type-specific data.
1064 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1066 switch (intspec[2]) {
1068 case 1: /* no EISR/EIMR support for now, treat as shared IRQ */
1071 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1074 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1077 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1080 *out_hwirq = mpic->timer_vecs[intspec[0]];
1083 pr_debug("%s: unknown irq type %u\n",
1084 __func__, intspec[2]);
1088 *out_flags = map_mpic_senses[intspec[1] & 3];
1089 } else if (intsize > 1) {
1092 /* Apple invented a new race of encoding on machines with
1093 * an HT APIC. They encode, among others, the index within
1094 * the HT APIC. We don't care about it here since thankfully,
1095 * it appears that they have the APIC already properly
1096 * configured, and thus our current fixup code that reads the
1097 * APIC config works fine. However, we still need to mask out
1098 * bits in the specifier to make sure we only get bit 0 which
1099 * is the level/edge bit (the only sense bit exposed by Apple),
1100 * as their bit 1 means something else.
1102 if (machine_is(powermac))
1104 *out_flags = map_mpic_senses[intspec[1] & mask];
1106 *out_flags = IRQ_TYPE_NONE;
1108 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1109 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1114 /* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1115 static void mpic_cascade(unsigned int irq, struct irq_desc *desc)
1117 struct irq_chip *chip = irq_desc_get_chip(desc);
1118 struct mpic *mpic = irq_desc_get_handler_data(desc);
1121 BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1123 virq = mpic_get_one_irq(mpic);
1125 generic_handle_irq(virq);
1127 chip->irq_eoi(&desc->irq_data);
1130 static struct irq_domain_ops mpic_host_ops = {
1131 .match = mpic_host_match,
1132 .map = mpic_host_map,
1133 .xlate = mpic_host_xlate,
1137 * Exported functions
1140 struct mpic * __init mpic_alloc(struct device_node *node,
1141 phys_addr_t phys_addr,
1143 unsigned int isu_size,
1144 unsigned int irq_count,
1147 int i, psize, intvec_top;
1154 /* Default MPIC search parameters */
1155 static const struct of_device_id __initconst mpic_device_id[] = {
1156 { .type = "open-pic", },
1157 { .compatible = "open-pic", },
1162 * If we were not passed a device-tree node, then perform the default
1163 * search for standardized a standardized OpenPIC.
1166 node = of_node_get(node);
1168 node = of_find_matching_node(NULL, mpic_device_id);
1173 /* Pick the physical address from the device tree if unspecified */
1175 /* Check if it is DCR-based */
1176 if (of_get_property(node, "dcr-reg", NULL)) {
1177 flags |= MPIC_USES_DCR;
1180 if (of_address_to_resource(node, 0, &r))
1181 goto err_of_node_put;
1182 phys_addr = r.start;
1186 /* Read extra device-tree properties into the flags variable */
1187 if (of_get_property(node, "big-endian", NULL))
1188 flags |= MPIC_BIG_ENDIAN;
1189 if (of_get_property(node, "pic-no-reset", NULL))
1190 flags |= MPIC_NO_RESET;
1191 if (of_get_property(node, "single-cpu-affinity", NULL))
1192 flags |= MPIC_SINGLE_DEST_CPU;
1193 if (of_device_is_compatible(node, "fsl,mpic"))
1196 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1198 goto err_of_node_put;
1202 mpic->paddr = phys_addr;
1203 mpic->flags = flags;
1205 mpic->hc_irq = mpic_irq_chip;
1206 mpic->hc_irq.name = name;
1207 if (!(mpic->flags & MPIC_SECONDARY))
1208 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1209 #ifdef CONFIG_MPIC_U3_HT_IRQS
1210 mpic->hc_ht_irq = mpic_irq_ht_chip;
1211 mpic->hc_ht_irq.name = name;
1212 if (!(mpic->flags & MPIC_SECONDARY))
1213 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1214 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1217 mpic->hc_ipi = mpic_ipi_chip;
1218 mpic->hc_ipi.name = name;
1219 #endif /* CONFIG_SMP */
1221 mpic->hc_tm = mpic_tm_chip;
1222 mpic->hc_tm.name = name;
1224 mpic->num_sources = 0; /* so far */
1226 if (mpic->flags & MPIC_LARGE_VECTORS)
1231 mpic->timer_vecs[0] = intvec_top - 12;
1232 mpic->timer_vecs[1] = intvec_top - 11;
1233 mpic->timer_vecs[2] = intvec_top - 10;
1234 mpic->timer_vecs[3] = intvec_top - 9;
1235 mpic->timer_vecs[4] = intvec_top - 8;
1236 mpic->timer_vecs[5] = intvec_top - 7;
1237 mpic->timer_vecs[6] = intvec_top - 6;
1238 mpic->timer_vecs[7] = intvec_top - 5;
1239 mpic->ipi_vecs[0] = intvec_top - 4;
1240 mpic->ipi_vecs[1] = intvec_top - 3;
1241 mpic->ipi_vecs[2] = intvec_top - 2;
1242 mpic->ipi_vecs[3] = intvec_top - 1;
1243 mpic->spurious_vec = intvec_top;
1245 /* Look for protected sources */
1246 psrc = of_get_property(mpic->node, "protected-sources", &psize);
1248 /* Allocate a bitmap with one bit per interrupt */
1249 unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1);
1250 mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL);
1251 BUG_ON(mpic->protected == NULL);
1252 for (i = 0; i < psize/sizeof(u32); i++) {
1253 if (psrc[i] > intvec_top)
1255 __set_bit(psrc[i], mpic->protected);
1259 #ifdef CONFIG_MPIC_WEIRD
1260 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
1263 /* default register type */
1264 if (mpic->flags & MPIC_BIG_ENDIAN)
1265 mpic->reg_type = mpic_access_mmio_be;
1267 mpic->reg_type = mpic_access_mmio_le;
1270 * An MPIC with a "dcr-reg" property must be accessed that way, but
1271 * only if the kernel includes DCR support.
1273 #ifdef CONFIG_PPC_DCR
1274 if (mpic->flags & MPIC_USES_DCR)
1275 mpic->reg_type = mpic_access_dcr;
1277 BUG_ON(mpic->flags & MPIC_USES_DCR);
1280 /* Map the global registers */
1281 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1282 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1286 /* When using a device-node, reset requests are only honored if the MPIC
1287 * is allowed to reset.
1289 if (!(mpic->flags & MPIC_NO_RESET)) {
1290 printk(KERN_DEBUG "mpic: Resetting\n");
1291 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1292 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1293 | MPIC_GREG_GCONF_RESET);
1294 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1295 & MPIC_GREG_GCONF_RESET)
1300 if (mpic->flags & MPIC_ENABLE_COREINT)
1301 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1302 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1303 | MPIC_GREG_GCONF_COREINT);
1305 if (mpic->flags & MPIC_ENABLE_MCK)
1306 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1307 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1308 | MPIC_GREG_GCONF_MCK);
1311 * The MPIC driver will crash if there are more cores than we
1312 * can initialize, so we may as well catch that problem here.
1314 BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
1316 /* Map the per-CPU registers */
1317 for_each_possible_cpu(i) {
1318 unsigned int cpu = get_hard_smp_processor_id(i);
1320 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1321 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1326 * Read feature register. For non-ISU MPICs, num sources as well. On
1327 * ISU MPICs, sources are counted as ISUs are added
1329 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1332 * By default, the last source number comes from the MPIC, but the
1333 * device-tree and board support code can override it on buggy hw.
1334 * If we get passed an isu_size (multi-isu MPIC) then we use that
1335 * as a default instead of the value read from the HW.
1337 last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1338 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;
1340 last_irq = isu_size * MPIC_MAX_ISU - 1;
1341 of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
1343 last_irq = irq_count - 1;
1345 /* Initialize main ISU if none provided */
1347 isu_size = last_irq + 1;
1348 mpic->num_sources = isu_size;
1349 mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1350 MPIC_INFO(IRQ_BASE),
1351 MPIC_INFO(IRQ_STRIDE) * isu_size);
1354 mpic->isu_size = isu_size;
1355 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1356 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1358 mpic->irqhost = irq_domain_add_linear(mpic->node,
1360 &mpic_host_ops, mpic);
1363 * FIXME: The code leaks the MPIC object and mappings here; this
1364 * is very unlikely to fail but it ought to be fixed anyways.
1366 if (mpic->irqhost == NULL)
1369 /* Display version */
1370 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1384 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1386 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1387 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1388 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1393 if (!(mpic->flags & MPIC_SECONDARY)) {
1394 mpic_primary = mpic;
1395 irq_set_default_host(mpic->irqhost);
1405 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1408 unsigned int isu_first = isu_num * mpic->isu_size;
1410 BUG_ON(isu_num >= MPIC_MAX_ISU);
1413 paddr, &mpic->isus[isu_num], 0,
1414 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1416 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1417 mpic->num_sources = isu_first + mpic->isu_size;
1420 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1422 mpic->senses = senses;
1423 mpic->senses_count = count;
1426 void __init mpic_init(struct mpic *mpic)
1430 BUG_ON(mpic->num_sources == 0);
1432 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1434 /* Set current processor priority to max */
1435 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1437 /* Initialize timers to our reserved vectors and mask them for now */
1438 for (i = 0; i < 4; i++) {
1439 mpic_write(mpic->tmregs,
1440 i * MPIC_INFO(TIMER_STRIDE) +
1441 MPIC_INFO(TIMER_DESTINATION),
1442 1 << hard_smp_processor_id());
1443 mpic_write(mpic->tmregs,
1444 i * MPIC_INFO(TIMER_STRIDE) +
1445 MPIC_INFO(TIMER_VECTOR_PRI),
1447 (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1448 (mpic->timer_vecs[0] + i));
1451 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1452 mpic_test_broken_ipi(mpic);
1453 for (i = 0; i < 4; i++) {
1456 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1457 (mpic->ipi_vecs[0] + i));
1460 /* Do the HT PIC fixups on U3 broken mpic */
1461 DBG("MPIC flags: %x\n", mpic->flags);
1462 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1463 mpic_scan_ht_pics(mpic);
1464 mpic_u3msi_init(mpic);
1467 mpic_pasemi_msi_init(mpic);
1469 cpu = mpic_processor_id(mpic);
1471 if (!(mpic->flags & MPIC_NO_RESET)) {
1472 for (i = 0; i < mpic->num_sources; i++) {
1473 /* start with vector = source number, and masked */
1474 u32 vecpri = MPIC_VECPRI_MASK | i |
1475 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1477 /* check if protected */
1478 if (mpic->protected && test_bit(i, mpic->protected))
1481 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1482 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1486 /* Init spurious vector */
1487 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1489 /* Disable 8259 passthrough, if supported */
1490 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1491 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1492 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1493 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1495 if (mpic->flags & MPIC_NO_BIAS)
1496 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1497 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1498 | MPIC_GREG_GCONF_NO_BIAS);
1500 /* Set current processor priority to 0 */
1501 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1504 /* allocate memory to save mpic state */
1505 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1507 BUG_ON(mpic->save_data == NULL);
1510 /* Check if this MPIC is chained from a parent interrupt controller */
1511 if (mpic->flags & MPIC_SECONDARY) {
1512 int virq = irq_of_parse_and_map(mpic->node, 0);
1513 if (virq != NO_IRQ) {
1514 printk(KERN_INFO "%s: hooking up to IRQ %d\n",
1515 mpic->node->full_name, virq);
1516 irq_set_handler_data(virq, mpic);
1517 irq_set_chained_handler(virq, &mpic_cascade);
1522 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1526 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1527 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1528 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1529 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1532 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1534 unsigned long flags;
1537 raw_spin_lock_irqsave(&mpic_lock, flags);
1538 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1540 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1542 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1543 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1544 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1547 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1549 struct mpic *mpic = mpic_find(irq);
1550 unsigned int src = virq_to_hw(irq);
1551 unsigned long flags;
1557 raw_spin_lock_irqsave(&mpic_lock, flags);
1558 if (mpic_is_ipi(mpic, irq)) {
1559 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1560 ~MPIC_VECPRI_PRIORITY_MASK;
1561 mpic_ipi_write(src - mpic->ipi_vecs[0],
1562 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1563 } else if (mpic_is_tm(mpic, irq)) {
1564 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1565 ~MPIC_VECPRI_PRIORITY_MASK;
1566 mpic_tm_write(src - mpic->timer_vecs[0],
1567 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1569 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1570 & ~MPIC_VECPRI_PRIORITY_MASK;
1571 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1572 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1574 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1577 void mpic_setup_this_cpu(void)
1580 struct mpic *mpic = mpic_primary;
1581 unsigned long flags;
1582 u32 msk = 1 << hard_smp_processor_id();
1585 BUG_ON(mpic == NULL);
1587 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1589 raw_spin_lock_irqsave(&mpic_lock, flags);
1591 /* let the mpic know we want intrs. default affinity is 0xffffffff
1592 * until changed via /proc. That's how it's done on x86. If we want
1593 * it differently, then we should make sure we also change the default
1594 * values of irq_desc[].affinity in irq.c.
1596 if (distribute_irqs) {
1597 for (i = 0; i < mpic->num_sources ; i++)
1598 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1599 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1602 /* Set current processor priority to 0 */
1603 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1605 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1606 #endif /* CONFIG_SMP */
1609 int mpic_cpu_get_priority(void)
1611 struct mpic *mpic = mpic_primary;
1613 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1616 void mpic_cpu_set_priority(int prio)
1618 struct mpic *mpic = mpic_primary;
1620 prio &= MPIC_CPU_TASKPRI_MASK;
1621 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1624 void mpic_teardown_this_cpu(int secondary)
1626 struct mpic *mpic = mpic_primary;
1627 unsigned long flags;
1628 u32 msk = 1 << hard_smp_processor_id();
1631 BUG_ON(mpic == NULL);
1633 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1634 raw_spin_lock_irqsave(&mpic_lock, flags);
1636 /* let the mpic know we don't want intrs. */
1637 for (i = 0; i < mpic->num_sources ; i++)
1638 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1639 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1641 /* Set current processor priority to max */
1642 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1643 /* We need to EOI the IPI since not all platforms reset the MPIC
1644 * on boot and new interrupts wouldn't get delivered otherwise.
1648 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1652 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1656 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1658 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1660 if (unlikely(src == mpic->spurious_vec)) {
1661 if (mpic->flags & MPIC_SPV_EOI)
1665 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1666 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1667 mpic->name, (int)src);
1672 return irq_linear_revmap(mpic->irqhost, src);
1675 unsigned int mpic_get_one_irq(struct mpic *mpic)
1677 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1680 unsigned int mpic_get_irq(void)
1682 struct mpic *mpic = mpic_primary;
1684 BUG_ON(mpic == NULL);
1686 return mpic_get_one_irq(mpic);
1689 unsigned int mpic_get_coreint_irq(void)
1692 struct mpic *mpic = mpic_primary;
1695 BUG_ON(mpic == NULL);
1697 src = mfspr(SPRN_EPR);
1699 if (unlikely(src == mpic->spurious_vec)) {
1700 if (mpic->flags & MPIC_SPV_EOI)
1704 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1705 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1706 mpic->name, (int)src);
1710 return irq_linear_revmap(mpic->irqhost, src);
1716 unsigned int mpic_get_mcirq(void)
1718 struct mpic *mpic = mpic_primary;
1720 BUG_ON(mpic == NULL);
1722 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1726 void mpic_request_ipis(void)
1728 struct mpic *mpic = mpic_primary;
1730 BUG_ON(mpic == NULL);
1732 printk(KERN_INFO "mpic: requesting IPIs...\n");
1734 for (i = 0; i < 4; i++) {
1735 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1736 mpic->ipi_vecs[0] + i);
1737 if (vipi == NO_IRQ) {
1738 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1741 smp_request_message_ipi(vipi, i);
1745 void smp_mpic_message_pass(int cpu, int msg)
1747 struct mpic *mpic = mpic_primary;
1750 BUG_ON(mpic == NULL);
1752 /* make sure we're sending something that translates to an IPI */
1753 if ((unsigned int)msg > 3) {
1754 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1755 smp_processor_id(), msg);
1760 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1763 physmask = 1 << get_hard_smp_processor_id(cpu);
1765 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1766 msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1769 int __init smp_mpic_probe(void)
1773 DBG("smp_mpic_probe()...\n");
1775 nr_cpus = cpumask_weight(cpu_possible_mask);
1777 DBG("nr_cpus: %d\n", nr_cpus);
1780 mpic_request_ipis();
1785 void __devinit smp_mpic_setup_cpu(int cpu)
1787 mpic_setup_this_cpu();
1790 void mpic_reset_core(int cpu)
1792 struct mpic *mpic = mpic_primary;
1794 int cpuid = get_hard_smp_processor_id(cpu);
1797 /* Set target bit for core reset */
1798 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1799 pir |= (1 << cpuid);
1800 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1801 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1803 /* Restore target bit after reset complete */
1804 pir &= ~(1 << cpuid);
1805 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1806 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1808 /* Perform 15 EOI on each reset core to clear pending interrupts.
1809 * This is required for FSL CoreNet based devices */
1810 if (mpic->flags & MPIC_FSL) {
1811 for (i = 0; i < 15; i++) {
1812 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1817 #endif /* CONFIG_SMP */
1820 static void mpic_suspend_one(struct mpic *mpic)
1824 for (i = 0; i < mpic->num_sources; i++) {
1825 mpic->save_data[i].vecprio =
1826 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1827 mpic->save_data[i].dest =
1828 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1832 static int mpic_suspend(void)
1834 struct mpic *mpic = mpics;
1837 mpic_suspend_one(mpic);
1844 static void mpic_resume_one(struct mpic *mpic)
1848 for (i = 0; i < mpic->num_sources; i++) {
1849 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1850 mpic->save_data[i].vecprio);
1851 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1852 mpic->save_data[i].dest);
1854 #ifdef CONFIG_MPIC_U3_HT_IRQS
1856 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1859 /* we use the lowest bit in an inverted meaning */
1860 if ((mpic->save_data[i].fixup_data & 1) == 0)
1863 /* Enable and configure */
1864 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1866 writel(mpic->save_data[i].fixup_data & ~1,
1871 } /* end for loop */
1874 static void mpic_resume(void)
1876 struct mpic *mpic = mpics;
1879 mpic_resume_one(mpic);
1884 static struct syscore_ops mpic_syscore_ops = {
1885 .resume = mpic_resume,
1886 .suspend = mpic_suspend,
1889 static int mpic_init_sys(void)
1891 register_syscore_ops(&mpic_syscore_ops);
1895 device_initcall(mpic_init_sys);