4 * Copyright 2013 Freescale Semiconductor, Inc.
5 * Author: Dongsheng Wang <Dongsheng.Wang@freescale.com>
6 * Li Yang <leoli@freescale.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/errno.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/of_irq.h>
25 #include <linux/syscore_ops.h>
26 #include <sysdev/fsl_soc.h>
29 #include <asm/mpic_timer.h>
31 #define FSL_GLOBAL_TIMER 0x1
34 * Divide by 64 0x00000300
35 * Divide by 32 0x00000200
36 * Divide by 16 0x00000100
37 * Divide by 8 0x00000000 (Hardware default div)
39 #define MPIC_TIMER_TCR_CLKDIV 0x00000300
41 #define MPIC_TIMER_TCR_ROVR_OFFSET 24
43 #define TIMER_STOP 0x80000000
44 #define TIMERS_PER_GROUP 4
45 #define MAX_TICKS (~0U >> 1)
46 #define MAX_TICKS_CASCADE (~0U)
47 #define TIMER_OFFSET(num) (1 << (TIMERS_PER_GROUP - 1 - num))
49 /* tv_usec should be less than ONE_SECOND, otherwise use tv_sec */
50 #define ONE_SECOND 1000000
64 u32 tcr_value; /* TCR register: CASC & ROVR value */
65 unsigned int cascade_map; /* cascade map */
66 unsigned int timer_num; /* cascade control timer */
69 struct timer_group_priv {
70 struct timer_regs __iomem *regs;
71 struct mpic_timer timer[TIMERS_PER_GROUP];
72 struct list_head node;
73 unsigned int timerfreq;
77 void __iomem *group_tcr;
80 static struct cascade_priv cascade_timer[] = {
81 /* cascade timer 0 and 1 */
83 /* cascade timer 1 and 2 */
85 /* cascade timer 2 and 3 */
89 static LIST_HEAD(timer_group_list);
91 static void convert_ticks_to_time(struct timer_group_priv *priv,
92 const u64 ticks, struct timeval *time)
96 time->tv_sec = (__kernel_time_t)div_u64(ticks, priv->timerfreq);
97 tmp_sec = (u64)time->tv_sec * (u64)priv->timerfreq;
99 time->tv_usec = (__kernel_suseconds_t)
100 div_u64((ticks - tmp_sec) * 1000000, priv->timerfreq);
105 /* the time set by the user is converted to "ticks" */
106 static int convert_time_to_ticks(struct timer_group_priv *priv,
107 const struct timeval *time, u64 *ticks)
109 u64 max_value; /* prevent u64 overflow */
116 max_value = div_u64(ULLONG_MAX, priv->timerfreq);
118 if (time->tv_sec > max_value ||
119 (time->tv_sec == max_value && time->tv_usec > 0))
122 tmp_sec = (u64)time->tv_sec * (u64)priv->timerfreq;
125 tmp_ms = time->tv_usec / 1000;
126 tmp_ms = div_u64((u64)tmp_ms * (u64)priv->timerfreq, 1000);
129 tmp_us = time->tv_usec % 1000;
130 tmp_us = div_u64((u64)tmp_us * (u64)priv->timerfreq, 1000000);
138 /* detect whether there is a cascade timer available */
139 static struct mpic_timer *detect_idle_cascade_timer(
140 struct timer_group_priv *priv)
142 struct cascade_priv *casc_priv;
144 unsigned int array_size = ARRAY_SIZE(cascade_timer);
149 casc_priv = cascade_timer;
150 for (i = 0; i < array_size; i++) {
151 spin_lock_irqsave(&priv->lock, flags);
152 map = casc_priv->cascade_map & priv->idle;
153 if (map == casc_priv->cascade_map) {
154 num = casc_priv->timer_num;
155 priv->timer[num].cascade_handle = casc_priv;
158 priv->idle &= ~casc_priv->cascade_map;
159 spin_unlock_irqrestore(&priv->lock, flags);
160 return &priv->timer[num];
162 spin_unlock_irqrestore(&priv->lock, flags);
169 static int set_cascade_timer(struct timer_group_priv *priv, u64 ticks,
172 struct cascade_priv *casc_priv;
177 /* set group tcr reg for cascade */
178 casc_priv = priv->timer[num].cascade_handle;
182 tcr = casc_priv->tcr_value |
183 (casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET);
184 setbits32(priv->group_tcr, tcr);
186 tmp_ticks = div_u64_rem(ticks, MAX_TICKS_CASCADE, &rem_ticks);
188 out_be32(&priv->regs[num].gtccr, 0);
189 out_be32(&priv->regs[num].gtbcr, tmp_ticks | TIMER_STOP);
191 out_be32(&priv->regs[num - 1].gtccr, 0);
192 out_be32(&priv->regs[num - 1].gtbcr, rem_ticks);
197 static struct mpic_timer *get_cascade_timer(struct timer_group_priv *priv,
200 struct mpic_timer *allocated_timer;
202 /* Two cascade timers: Support the maximum time */
203 const u64 max_ticks = (u64)MAX_TICKS * (u64)MAX_TICKS_CASCADE;
206 if (ticks > max_ticks)
209 /* detect idle timer */
210 allocated_timer = detect_idle_cascade_timer(priv);
211 if (!allocated_timer)
214 /* set ticks to timer */
215 ret = set_cascade_timer(priv, ticks, allocated_timer->num);
219 return allocated_timer;
222 static struct mpic_timer *get_timer(const struct timeval *time)
224 struct timer_group_priv *priv;
225 struct mpic_timer *timer;
233 list_for_each_entry(priv, &timer_group_list, node) {
234 ret = convert_time_to_ticks(priv, time, &ticks);
238 if (ticks > MAX_TICKS) {
239 if (!(priv->flags & FSL_GLOBAL_TIMER))
242 timer = get_cascade_timer(priv, ticks);
249 for (i = 0; i < TIMERS_PER_GROUP; i++) {
250 /* one timer: Reverse allocation */
251 num = TIMERS_PER_GROUP - 1 - i;
252 spin_lock_irqsave(&priv->lock, flags);
253 if (priv->idle & (1 << i)) {
255 priv->idle &= ~(1 << i);
256 /* set ticks & stop timer */
257 out_be32(&priv->regs[num].gtbcr,
259 out_be32(&priv->regs[num].gtccr, 0);
260 priv->timer[num].cascade_handle = NULL;
261 spin_unlock_irqrestore(&priv->lock, flags);
262 return &priv->timer[num];
264 spin_unlock_irqrestore(&priv->lock, flags);
272 * mpic_start_timer - start hardware timer
273 * @handle: the timer to be started.
275 * It will do ->fn(->dev) callback from the hardware interrupt at
276 * the ->timeval point in the future.
278 void mpic_start_timer(struct mpic_timer *handle)
280 struct timer_group_priv *priv = container_of(handle,
281 struct timer_group_priv, timer[handle->num]);
283 clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
285 EXPORT_SYMBOL(mpic_start_timer);
288 * mpic_stop_timer - stop hardware timer
289 * @handle: the timer to be stoped
291 * The timer periodically generates an interrupt. Unless user stops the timer.
293 void mpic_stop_timer(struct mpic_timer *handle)
295 struct timer_group_priv *priv = container_of(handle,
296 struct timer_group_priv, timer[handle->num]);
297 struct cascade_priv *casc_priv;
299 setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
301 casc_priv = priv->timer[handle->num].cascade_handle;
303 out_be32(&priv->regs[handle->num].gtccr, 0);
304 out_be32(&priv->regs[handle->num - 1].gtccr, 0);
306 out_be32(&priv->regs[handle->num].gtccr, 0);
309 EXPORT_SYMBOL(mpic_stop_timer);
312 * mpic_get_remain_time - get timer time
313 * @handle: the timer to be selected.
314 * @time: time for timer
316 * Query timer remaining time.
318 void mpic_get_remain_time(struct mpic_timer *handle, struct timeval *time)
320 struct timer_group_priv *priv = container_of(handle,
321 struct timer_group_priv, timer[handle->num]);
322 struct cascade_priv *casc_priv;
327 casc_priv = priv->timer[handle->num].cascade_handle;
329 tmp_ticks = in_be32(&priv->regs[handle->num].gtccr);
330 ticks = ((u64)tmp_ticks & UINT_MAX) * (u64)MAX_TICKS_CASCADE;
331 tmp_ticks = in_be32(&priv->regs[handle->num - 1].gtccr);
334 ticks = in_be32(&priv->regs[handle->num].gtccr);
337 convert_ticks_to_time(priv, ticks, time);
339 EXPORT_SYMBOL(mpic_get_remain_time);
342 * mpic_free_timer - free hardware timer
343 * @handle: the timer to be removed.
347 * Note: can not be used in interrupt context.
349 void mpic_free_timer(struct mpic_timer *handle)
351 struct timer_group_priv *priv = container_of(handle,
352 struct timer_group_priv, timer[handle->num]);
354 struct cascade_priv *casc_priv;
357 mpic_stop_timer(handle);
359 casc_priv = priv->timer[handle->num].cascade_handle;
361 free_irq(priv->timer[handle->num].irq, priv->timer[handle->num].dev);
363 spin_lock_irqsave(&priv->lock, flags);
366 tcr = casc_priv->tcr_value | (casc_priv->tcr_value <<
367 MPIC_TIMER_TCR_ROVR_OFFSET);
368 clrbits32(priv->group_tcr, tcr);
369 priv->idle |= casc_priv->cascade_map;
370 priv->timer[handle->num].cascade_handle = NULL;
372 priv->idle |= TIMER_OFFSET(handle->num);
374 spin_unlock_irqrestore(&priv->lock, flags);
376 EXPORT_SYMBOL(mpic_free_timer);
379 * mpic_request_timer - get a hardware timer
380 * @fn: interrupt handler function
381 * @dev: callback function of the data
382 * @time: time for timer
384 * This executes the "request_irq", returning NULL
385 * else "handle" on success.
387 struct mpic_timer *mpic_request_timer(irq_handler_t fn, void *dev,
388 const struct timeval *time)
390 struct mpic_timer *allocated_timer;
393 if (list_empty(&timer_group_list))
396 if (!(time->tv_sec + time->tv_usec) ||
397 time->tv_sec < 0 || time->tv_usec < 0)
400 if (time->tv_usec > ONE_SECOND)
403 allocated_timer = get_timer(time);
404 if (!allocated_timer)
407 ret = request_irq(allocated_timer->irq, fn,
408 IRQF_TRIGGER_LOW, "global-timer", dev);
410 mpic_free_timer(allocated_timer);
414 allocated_timer->dev = dev;
416 return allocated_timer;
418 EXPORT_SYMBOL(mpic_request_timer);
420 static int timer_group_get_freq(struct device_node *np,
421 struct timer_group_priv *priv)
425 if (priv->flags & FSL_GLOBAL_TIMER) {
426 struct device_node *dn;
428 dn = of_find_compatible_node(NULL, NULL, "fsl,mpic");
430 of_property_read_u32(dn, "clock-frequency",
436 if (priv->timerfreq <= 0)
439 if (priv->flags & FSL_GLOBAL_TIMER) {
440 div = (1 << (MPIC_TIMER_TCR_CLKDIV >> 8)) * 8;
441 priv->timerfreq /= div;
447 static int timer_group_get_irq(struct device_node *np,
448 struct timer_group_priv *priv)
450 const u32 all_timer[] = { 0, TIMERS_PER_GROUP };
457 unsigned int irq_index = 0;
461 p = of_get_property(np, "fsl,available-ranges", &len);
462 if (p && len % (2 * sizeof(u32)) != 0) {
463 pr_err("%s: malformed available-ranges property.\n",
470 len = sizeof(all_timer);
473 len /= 2 * sizeof(u32);
475 for (i = 0; i < len; i++) {
477 count = p[i * 2 + 1];
478 for (j = 0; j < count; j++) {
479 irq = irq_of_parse_and_map(np, irq_index);
481 pr_err("%s: irq parse and map failed.\n",
487 priv->idle |= TIMER_OFFSET((offset + j));
488 priv->timer[offset + j].irq = irq;
489 priv->timer[offset + j].num = offset + j;
497 static void timer_group_init(struct device_node *np)
499 struct timer_group_priv *priv;
503 priv = kzalloc(sizeof(struct timer_group_priv), GFP_KERNEL);
505 pr_err("%s: cannot allocate memory for group.\n",
510 if (of_device_is_compatible(np, "fsl,mpic-global-timer"))
511 priv->flags |= FSL_GLOBAL_TIMER;
513 priv->regs = of_iomap(np, i++);
515 pr_err("%s: cannot ioremap timer register address.\n",
520 if (priv->flags & FSL_GLOBAL_TIMER) {
521 priv->group_tcr = of_iomap(np, i++);
522 if (!priv->group_tcr) {
523 pr_err("%s: cannot ioremap tcr address.\n",
529 ret = timer_group_get_freq(np, priv);
531 pr_err("%s: cannot get timer frequency.\n", np->full_name);
535 ret = timer_group_get_irq(np, priv);
537 pr_err("%s: cannot get timer irqs.\n", np->full_name);
541 spin_lock_init(&priv->lock);
543 /* Init FSL timer hardware */
544 if (priv->flags & FSL_GLOBAL_TIMER)
545 setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
547 list_add_tail(&priv->node, &timer_group_list);
556 iounmap(priv->group_tcr);
561 static void mpic_timer_resume(void)
563 struct timer_group_priv *priv;
565 list_for_each_entry(priv, &timer_group_list, node) {
566 /* Init FSL timer hardware */
567 if (priv->flags & FSL_GLOBAL_TIMER)
568 setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
572 static const struct of_device_id mpic_timer_ids[] = {
573 { .compatible = "fsl,mpic-global-timer", },
577 static struct syscore_ops mpic_timer_syscore_ops = {
578 .resume = mpic_timer_resume,
581 static int __init mpic_timer_init(void)
583 struct device_node *np = NULL;
585 for_each_matching_node(np, mpic_timer_ids)
586 timer_group_init(np);
588 register_syscore_ops(&mpic_timer_syscore_ops);
590 if (list_empty(&timer_group_list))
595 subsys_initcall(mpic_timer_init);