4 * Copyright (c) 2008 Harris Corporation
5 * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6 * Copyright (c) MontaVista Software, Inc. 2008.
8 * Author: Steve Falco <sfalco@harris.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2
12 * as published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/spinlock.h>
29 #include <linux/of_gpio.h>
30 #include <linux/gpio/driver.h>
31 #include <linux/types.h>
32 #include <linux/slab.h>
34 #define GPIO_MASK(gpio) (0x80000000 >> (gpio))
35 #define GPIO_MASK2(gpio) (0xc0000000 >> ((gpio) * 2))
37 /* Physical GPIO register layout */
59 struct ppc4xx_gpio_chip {
60 struct of_mm_gpio_chip mm_gc;
65 * GPIO LIB API implementation for GPIOs
67 * There are a maximum of 32 gpios in each gpio controller.
70 static int ppc4xx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
72 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
73 struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
75 return !!(in_be32(®s->ir) & GPIO_MASK(gpio));
79 __ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
81 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
82 struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
85 setbits32(®s->or, GPIO_MASK(gpio));
87 clrbits32(®s->or, GPIO_MASK(gpio));
91 ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
93 struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc);
96 spin_lock_irqsave(&chip->lock, flags);
98 __ppc4xx_gpio_set(gc, gpio, val);
100 spin_unlock_irqrestore(&chip->lock, flags);
102 pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
105 static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
107 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
108 struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc);
109 struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
112 spin_lock_irqsave(&chip->lock, flags);
114 /* Disable open-drain function */
115 clrbits32(®s->odr, GPIO_MASK(gpio));
118 clrbits32(®s->tcr, GPIO_MASK(gpio));
120 /* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */
122 clrbits32(®s->osrl, GPIO_MASK2(gpio));
123 clrbits32(®s->tsrl, GPIO_MASK2(gpio));
125 clrbits32(®s->osrh, GPIO_MASK2(gpio));
126 clrbits32(®s->tsrh, GPIO_MASK2(gpio));
129 spin_unlock_irqrestore(&chip->lock, flags);
135 ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
137 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
138 struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc);
139 struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
142 spin_lock_irqsave(&chip->lock, flags);
144 /* First set initial value */
145 __ppc4xx_gpio_set(gc, gpio, val);
147 /* Disable open-drain function */
148 clrbits32(®s->odr, GPIO_MASK(gpio));
151 setbits32(®s->tcr, GPIO_MASK(gpio));
153 /* Bits 0-15 use TSRL, bits 16-31 use TSRH */
155 clrbits32(®s->osrl, GPIO_MASK2(gpio));
156 clrbits32(®s->tsrl, GPIO_MASK2(gpio));
158 clrbits32(®s->osrh, GPIO_MASK2(gpio));
159 clrbits32(®s->tsrh, GPIO_MASK2(gpio));
162 spin_unlock_irqrestore(&chip->lock, flags);
164 pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
169 static int __init ppc4xx_add_gpiochips(void)
171 struct device_node *np;
173 for_each_compatible_node(np, NULL, "ibm,ppc4xx-gpio") {
175 struct ppc4xx_gpio_chip *ppc4xx_gc;
176 struct of_mm_gpio_chip *mm_gc;
177 struct gpio_chip *gc;
179 ppc4xx_gc = kzalloc(sizeof(*ppc4xx_gc), GFP_KERNEL);
185 spin_lock_init(&ppc4xx_gc->lock);
187 mm_gc = &ppc4xx_gc->mm_gc;
191 gc->direction_input = ppc4xx_gpio_dir_in;
192 gc->direction_output = ppc4xx_gpio_dir_out;
193 gc->get = ppc4xx_gpio_get;
194 gc->set = ppc4xx_gpio_set;
196 ret = of_mm_gpiochip_add_data(np, mm_gc, ppc4xx_gc);
201 pr_err("%s: registration failed with status %d\n",
204 /* try others anyway */
208 arch_initcall(ppc4xx_add_gpiochips);