2 * Copyright 2011 IBM Corporation.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
11 #include <linux/types.h>
12 #include <linux/kernel.h>
13 #include <linux/irq.h>
14 #include <linux/smp.h>
15 #include <linux/interrupt.h>
16 #include <linux/init.h>
17 #include <linux/cpu.h>
19 #include <linux/spinlock.h>
20 #include <linux/module.h>
26 #include <asm/errno.h>
28 #include <asm/kvm_ppc.h>
49 static struct icp_ipl __iomem *icp_native_regs[NR_CPUS];
51 static inline unsigned int icp_native_get_xirr(void)
53 int cpu = smp_processor_id();
56 /* Handled an interrupt latched by KVM */
57 xirr = kvmppc_get_xics_latch();
61 return in_be32(&icp_native_regs[cpu]->xirr.word);
64 static inline void icp_native_set_xirr(unsigned int value)
66 int cpu = smp_processor_id();
68 out_be32(&icp_native_regs[cpu]->xirr.word, value);
71 static inline void icp_native_set_cppr(u8 value)
73 int cpu = smp_processor_id();
75 out_8(&icp_native_regs[cpu]->xirr.bytes[0], value);
78 static inline void icp_native_set_qirr(int n_cpu, u8 value)
80 out_8(&icp_native_regs[n_cpu]->qirr.bytes[0], value);
83 static void icp_native_set_cpu_priority(unsigned char cppr)
85 xics_set_base_cppr(cppr);
86 icp_native_set_cppr(cppr);
90 static void icp_native_eoi(struct irq_data *d)
92 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
95 icp_native_set_xirr((xics_pop_cppr() << 24) | hw_irq);
98 static void icp_native_teardown_cpu(void)
100 int cpu = smp_processor_id();
102 /* Clear any pending IPI */
103 icp_native_set_qirr(cpu, 0xff);
106 static void icp_native_flush_ipi(void)
108 /* We take the ipi irq but and never return so we
109 * need to EOI the IPI, but want to leave our priority 0
111 * should we check all the other interrupts too?
112 * should we be flagging idle loop instead?
113 * or creating some task to be scheduled?
116 icp_native_set_xirr((0x00 << 24) | XICS_IPI);
119 static unsigned int icp_native_get_irq(void)
121 unsigned int xirr = icp_native_get_xirr();
122 unsigned int vec = xirr & 0x00ffffff;
125 if (vec == XICS_IRQ_SPURIOUS)
128 irq = irq_find_mapping(xics_host, vec);
129 if (likely(irq != NO_IRQ)) {
134 /* We don't have a linux mapping, so have rtas mask it. */
135 xics_mask_unknown_vec(vec);
137 /* We might learn about it later, so EOI it */
138 icp_native_set_xirr(xirr);
145 static void icp_native_cause_ipi(int cpu, unsigned long data)
147 kvmppc_set_host_ipi(cpu, 1);
148 icp_native_set_qirr(cpu, IPI_PRIORITY);
151 void xics_wake_cpu(int cpu)
153 icp_native_set_qirr(cpu, IPI_PRIORITY);
155 EXPORT_SYMBOL_GPL(xics_wake_cpu);
157 static irqreturn_t icp_native_ipi_action(int irq, void *dev_id)
159 int cpu = smp_processor_id();
161 kvmppc_set_host_ipi(cpu, 0);
162 icp_native_set_qirr(cpu, 0xff);
164 return smp_ipi_demux();
167 #endif /* CONFIG_SMP */
169 static int __init icp_native_map_one_cpu(int hw_id, unsigned long addr,
175 /* This may look gross but it's good enough for now, we don't quite
176 * have a hard -> linux processor id matching.
178 for_each_possible_cpu(i) {
181 if (hw_id == get_hard_smp_processor_id(i)) {
187 /* Fail, skip that CPU. Don't print, it's normal, some XICS come up
188 * with way more entries in there than you have CPUs
193 rname = kasprintf(GFP_KERNEL, "CPU %d [0x%x] Interrupt Presentation",
196 if (!request_mem_region(addr, size, rname)) {
197 pr_warning("icp_native: Could not reserve ICP MMIO"
198 " for CPU %d, interrupt server #0x%x\n",
203 icp_native_regs[cpu] = ioremap(addr, size);
204 kvmppc_set_xics_phys(cpu, addr);
205 if (!icp_native_regs[cpu]) {
206 pr_warning("icp_native: Failed ioremap for CPU %d, "
207 "interrupt server #0x%x, addr %#lx\n",
209 release_mem_region(addr, size);
215 static int __init icp_native_init_one_node(struct device_node *np,
224 /* This code does the theorically broken assumption that the interrupt
225 * server numbers are the same as the hard CPU numbers.
226 * This happens to be the case so far but we are playing with fire...
227 * should be fixed one of these days. -BenH.
229 ireg = of_get_property(np, "ibm,interrupt-server-ranges", &ilen);
231 /* Do that ever happen ? we'll know soon enough... but even good'old
232 * f80 does have that property ..
234 WARN_ON((ireg == NULL) || (ilen != 2*sizeof(u32)));
237 *indx = of_read_number(ireg, 1);
238 if (ilen >= 2*sizeof(u32))
239 num_servers = of_read_number(ireg + 1, 1);
242 ireg = of_get_property(np, "reg", &ilen);
244 pr_err("icp_native: Can't find interrupt reg property");
248 reg_tuple_size = (of_n_addr_cells(np) + of_n_size_cells(np)) * 4;
249 if (((ilen % reg_tuple_size) != 0)
250 || (num_servers && (num_servers != (ilen / reg_tuple_size)))) {
251 pr_err("icp_native: ICP reg len (%d) != num servers (%d)",
252 ilen / reg_tuple_size, num_servers);
256 for (i = 0; i < (ilen / reg_tuple_size); i++) {
260 err = of_address_to_resource(np, i, &r);
262 pr_err("icp_native: Could not translate ICP MMIO"
263 " for interrupt server 0x%x (%d)\n", *indx, err);
267 if (icp_native_map_one_cpu(*indx, r.start, resource_size(&r)))
275 static const struct icp_ops icp_native_ops = {
276 .get_irq = icp_native_get_irq,
277 .eoi = icp_native_eoi,
278 .set_priority = icp_native_set_cpu_priority,
279 .teardown_cpu = icp_native_teardown_cpu,
280 .flush_ipi = icp_native_flush_ipi,
282 .ipi_action = icp_native_ipi_action,
283 .cause_ipi = icp_native_cause_ipi,
287 int __init icp_native_init(void)
289 struct device_node *np;
293 for_each_compatible_node(np, NULL, "ibm,ppc-xicp")
294 if (icp_native_init_one_node(np, &indx) == 0)
297 for_each_node_by_type(np,
298 "PowerPC-External-Interrupt-Presentation") {
299 if (icp_native_init_one_node(np, &indx) == 0)
307 icp_ops = &icp_native_ops;