arch/powerpc/sysdev/xive/native.c

   1 /*
   2  * Copyright 2016,2017 IBM Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #define pr_fmt(fmt) "xive: " fmt
  11
  12 #include <linux/types.h>
  13 #include <linux/irq.h>
  14 #include <linux/debugfs.h>
  15 #include <linux/smp.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/seq_file.h>
  18 #include <linux/init.h>
  19 #include <linux/of.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/delay.h>
  23 #include <linux/cpumask.h>
  24 #include <linux/mm.h>
  25
  26 #include <asm/prom.h>
  27 #include <asm/io.h>
  28 #include <asm/smp.h>
  29 #include <asm/irq.h>
  30 #include <asm/errno.h>
  31 #include <asm/xive.h>
  32 #include <asm/xive-regs.h>
  33 #include <asm/opal.h>
  34 #include <asm/kvm_ppc.h>
  35
  36 #include "xive-internal.h"
  37
  38
  39 static u32 xive_provision_size;
  40 static u32 *xive_provision_chips;
  41 static u32 xive_provision_chip_count;
  42 static u32 xive_queue_shift;
  43 static u32 xive_pool_vps = XIVE_INVALID_VP;
  44 static struct kmem_cache *xive_provision_cache;
  45
  46 int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
  47 {
  48         __be64 flags, eoi_page, trig_page;
  49         __be32 esb_shift, src_chip;
  50         u64 opal_flags;
  51         s64 rc;
  52
  53         memset(data, 0, sizeof(*data));
  54
  55         rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page,
  56                                     &esb_shift, &src_chip);
  57         if (rc) {
  58                 pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n",
  59                        hw_irq, rc);
  60                 return -EINVAL;
  61         }
  62
  63         opal_flags = be64_to_cpu(flags);
  64         if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI)
  65                 data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
  66         if (opal_flags & OPAL_XIVE_IRQ_LSI)
  67                 data->flags |= XIVE_IRQ_FLAG_LSI;
  68         if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG)
  69                 data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG;
  70         if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW)
  71                 data->flags |= XIVE_IRQ_FLAG_MASK_FW;
  72         if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
  73                 data->flags |= XIVE_IRQ_FLAG_EOI_FW;
  74         data->eoi_page = be64_to_cpu(eoi_page);
  75         data->trig_page = be64_to_cpu(trig_page);
  76         data->esb_shift = be32_to_cpu(esb_shift);
  77         data->src_chip = be32_to_cpu(src_chip);
  78
  79         data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
  80         if (!data->eoi_mmio) {
  81                 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
  82                 return -ENOMEM;
  83         }
  84
  85         if (!data->trig_page)
  86                 return 0;
  87         if (data->trig_page == data->eoi_page) {
  88                 data->trig_mmio = data->eoi_mmio;
  89                 return 0;
  90         }
  91
  92         data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
  93         if (!data->trig_mmio) {
  94                 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
  95                 return -ENOMEM;
  96         }
  97         return 0;
  98 }
  99 EXPORT_SYMBOL_GPL(xive_native_populate_irq_data);
 100
 101 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
 102 {
 103         s64 rc;
 104
 105         for (;;) {
 106                 rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq);
 107                 if (rc != OPAL_BUSY)
 108                         break;
 109                 msleep(1);
 110         }
 111         return rc == 0 ? 0 : -ENXIO;
 112 }
 113 EXPORT_SYMBOL_GPL(xive_native_configure_irq);
 114
 115
 116 /* This can be called multiple time to change a queue configuration */
 117 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
 118                                 __be32 *qpage, u32 order, bool can_escalate)
 119 {
 120         s64 rc = 0;
 121         __be64 qeoi_page_be;
 122         __be32 esc_irq_be;
 123         u64 flags, qpage_phys;
 124
 125         /* If there's an actual queue page, clean it */
 126         if (order) {
 127                 if (WARN_ON(!qpage))
 128                         return -EINVAL;
 129                 qpage_phys = __pa(qpage);
 130         } else
 131                 qpage_phys = 0;
 132
 133         /* Initialize the rest of the fields */
 134         q->msk = order ? ((1u << (order - 2)) - 1) : 0;
 135         q->idx = 0;
 136         q->toggle = 0;
 137
 138         rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL,
 139                                       &qeoi_page_be,
 140                                       &esc_irq_be,
 141                                       NULL);
 142         if (rc) {
 143                 pr_err("Error %lld getting queue info prio %d\n", rc, prio);
 144                 rc = -EIO;
 145                 goto fail;
 146         }
 147         q->eoi_phys = be64_to_cpu(qeoi_page_be);
 148
 149         /* Default flags */
 150         flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED;
 151
 152         /* Escalation needed ? */
 153         if (can_escalate) {
 154                 q->esc_irq = be32_to_cpu(esc_irq_be);
 155                 flags |= OPAL_XIVE_EQ_ESCALATE;
 156         }
 157
 158         /* Configure and enable the queue in HW */
 159         for (;;) {
 160                 rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags);
 161                 if (rc != OPAL_BUSY)
 162                         break;
 163                 msleep(1);
 164         }
 165         if (rc) {
 166                 pr_err("Error %lld setting queue for prio %d\n", rc, prio);
 167                 rc = -EIO;
 168         } else {
 169                 /*
 170                  * KVM code requires all of the above to be visible before
 171                  * q->qpage is set due to how it manages IPI EOIs
 172                  */
 173                 wmb();
 174                 q->qpage = qpage;
 175         }
 176 fail:
 177         return rc;
 178 }
 179 EXPORT_SYMBOL_GPL(xive_native_configure_queue);
 180
 181 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
 182 {
 183         s64 rc;
 184
 185         /* Disable the queue in HW */
 186         for (;;) {
 187                 rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0);
 188                         break;
 189                 msleep(1);
 190         }
 191         if (rc)
 192                 pr_err("Error %lld disabling queue for prio %d\n", rc, prio);
 193 }
 194
 195 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
 196 {
 197         __xive_native_disable_queue(vp_id, q, prio);
 198 }
 199 EXPORT_SYMBOL_GPL(xive_native_disable_queue);
 200
 201 static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
 202 {
 203         struct xive_q *q = &xc->queue[prio];
 204         unsigned int alloc_order;
 205         struct page *pages;
 206         __be32 *qpage;
 207
 208         alloc_order = (xive_queue_shift > PAGE_SHIFT) ?
 209                 (xive_queue_shift - PAGE_SHIFT) : 0;
 210         pages = alloc_pages_node(cpu_to_node(cpu), GFP_KERNEL, alloc_order);
 211         if (!pages)
 212                 return -ENOMEM;
 213         qpage = (__be32 *)page_address(pages);
 214         memset(qpage, 0, 1 << xive_queue_shift);
 215         return xive_native_configure_queue(get_hard_smp_processor_id(cpu),
 216                                            q, prio, qpage, xive_queue_shift, false);
 217 }
 218
 219 static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
 220 {
 221         struct xive_q *q = &xc->queue[prio];
 222         unsigned int alloc_order;
 223
 224         /*
 225          * We use the variant with no iounmap as this is called on exec
 226          * from an IPI and iounmap isn't safe
 227          */
 228         __xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio);
 229         alloc_order = (xive_queue_shift > PAGE_SHIFT) ?
 230                 (xive_queue_shift - PAGE_SHIFT) : 0;
 231         free_pages((unsigned long)q->qpage, alloc_order);
 232         q->qpage = NULL;
 233 }
 234
 235 static bool xive_native_match(struct device_node *node)
 236 {
 237         return of_device_is_compatible(node, "ibm,opal-xive-vc");
 238 }
 239
 240 #ifdef CONFIG_SMP
 241 static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc)
 242 {
 243         struct device_node *np;
 244         unsigned int chip_id;
 245         s64 irq;
 246
 247         /* Find the chip ID */
 248         np = of_get_cpu_node(cpu, NULL);
 249         if (np) {
 250                 if (of_property_read_u32(np, "ibm,chip-id", &chip_id) < 0)
 251                         chip_id = 0;
 252         }
 253
 254         /* Allocate an IPI and populate info about it */
 255         for (;;) {
 256                 irq = opal_xive_allocate_irq(chip_id);
 257                 if (irq == OPAL_BUSY) {
 258                         msleep(1);
 259                         continue;
 260                 }
 261                 if (irq < 0) {
 262                         pr_err("Failed to allocate IPI on CPU %d\n", cpu);
 263                         return -ENXIO;
 264                 }
 265                 xc->hw_ipi = irq;
 266                 break;
 267         }
 268         return 0;
 269 }
 270 #endif /* CONFIG_SMP */
 271
 272 u32 xive_native_alloc_irq(void)
 273 {
 274         s64 rc;
 275
 276         for (;;) {
 277                 rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP);
 278                 if (rc != OPAL_BUSY)
 279                         break;
 280                 msleep(1);
 281         }
 282         if (rc < 0)
 283                 return 0;
 284         return rc;
 285 }
 286 EXPORT_SYMBOL_GPL(xive_native_alloc_irq);
 287
 288 void xive_native_free_irq(u32 irq)
 289 {
 290         for (;;) {
 291                 s64 rc = opal_xive_free_irq(irq);
 292                 if (rc != OPAL_BUSY)
 293                         break;
 294                 msleep(1);
 295         }
 296 }
 297 EXPORT_SYMBOL_GPL(xive_native_free_irq);
 298
 299 #ifdef CONFIG_SMP
 300 static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc)
 301 {
 302         s64 rc;
 303
 304         /* Free the IPI */
 305         if (!xc->hw_ipi)
 306                 return;
 307         for (;;) {
 308                 rc = opal_xive_free_irq(xc->hw_ipi);
 309                 if (rc == OPAL_BUSY) {
 310                         msleep(1);
 311                         continue;
 312                 }
 313                 xc->hw_ipi = 0;
 314                 break;
 315         }
 316 }
 317 #endif /* CONFIG_SMP */
 318
 319 static void xive_native_shutdown(void)
 320 {
 321         /* Switch the XIVE to emulation mode */
 322         opal_xive_reset(OPAL_XIVE_MODE_EMU);
 323 }
 324
 325 /*
 326  * Perform an "ack" cycle on the current thread, thus
 327  * grabbing the pending active priorities and updating
 328  * the CPPR to the most favored one.
 329  */
 330 static void xive_native_update_pending(struct xive_cpu *xc)
 331 {
 332         u8 he, cppr;
 333         u16 ack;
 334
 335         /* Perform the acknowledge hypervisor to register cycle */
 336         ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG));
 337
 338         /* Synchronize subsequent queue accesses */
 339         mb();
 340
 341         /*
 342          * Grab the CPPR and the "HE" field which indicates the source
 343          * of the hypervisor interrupt (if any)
 344          */
 345         cppr = ack & 0xff;
 346         he = GETFIELD(TM_QW3_NSR_HE, (ack >> 8));
 347         switch(he) {
 348         case TM_QW3_NSR_HE_NONE: /* Nothing to see here */
 349                 break;
 350         case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */
 351                 if (cppr == 0xff)
 352                         return;
 353                 /* Mark the priority pending */
 354                 xc->pending_prio |= 1 << cppr;
 355
 356                 /*
 357                  * A new interrupt should never have a CPPR less favored
 358                  * than our current one.
 359                  */
 360                 if (cppr >= xc->cppr)
 361                         pr_err("CPU %d odd ack CPPR, got %d at %d\n",
 362                                smp_processor_id(), cppr, xc->cppr);
 363
 364                 /* Update our idea of what the CPPR is */
 365                 xc->cppr = cppr;
 366                 break;
 367         case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */
 368         case TM_QW3_NSR_HE_LSI:  /* Legacy FW LSI (unused) */
 369                 pr_err("CPU %d got unexpected interrupt type HE=%d\n",
 370                        smp_processor_id(), he);
 371                 return;
 372         }
 373 }
 374
 375 static void xive_native_eoi(u32 hw_irq)
 376 {
 377         /*
 378          * Not normally used except if specific interrupts need
 379          * a workaround on EOI.
 380          */
 381         opal_int_eoi(hw_irq);
 382 }
 383
 384 static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
 385 {
 386         s64 rc;
 387         u32 vp;
 388         __be64 vp_cam_be;
 389         u64 vp_cam;
 390
 391         if (xive_pool_vps == XIVE_INVALID_VP)
 392                 return;
 393
 394         /* Enable the pool VP */
 395         vp = xive_pool_vps + cpu;
 396         pr_debug("CPU %d setting up pool VP 0x%x\n", cpu, vp);
 397         for (;;) {
 398                 rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0);
 399                 if (rc != OPAL_BUSY)
 400                         break;
 401                 msleep(1);
 402         }
 403         if (rc) {
 404                 pr_err("Failed to enable pool VP on CPU %d\n", cpu);
 405                 return;
 406         }
 407
 408         /* Grab it's CAM value */
 409         rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL);
 410         if (rc) {
 411                 pr_err("Failed to get pool VP info CPU %d\n", cpu);
 412                 return;
 413         }
 414         vp_cam = be64_to_cpu(vp_cam_be);
 415
 416         pr_debug("VP CAM = %llx\n", vp_cam);
 417
 418         /* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */
 419         pr_debug("(Old HW value: %08x)\n",
 420                  in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
 421         out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff);
 422         out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2,
 423                  TM_QW2W2_VP | vp_cam);
 424         pr_debug("(New HW value: %08x)\n",
 425                  in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
 426 }
 427
 428 static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
 429 {
 430         s64 rc;
 431         u32 vp;
 432
 433         if (xive_pool_vps == XIVE_INVALID_VP)
 434                 return;
 435
 436         /* Pull the pool VP from the CPU */
 437         in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
 438
 439         /* Disable it */
 440         vp = xive_pool_vps + cpu;
 441         for (;;) {
 442                 rc = opal_xive_set_vp_info(vp, 0, 0);
 443                 if (rc != OPAL_BUSY)
 444                         break;
 445                 msleep(1);
 446         }
 447 }
 448
 449 void xive_native_sync_source(u32 hw_irq)
 450 {
 451         opal_xive_sync(XIVE_SYNC_EAS, hw_irq);
 452 }
 453 EXPORT_SYMBOL_GPL(xive_native_sync_source);
 454
 455 static const struct xive_ops xive_native_ops = {
 456         .populate_irq_data      = xive_native_populate_irq_data,
 457         .configure_irq          = xive_native_configure_irq,
 458         .setup_queue            = xive_native_setup_queue,
 459         .cleanup_queue          = xive_native_cleanup_queue,
 460         .match                  = xive_native_match,
 461         .shutdown               = xive_native_shutdown,
 462         .update_pending         = xive_native_update_pending,
 463         .eoi                    = xive_native_eoi,
 464         .setup_cpu              = xive_native_setup_cpu,
 465         .teardown_cpu           = xive_native_teardown_cpu,
 466         .sync_source            = xive_native_sync_source,
 467 #ifdef CONFIG_SMP
 468         .get_ipi                = xive_native_get_ipi,
 469         .put_ipi                = xive_native_put_ipi,
 470 #endif /* CONFIG_SMP */
 471         .name                   = "native",
 472 };
 473
 474 static bool xive_parse_provisioning(struct device_node *np)
 475 {
 476         int rc;
 477
 478         if (of_property_read_u32(np, "ibm,xive-provision-page-size",
 479                                  &xive_provision_size) < 0)
 480                 return true;
 481         rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4);
 482         if (rc < 0) {
 483                 pr_err("Error %d getting provision chips array\n", rc);
 484                 return false;
 485         }
 486         xive_provision_chip_count = rc;
 487         if (rc == 0)
 488                 return true;
 489
 490         xive_provision_chips = kzalloc(4 * xive_provision_chip_count,
 491                                        GFP_KERNEL);
 492         if (WARN_ON(!xive_provision_chips))
 493                 return false;
 494
 495         rc = of_property_read_u32_array(np, "ibm,xive-provision-chips",
 496                                         xive_provision_chips,
 497                                         xive_provision_chip_count);
 498         if (rc < 0) {
 499                 pr_err("Error %d reading provision chips array\n", rc);
 500                 return false;
 501         }
 502
 503         xive_provision_cache = kmem_cache_create("xive-provision",
 504                                                  xive_provision_size,
 505                                                  xive_provision_size,
 506                                                  0, NULL);
 507         if (!xive_provision_cache) {
 508                 pr_err("Failed to allocate provision cache\n");
 509                 return false;
 510         }
 511         return true;
 512 }
 513
 514 static void xive_native_setup_pools(void)
 515 {
 516         /* Allocate a pool big enough */
 517         pr_debug("XIVE: Allocating VP block for pool size %d\n", nr_cpu_ids);
 518
 519         xive_pool_vps = xive_native_alloc_vp_block(nr_cpu_ids);
 520         if (WARN_ON(xive_pool_vps == XIVE_INVALID_VP))
 521                 pr_err("XIVE: Failed to allocate pool VP, KVM might not function\n");
 522
 523         pr_debug("XIVE: Pool VPs allocated at 0x%x for %d max CPUs\n",
 524                  xive_pool_vps, nr_cpu_ids);
 525 }
 526
 527 u32 xive_native_default_eq_shift(void)
 528 {
 529         return xive_queue_shift;
 530 }
 531 EXPORT_SYMBOL_GPL(xive_native_default_eq_shift);
 532
 533 bool xive_native_init(void)
 534 {
 535         struct device_node *np;
 536         struct resource r;
 537         void __iomem *tima;
 538         struct property *prop;
 539         u8 max_prio = 7;
 540         const __be32 *p;
 541         u32 val, cpu;
 542         s64 rc;
 543
 544         if (xive_cmdline_disabled)
 545                 return false;
 546
 547         pr_devel("xive_native_init()\n");
 548         np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe");
 549         if (!np) {
 550                 pr_devel("not found !\n");
 551                 return false;
 552         }
 553         pr_devel("Found %s\n", np->full_name);
 554
 555         /* Resource 1 is HV window */
 556         if (of_address_to_resource(np, 1, &r)) {
 557                 pr_err("Failed to get thread mgmnt area resource\n");
 558                 return false;
 559         }
 560         tima = ioremap(r.start, resource_size(&r));
 561         if (!tima) {
 562                 pr_err("Failed to map thread mgmnt area\n");
 563                 return false;
 564         }
 565
 566         /* Read number of priorities */
 567         if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0)
 568                 max_prio = val - 1;
 569
 570         /* Iterate the EQ sizes and pick one */
 571         of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) {
 572                 xive_queue_shift = val;
 573                 if (val == PAGE_SHIFT)
 574                         break;
 575         }
 576
 577         /* Configure Thread Management areas for KVM */
 578         for_each_possible_cpu(cpu)
 579                 kvmppc_set_xive_tima(cpu, r.start, tima);
 580
 581         /* Grab size of provisionning pages */
 582         xive_parse_provisioning(np);
 583
 584         /* Switch the XIVE to exploitation mode */
 585         rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL);
 586         if (rc) {
 587                 pr_err("Switch to exploitation mode failed with error %lld\n", rc);
 588                 return false;
 589         }
 590
 591         /* Setup some dummy HV pool VPs */
 592         xive_native_setup_pools();
 593
 594         /* Initialize XIVE core with our backend */
 595         if (!xive_core_init(&xive_native_ops, tima, TM_QW3_HV_PHYS,
 596                             max_prio)) {
 597                 opal_xive_reset(OPAL_XIVE_MODE_EMU);
 598                 return false;
 599         }
 600         pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
 601         return true;
 602 }
 603
 604 static bool xive_native_provision_pages(void)
 605 {
 606         u32 i;
 607         void *p;
 608
 609         for (i = 0; i < xive_provision_chip_count; i++) {
 610                 u32 chip = xive_provision_chips[i];
 611
 612                 /*
 613                  * XXX TODO: Try to make the allocation local to the node where
 614                  * the chip resides.
 615                  */
 616                 p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL);
 617                 if (!p) {
 618                         pr_err("Failed to allocate provisioning page\n");
 619                         return false;
 620                 }
 621                 opal_xive_donate_page(chip, __pa(p));
 622         }
 623         return true;
 624 }
 625
 626 u32 xive_native_alloc_vp_block(u32 max_vcpus)
 627 {
 628         s64 rc;
 629         u32 order;
 630
 631         order = fls(max_vcpus) - 1;
 632         if (max_vcpus > (1 << order))
 633                 order++;
 634
 635         pr_info("VP block alloc, for max VCPUs %d use order %d\n",
 636                 max_vcpus, order);
 637
 638         for (;;) {
 639                 rc = opal_xive_alloc_vp_block(order);
 640                 switch (rc) {
 641                 case OPAL_BUSY:
 642                         msleep(1);
 643                         break;
 644                 case OPAL_XIVE_PROVISIONING:
 645                         if (!xive_native_provision_pages())
 646                                 return XIVE_INVALID_VP;
 647                         break;
 648                 default:
 649                         if (rc < 0) {
 650                                 pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n",
 651                                        order, rc);
 652                                 return XIVE_INVALID_VP;
 653                         }
 654                         return rc;
 655                 }
 656         }
 657 }
 658 EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block);
 659
 660 void xive_native_free_vp_block(u32 vp_base)
 661 {
 662         s64 rc;
 663
 664         if (vp_base == XIVE_INVALID_VP)
 665                 return;
 666
 667         rc = opal_xive_free_vp_block(vp_base);
 668         if (rc < 0)
 669                 pr_warn("OPAL error %lld freeing VP block\n", rc);
 670 }
 671 EXPORT_SYMBOL_GPL(xive_native_free_vp_block);
 672
 673 int xive_native_enable_vp(u32 vp_id)
 674 {
 675         s64 rc;
 676
 677         for (;;) {
 678                 rc = opal_xive_set_vp_info(vp_id, OPAL_XIVE_VP_ENABLED, 0);
 679                 if (rc != OPAL_BUSY)
 680                         break;
 681                 msleep(1);
 682         }
 683         return rc ? -EIO : 0;
 684 }
 685 EXPORT_SYMBOL_GPL(xive_native_enable_vp);
 686
 687 int xive_native_disable_vp(u32 vp_id)
 688 {
 689         s64 rc;
 690
 691         for (;;) {
 692                 rc = opal_xive_set_vp_info(vp_id, 0, 0);
 693                 if (rc != OPAL_BUSY)
 694                         break;
 695                 msleep(1);
 696         }
 697         return rc ? -EIO : 0;
 698 }
 699 EXPORT_SYMBOL_GPL(xive_native_disable_vp);
 700
 701 int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id)
 702 {
 703         __be64 vp_cam_be;
 704         __be32 vp_chip_id_be;
 705         s64 rc;
 706
 707         rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be);
 708         if (rc)
 709                 return -EIO;
 710         *out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu;
 711         *out_chip_id = be32_to_cpu(vp_chip_id_be);
 712
 713         return 0;
 714 }
 715 EXPORT_SYMBOL_GPL(xive_native_get_vp_info);