2 * Copyright 2016,2017 IBM Corporation.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #define pr_fmt(fmt) "xive: " fmt
12 #include <linux/types.h>
13 #include <linux/irq.h>
14 #include <linux/debugfs.h>
15 #include <linux/smp.h>
16 #include <linux/interrupt.h>
17 #include <linux/seq_file.h>
18 #include <linux/init.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/delay.h>
23 #include <linux/cpumask.h>
30 #include <asm/errno.h>
32 #include <asm/xive-regs.h>
35 #include "xive-internal.h"
38 static u32 xive_provision_size;
39 static u32 *xive_provision_chips;
40 static u32 xive_provision_chip_count;
41 static u32 xive_queue_shift;
42 static u32 xive_pool_vps = XIVE_INVALID_VP;
43 static struct kmem_cache *xive_provision_cache;
45 int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
47 __be64 flags, eoi_page, trig_page;
48 __be32 esb_shift, src_chip;
52 memset(data, 0, sizeof(*data));
54 rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page,
55 &esb_shift, &src_chip);
57 pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n",
62 opal_flags = be64_to_cpu(flags);
63 if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI)
64 data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
65 if (opal_flags & OPAL_XIVE_IRQ_LSI)
66 data->flags |= XIVE_IRQ_FLAG_LSI;
67 if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG)
68 data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG;
69 if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW)
70 data->flags |= XIVE_IRQ_FLAG_MASK_FW;
71 if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
72 data->flags |= XIVE_IRQ_FLAG_EOI_FW;
73 data->eoi_page = be64_to_cpu(eoi_page);
74 data->trig_page = be64_to_cpu(trig_page);
75 data->esb_shift = be32_to_cpu(esb_shift);
76 data->src_chip = be32_to_cpu(src_chip);
78 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
79 if (!data->eoi_mmio) {
80 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
86 if (data->trig_page == data->eoi_page) {
87 data->trig_mmio = data->eoi_mmio;
91 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
92 if (!data->trig_mmio) {
93 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
99 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
104 rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq);
109 return rc == 0 ? 0 : -ENXIO;
112 /* This can be called multiple time to change a queue configuration */
113 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
114 __be32 *qpage, u32 order, bool can_escalate)
119 u64 flags, qpage_phys;
121 /* If there's an actual queue page, clean it */
125 qpage_phys = __pa(qpage);
129 /* Initialize the rest of the fields */
130 q->msk = order ? ((1u << (order - 2)) - 1) : 0;
134 rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL,
139 pr_err("Error %lld getting queue info prio %d\n", rc, prio);
143 q->eoi_phys = be64_to_cpu(qeoi_page_be);
146 flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED;
148 /* Escalation needed ? */
150 q->esc_irq = be32_to_cpu(esc_irq_be);
151 flags |= OPAL_XIVE_EQ_ESCALATE;
154 /* Configure and enable the queue in HW */
156 rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags);
162 pr_err("Error %lld setting queue for prio %d\n", rc, prio);
166 * KVM code requires all of the above to be visible before
167 * q->qpage is set due to how it manages IPI EOIs
176 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
180 /* Disable the queue in HW */
182 rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0);
188 pr_err("Error %lld disabling queue for prio %d\n", rc, prio);
191 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
193 __xive_native_disable_queue(vp_id, q, prio);
196 static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
198 struct xive_q *q = &xc->queue[prio];
199 unsigned int alloc_order;
203 alloc_order = (xive_queue_shift > PAGE_SHIFT) ?
204 (xive_queue_shift - PAGE_SHIFT) : 0;
205 pages = alloc_pages_node(cpu_to_node(cpu), GFP_KERNEL, alloc_order);
208 qpage = (__be32 *)page_address(pages);
209 memset(qpage, 0, 1 << xive_queue_shift);
210 return xive_native_configure_queue(get_hard_smp_processor_id(cpu),
211 q, prio, qpage, xive_queue_shift, false);
214 static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
216 struct xive_q *q = &xc->queue[prio];
217 unsigned int alloc_order;
220 * We use the variant with no iounmap as this is called on exec
221 * from an IPI and iounmap isn't safe
223 __xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio);
224 alloc_order = (xive_queue_shift > PAGE_SHIFT) ?
225 (xive_queue_shift - PAGE_SHIFT) : 0;
226 free_pages((unsigned long)q->qpage, alloc_order);
230 static bool xive_native_match(struct device_node *node)
232 return of_device_is_compatible(node, "ibm,opal-xive-vc");
236 static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc)
238 struct device_node *np;
239 unsigned int chip_id;
242 /* Find the chip ID */
243 np = of_get_cpu_node(cpu, NULL);
245 if (of_property_read_u32(np, "ibm,chip-id", &chip_id) < 0)
249 /* Allocate an IPI and populate info about it */
251 irq = opal_xive_allocate_irq(chip_id);
252 if (irq == OPAL_BUSY) {
257 pr_err("Failed to allocate IPI on CPU %d\n", cpu);
266 u32 xive_native_alloc_irq(void)
271 rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP);
281 void xive_native_free_irq(u32 irq)
284 s64 rc = opal_xive_free_irq(irq);
291 static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc)
299 rc = opal_xive_free_irq(xc->hw_ipi);
300 if (rc == OPAL_BUSY) {
308 #endif /* CONFIG_SMP */
310 static void xive_native_shutdown(void)
312 /* Switch the XIVE to emulation mode */
313 opal_xive_reset(OPAL_XIVE_MODE_EMU);
317 * Perform an "ack" cycle on the current thread, thus
318 * grabbing the pending active priorities and updating
319 * the CPPR to the most favored one.
321 static void xive_native_update_pending(struct xive_cpu *xc)
326 /* Perform the acknowledge hypervisor to register cycle */
327 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG));
329 /* Synchronize subsequent queue accesses */
333 * Grab the CPPR and the "HE" field which indicates the source
334 * of the hypervisor interrupt (if any)
337 he = GETFIELD(TM_QW3_NSR_HE, (ack >> 8));
339 case TM_QW3_NSR_HE_NONE: /* Nothing to see here */
341 case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */
344 /* Mark the priority pending */
345 xc->pending_prio |= 1 << cppr;
348 * A new interrupt should never have a CPPR less favored
349 * than our current one.
351 if (cppr >= xc->cppr)
352 pr_err("CPU %d odd ack CPPR, got %d at %d\n",
353 smp_processor_id(), cppr, xc->cppr);
355 /* Update our idea of what the CPPR is */
358 case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */
359 case TM_QW3_NSR_HE_LSI: /* Legacy FW LSI (unused) */
360 pr_err("CPU %d got unexpected interrupt type HE=%d\n",
361 smp_processor_id(), he);
366 static void xive_native_eoi(u32 hw_irq)
369 * Not normally used except if specific interrupts need
370 * a workaround on EOI.
372 opal_int_eoi(hw_irq);
375 static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
382 if (xive_pool_vps == XIVE_INVALID_VP)
385 /* Enable the pool VP */
386 vp = xive_pool_vps + get_hard_smp_processor_id(cpu);
387 pr_debug("CPU %d setting up pool VP 0x%x\n", cpu, vp);
389 rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0);
395 pr_err("Failed to enable pool VP on CPU %d\n", cpu);
399 /* Grab it's CAM value */
400 rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL);
402 pr_err("Failed to get pool VP info CPU %d\n", cpu);
405 vp_cam = be64_to_cpu(vp_cam_be);
407 pr_debug("VP CAM = %llx\n", vp_cam);
409 /* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */
410 pr_debug("(Old HW value: %08x)\n",
411 in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
412 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff);
413 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2,
414 TM_QW2W2_VP | vp_cam);
415 pr_debug("(New HW value: %08x)\n",
416 in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
419 static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
424 if (xive_pool_vps == XIVE_INVALID_VP)
427 /* Pull the pool VP from the CPU */
428 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
431 vp = xive_pool_vps + get_hard_smp_processor_id(cpu);
433 rc = opal_xive_set_vp_info(vp, 0, 0);
440 static void xive_native_sync_source(u32 hw_irq)
442 opal_xive_sync(XIVE_SYNC_EAS, hw_irq);
445 static const struct xive_ops xive_native_ops = {
446 .populate_irq_data = xive_native_populate_irq_data,
447 .configure_irq = xive_native_configure_irq,
448 .setup_queue = xive_native_setup_queue,
449 .cleanup_queue = xive_native_cleanup_queue,
450 .match = xive_native_match,
451 .shutdown = xive_native_shutdown,
452 .update_pending = xive_native_update_pending,
453 .eoi = xive_native_eoi,
454 .setup_cpu = xive_native_setup_cpu,
455 .teardown_cpu = xive_native_teardown_cpu,
456 .sync_source = xive_native_sync_source,
458 .get_ipi = xive_native_get_ipi,
459 .put_ipi = xive_native_put_ipi,
460 #endif /* CONFIG_SMP */
464 static bool xive_parse_provisioning(struct device_node *np)
468 if (of_property_read_u32(np, "ibm,xive-provision-page-size",
469 &xive_provision_size) < 0)
471 rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4);
473 pr_err("Error %d getting provision chips array\n", rc);
476 xive_provision_chip_count = rc;
480 xive_provision_chips = kzalloc(4 * xive_provision_chip_count,
482 if (WARN_ON(!xive_provision_chips))
485 rc = of_property_read_u32_array(np, "ibm,xive-provision-chips",
486 xive_provision_chips,
487 xive_provision_chip_count);
489 pr_err("Error %d reading provision chips array\n", rc);
493 xive_provision_cache = kmem_cache_create("xive-provision",
497 if (!xive_provision_cache) {
498 pr_err("Failed to allocate provision cache\n");
504 u32 xive_native_default_eq_shift(void)
506 return xive_queue_shift;
509 bool xive_native_init(void)
511 struct device_node *np;
514 struct property *prop;
520 if (xive_cmdline_disabled)
523 pr_devel("xive_native_init()\n");
524 np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe");
526 pr_devel("not found !\n");
529 pr_devel("Found %s\n", np->full_name);
531 /* Resource 1 is HV window */
532 if (of_address_to_resource(np, 1, &r)) {
533 pr_err("Failed to get thread mgmnt area resource\n");
536 tima = ioremap(r.start, resource_size(&r));
538 pr_err("Failed to map thread mgmnt area\n");
542 /* Read number of priorities */
543 if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0)
546 /* Iterate the EQ sizes and pick one */
547 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) {
548 xive_queue_shift = val;
549 if (val == PAGE_SHIFT)
553 /* Grab size of provisioning pages */
554 xive_parse_provisioning(np);
556 /* Switch the XIVE to exploitation mode */
557 rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL);
559 pr_err("Switch to exploitation mode failed with error %lld\n", rc);
563 /* Initialize XIVE core with our backend */
564 if (!xive_core_init(&xive_native_ops, tima, TM_QW3_HV_PHYS,
566 opal_xive_reset(OPAL_XIVE_MODE_EMU);
569 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
573 static bool xive_native_provision_pages(void)
578 for (i = 0; i < xive_provision_chip_count; i++) {
579 u32 chip = xive_provision_chips[i];
582 * XXX TODO: Try to make the allocation local to the node where
585 p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL);
587 pr_err("Failed to allocate provisioning page\n");
590 opal_xive_donate_page(chip, __pa(p));
595 u32 xive_native_alloc_vp_block(u32 max_vcpus)
600 order = fls(max_vcpus) - 1;
601 if (max_vcpus > (1 << order))
604 pr_info("VP block alloc, for max VCPUs %d use order %d\n",
608 rc = opal_xive_alloc_vp_block(order);
613 case OPAL_XIVE_PROVISIONING:
614 if (!xive_native_provision_pages())
615 return XIVE_INVALID_VP;
619 pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n",
621 return XIVE_INVALID_VP;
627 EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block);
629 void xive_native_free_vp_block(u32 vp_base)
633 if (vp_base == XIVE_INVALID_VP)
636 rc = opal_xive_free_vp_block(vp_base);
638 pr_warn("OPAL error %lld freeing VP block\n", rc);
640 EXPORT_SYMBOL_GPL(xive_native_free_vp_block);