1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of GDB, GAS, and the GNU binutils.
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 2, or (at your option) any later version.
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
27 #include "opcode/ppc.h"
29 /* This file provides several disassembler functions, all of which use
30 the disassembler interface defined in dis-asm.h. Several functions
31 are provided because this file handles disassembly for the PowerPC
32 in both big and little endian mode and also for the POWER (RS/6000)
34 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
39 /* Stash the result of parsing disassembler_options here. */
43 #define POWERPC_DIALECT(INFO) \
44 (((struct dis_private *) ((INFO)->private_data))->dialect)
52 struct ppc_mopt ppc_opts[] = {
53 { "403", PPC_OPCODE_PPC | PPC_OPCODE_403,
55 { "405", PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
57 { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
58 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
60 { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
61 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
63 { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
64 | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
66 { "601", PPC_OPCODE_PPC | PPC_OPCODE_601,
68 { "603", PPC_OPCODE_PPC,
70 { "604", PPC_OPCODE_PPC,
72 { "620", PPC_OPCODE_PPC | PPC_OPCODE_64,
74 { "7400", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
76 { "7410", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
78 { "7450", PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
80 { "7455", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
82 { "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
84 { "821", PPC_OPCODE_PPC | PPC_OPCODE_860,
86 { "850", PPC_OPCODE_PPC | PPC_OPCODE_860,
88 { "860", PPC_OPCODE_PPC | PPC_OPCODE_860,
90 { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
91 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
94 { "altivec", PPC_OPCODE_PPC,
95 PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 },
98 { "booke", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
100 { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
102 { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
103 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
105 { "com", PPC_OPCODE_COMMON,
107 { "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
108 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
109 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
110 | PPC_OPCODE_E500 | PPC_OPCODE_E200Z4),
112 { "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
114 { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
115 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
116 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
119 { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
120 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
121 | PPC_OPCODE_E500MC),
123 { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
124 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
125 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
126 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
128 { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
129 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
130 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
131 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
132 | PPC_OPCODE_POWER7),
134 { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
135 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
136 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
137 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
138 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
140 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
141 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
142 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
145 { "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
147 { "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
149 { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
150 | PPC_OPCODE_POWER5),
152 { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
153 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
155 { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
156 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
157 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
159 { "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
160 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
161 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
162 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
164 { "power9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
165 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
166 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
167 | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
168 | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
170 { "ppc", PPC_OPCODE_PPC,
172 { "ppc32", PPC_OPCODE_PPC,
174 { "ppc64", PPC_OPCODE_PPC | PPC_OPCODE_64,
176 { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
178 { "ppcps", PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
180 { "pwr", PPC_OPCODE_POWER,
182 { "pwr2", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
184 { "pwr4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
186 { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
187 | PPC_OPCODE_POWER5),
189 { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
190 | PPC_OPCODE_POWER5),
192 { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
193 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
195 { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
196 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
197 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
199 { "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
200 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
201 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
202 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
204 { "pwr9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
205 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
206 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
207 | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
208 | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
210 { "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
212 { "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
214 { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
215 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
217 { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
218 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
219 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
222 { "vsx", PPC_OPCODE_PPC,
223 PPC_OPCODE_VSX | PPC_OPCODE_VSX3 },
224 { "htm", PPC_OPCODE_PPC,
228 /* Switch between Booke and VLE dialects for interlinked dumps. */
230 get_powerpc_dialect (struct disassemble_info *info)
232 ppc_cpu_t dialect = 0;
234 dialect = POWERPC_DIALECT (info);
236 /* Disassemble according to the section headers flags for VLE-mode. */
237 if (dialect & PPC_OPCODE_VLE
238 && info->section->owner != NULL
239 && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
240 && elf_object_id (info->section->owner) == PPC32_ELF_DATA
241 && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
244 return dialect & ~ PPC_OPCODE_VLE;
247 /* Handle -m and -M options that set cpu type, and .machine arg. */
250 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
254 for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
255 if (strcmp (ppc_opts[i].opt, arg) == 0)
257 if (ppc_opts[i].sticky)
259 *sticky |= ppc_opts[i].sticky;
260 if ((ppc_cpu & ~*sticky) != 0)
263 ppc_cpu = ppc_opts[i].cpu;
266 if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
273 /* Determine which set of machines to disassemble for. */
276 powerpc_init_dialect (struct disassemble_info *info)
278 ppc_cpu_t dialect = 0;
279 ppc_cpu_t sticky = 0;
281 struct dis_private *priv = calloc (sizeof (*priv), 1);
288 case bfd_mach_ppc_403:
289 case bfd_mach_ppc_403gc:
290 dialect = ppc_parse_cpu (dialect, &sticky, "403");
292 case bfd_mach_ppc_405:
293 dialect = ppc_parse_cpu (dialect, &sticky, "405");
295 case bfd_mach_ppc_601:
296 dialect = ppc_parse_cpu (dialect, &sticky, "601");
298 case bfd_mach_ppc_a35:
299 case bfd_mach_ppc_rs64ii:
300 case bfd_mach_ppc_rs64iii:
301 dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
303 case bfd_mach_ppc_e500:
304 dialect = ppc_parse_cpu (dialect, &sticky, "e500");
306 case bfd_mach_ppc_e500mc:
307 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
309 case bfd_mach_ppc_e500mc64:
310 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
312 case bfd_mach_ppc_e5500:
313 dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
315 case bfd_mach_ppc_e6500:
316 dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
318 case bfd_mach_ppc_titan:
319 dialect = ppc_parse_cpu (dialect, &sticky, "titan");
321 case bfd_mach_ppc_vle:
322 dialect = ppc_parse_cpu (dialect, &sticky, "vle");
325 dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
328 arg = info->disassembler_options;
331 ppc_cpu_t new_cpu = 0;
332 char *end = strchr (arg, ',');
337 if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0)
339 else if (strcmp (arg, "32") == 0)
340 dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
341 else if (strcmp (arg, "64") == 0)
342 dialect |= PPC_OPCODE_64;
344 fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
351 info->private_data = priv;
352 POWERPC_DIALECT(info) = dialect;
355 #define PPC_OPCD_SEGS 64
356 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
357 #define VLE_OPCD_SEGS 32
358 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
360 /* Calculate opcode table indices to speed up disassembly,
364 disassemble_init_powerpc (struct disassemble_info *info)
369 if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
372 i = powerpc_num_opcodes;
375 unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
377 powerpc_opcd_indices[op] = i;
380 last = powerpc_num_opcodes;
381 for (i = PPC_OPCD_SEGS; i > 0; --i)
383 if (powerpc_opcd_indices[i] == 0)
384 powerpc_opcd_indices[i] = last;
385 last = powerpc_opcd_indices[i];
391 unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
392 unsigned seg = VLE_OP_TO_SEG (op);
394 vle_opcd_indices[seg] = i;
397 last = vle_num_opcodes;
398 for (i = VLE_OPCD_SEGS; i > 0; --i)
400 if (vle_opcd_indices[i] == 0)
401 vle_opcd_indices[i] = last;
402 last = vle_opcd_indices[i];
406 if (info->arch == bfd_arch_powerpc)
407 powerpc_init_dialect (info);
410 /* Print a big endian PowerPC instruction. */
413 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
415 return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
418 /* Print a little endian PowerPC instruction. */
421 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
423 return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
426 /* Print a POWER (RS/6000) instruction. */
429 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
431 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
434 /* Extract the operand value from the PowerPC or POWER instruction. */
437 operand_value_powerpc (const struct powerpc_operand *operand,
438 unsigned long insn, ppc_cpu_t dialect)
442 /* Extract the value from the instruction. */
443 if (operand->extract)
444 value = (*operand->extract) (insn, dialect, &invalid);
447 if (operand->shift >= 0)
448 value = (insn >> operand->shift) & operand->bitm;
450 value = (insn << -operand->shift) & operand->bitm;
451 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
453 /* BITM is always some number of zeros followed by some
454 number of ones, followed by some number of zeros. */
455 unsigned long top = operand->bitm;
456 /* top & -top gives the rightmost 1 bit, so this
457 fills in any trailing zeros. */
458 top |= (top & -top) - 1;
460 value = (value ^ top) - top;
467 /* Determine whether the optional operand(s) should be printed. */
470 skip_optional_operands (const unsigned char *opindex,
471 unsigned long insn, ppc_cpu_t dialect)
473 const struct powerpc_operand *operand;
475 for (; *opindex != 0; opindex++)
477 operand = &powerpc_operands[*opindex];
478 if ((operand->flags & PPC_OPERAND_NEXT) != 0
479 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
480 && operand_value_powerpc (operand, insn, dialect) !=
481 ppc_optional_operand_value (operand)))
488 /* Find a match for INSN in the opcode table, given machine DIALECT.
489 A DIALECT of -1 is special, matching all machine opcode variations. */
491 static const struct powerpc_opcode *
492 lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
494 const struct powerpc_opcode *opcode;
495 const struct powerpc_opcode *opcode_end;
498 /* Get the major opcode of the instruction. */
501 /* Find the first match in the opcode table for this major opcode. */
502 opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
503 for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
507 const unsigned char *opindex;
508 const struct powerpc_operand *operand;
511 if ((insn & opcode->mask) != opcode->opcode
512 || (dialect != (ppc_cpu_t) -1
513 && ((opcode->flags & dialect) == 0
514 || (opcode->deprecated & dialect) != 0)))
517 /* Check validity of operands. */
519 for (opindex = opcode->operands; *opindex != 0; opindex++)
521 operand = powerpc_operands + *opindex;
522 if (operand->extract)
523 (*operand->extract) (insn, dialect, &invalid);
534 /* Find a match for INSN in the VLE opcode table. */
536 static const struct powerpc_opcode *
537 lookup_vle (unsigned long insn)
539 const struct powerpc_opcode *opcode;
540 const struct powerpc_opcode *opcode_end;
544 if (op >= 0x20 && op <= 0x37)
546 /* This insn has a 4-bit opcode. */
549 seg = VLE_OP_TO_SEG (op);
551 /* Find the first match in the opcode table for this major opcode. */
552 opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
553 for (opcode = vle_opcodes + vle_opcd_indices[seg];
557 unsigned long table_opcd = opcode->opcode;
558 unsigned long table_mask = opcode->mask;
559 bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
561 const unsigned char *opindex;
562 const struct powerpc_operand *operand;
566 if (table_op_is_short)
568 if ((insn2 & table_mask) != table_opcd)
571 /* Check validity of operands. */
573 for (opindex = opcode->operands; *opindex != 0; ++opindex)
575 operand = powerpc_operands + *opindex;
576 if (operand->extract)
577 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
588 /* Print a PowerPC or POWER instruction. */
591 print_insn_powerpc (bfd_vma memaddr,
592 struct disassemble_info *info,
599 const struct powerpc_opcode *opcode;
600 bfd_boolean insn_is_short;
602 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
605 /* The final instruction may be a 2-byte VLE insn. */
606 if ((dialect & PPC_OPCODE_VLE) != 0)
608 /* Clear buffer so unused bytes will not have garbage in them. */
609 buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
610 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
613 (*info->memory_error_func) (status, memaddr, info);
619 (*info->memory_error_func) (status, memaddr, info);
625 insn = bfd_getb32 (buffer);
627 insn = bfd_getl32 (buffer);
629 /* Get the major opcode of the insn. */
631 insn_is_short = FALSE;
632 if ((dialect & PPC_OPCODE_VLE) != 0)
634 opcode = lookup_vle (insn);
636 insn_is_short = PPC_OP_SE_VLE(opcode->mask);
639 opcode = lookup_powerpc (insn, dialect);
640 if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
641 opcode = lookup_powerpc (insn, (ppc_cpu_t) -1);
645 const unsigned char *opindex;
646 const struct powerpc_operand *operand;
651 if (opcode->operands[0] != 0)
652 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
654 (*info->fprintf_func) (info->stream, "%s", opcode->name);
657 /* The operands will be fetched out of the 16-bit instruction. */
660 /* Now extract and print the operands. */
664 for (opindex = opcode->operands; *opindex != 0; opindex++)
668 operand = powerpc_operands + *opindex;
670 /* Operands that are marked FAKE are simply ignored. We
671 already made sure that the extract function considered
672 the instruction to be valid. */
673 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
676 /* If all of the optional operands have the value zero,
677 then don't print any of them. */
678 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
680 if (skip_optional < 0)
681 skip_optional = skip_optional_operands (opindex, insn,
687 value = operand_value_powerpc (operand, insn, dialect);
691 (*info->fprintf_func) (info->stream, ",");
695 /* Print the operand as directed by the flags. */
696 if ((operand->flags & PPC_OPERAND_GPR) != 0
697 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
698 (*info->fprintf_func) (info->stream, "r%ld", value);
699 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
700 (*info->fprintf_func) (info->stream, "f%ld", value);
701 else if ((operand->flags & PPC_OPERAND_VR) != 0)
702 (*info->fprintf_func) (info->stream, "v%ld", value);
703 else if ((operand->flags & PPC_OPERAND_VSR) != 0)
704 (*info->fprintf_func) (info->stream, "vs%ld", value);
705 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
706 (*info->print_address_func) (memaddr + value, info);
707 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
708 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
709 else if ((operand->flags & PPC_OPERAND_FSL) != 0)
710 (*info->fprintf_func) (info->stream, "fsl%ld", value);
711 else if ((operand->flags & PPC_OPERAND_FCR) != 0)
712 (*info->fprintf_func) (info->stream, "fcr%ld", value);
713 else if ((operand->flags & PPC_OPERAND_UDI) != 0)
714 (*info->fprintf_func) (info->stream, "%ld", value);
715 else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
716 && (((dialect & PPC_OPCODE_PPC) != 0)
717 || ((dialect & PPC_OPCODE_VLE) != 0)))
718 (*info->fprintf_func) (info->stream, "cr%ld", value);
719 else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
720 && (((dialect & PPC_OPCODE_PPC) != 0)
721 || ((dialect & PPC_OPCODE_VLE) != 0)))
723 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
729 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
731 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
734 (*info->fprintf_func) (info->stream, "%d", (int) value);
738 (*info->fprintf_func) (info->stream, ")");
742 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
746 (*info->fprintf_func) (info->stream, "(");
751 /* We have found and printed an instruction.
752 If it was a short VLE instruction we have more to do. */
759 /* Otherwise, return. */
763 /* We could not find a match. */
764 (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
770 print_ppc_disassembler_options (FILE *stream)
774 fprintf (stream, _("\n\
775 The following PPC specific disassembler options are supported for use with\n\
778 for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
780 col += fprintf (stream, " %s,", ppc_opts[i].opt);
783 fprintf (stream, "\n");
787 fprintf (stream, " 32, 64\n");