2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /*------------------------------------------------------------------------------+
28 * This source code is dual-licensed. You may use it under the terms of the
29 * GNU General Public License version 2, or under the license below.
31 * This source code has been made available to you by IBM on an AS-IS
32 * basis. Anyone receiving this source is licensed under IBM
33 * copyrights to use it in any way he or she deems fit, including
34 * copying it, modifying it, compiling it, and redistributing it either
35 * with or without modifications. No license under IBM patents or
36 * patent applications is to be implied by the copyright license.
38 * Any user of this software should understand that IBM cannot provide
39 * technical support for this software and will not be responsible for
40 * any consequences resulting from the use of this software.
42 * Any person who transfers this source code or any derivative work
43 * must include the IBM copyright notice, this paragraph, and the
44 * preceding two paragraphs in the transferred software.
46 * COPYRIGHT I B M CORPORATION 1995
47 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
48 *-------------------------------------------------------------------------------
51 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
54 * The processor starts at 0xfffffffc and the code is executed
56 * in memory, but as long we don't jump around before relocating.
57 * board_init lies at a quite high address and when the cpu has
58 * jumped there, everything is ok.
59 * This works because the cpu gives the FLASH (CS0) the whole
60 * address space at startup, and board_init lies as a echo of
61 * the flash somewhere up there in the memorymap.
63 * board_init will change CS0 to be positioned at the correct
64 * address and (s)dram will be positioned at address 0
68 #include <timestamp.h>
71 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
73 #include <ppc_asm.tmpl>
76 #include <asm/cache.h>
78 #include <asm/ppc4xx-isram.h>
80 #ifndef CONFIG_IDENT_STRING
81 #define CONFIG_IDENT_STRING ""
84 #ifdef CONFIG_SYS_INIT_DCACHE_CS
85 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
88 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
89 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
90 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
93 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
96 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
97 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
98 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
101 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
104 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
105 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
106 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
109 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
112 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
113 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
114 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
117 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
120 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
121 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
122 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
125 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
128 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
129 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
130 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
133 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
136 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
137 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
138 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
141 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
144 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
145 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
146 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
156 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
157 * used as temporary stack pointer for the primordial stack
159 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
160 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
161 EBC_BXAP_TWT_ENCODE(7) | \
162 EBC_BXAP_BCE_DISABLE | \
163 EBC_BXAP_BCT_2TRANS | \
164 EBC_BXAP_CSN_ENCODE(0) | \
165 EBC_BXAP_OEN_ENCODE(0) | \
166 EBC_BXAP_WBN_ENCODE(0) | \
167 EBC_BXAP_WBF_ENCODE(0) | \
168 EBC_BXAP_TH_ENCODE(2) | \
169 EBC_BXAP_RE_DISABLED | \
170 EBC_BXAP_SOR_NONDELAYED | \
171 EBC_BXAP_BEM_WRITEONLY | \
172 EBC_BXAP_PEN_DISABLED)
173 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
174 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
175 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
179 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
180 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
181 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
183 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
185 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
186 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
190 * Unless otherwise overriden, enable two 128MB cachable instruction regions
191 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
192 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
194 #if !defined(CONFIG_SYS_FLASH_BASE)
195 /* If not already defined, set it to the "last" 128MByte region */
196 # define CONFIG_SYS_FLASH_BASE 0xf8000000
198 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
199 # define CONFIG_SYS_ICACHE_SACR_VALUE \
200 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
201 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
202 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
203 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
205 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
206 # define CONFIG_SYS_DCACHE_SACR_VALUE \
208 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
210 #define function_prolog(func_name) .text; \
214 #define function_epilog(func_name) .type func_name,@function; \
215 .size func_name,.-func_name
217 /* We don't want the MMU yet.
220 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
223 .extern ext_bus_cntlr_init
224 #ifdef CONFIG_NAND_U_BOOT
225 .extern reconfig_tlb0
229 * Set up GOT: Global Offset Table
231 * Use r12 to access the GOT
233 #if !defined(CONFIG_NAND_SPL)
235 GOT_ENTRY(_GOT2_TABLE_)
236 GOT_ENTRY(_FIXUP_TABLE_)
239 GOT_ENTRY(_start_of_vectors)
240 GOT_ENTRY(_end_of_vectors)
241 GOT_ENTRY(transfer_to_handler)
243 GOT_ENTRY(__init_end)
245 GOT_ENTRY(__bss_start)
247 #endif /* CONFIG_NAND_SPL */
249 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
251 * NAND U-Boot image is started from offset 0
254 #if defined(CONFIG_440)
258 bl cpu_init_f /* run low-level CPU init code (from Flash) */
262 #if defined(CONFIG_SYS_RAMBOOT)
264 * 4xx RAM-booting U-Boot image is started from offset 0
271 * 440 Startup -- on reset only the top 4k of the effective
272 * address space is mapped in by an entry in the instruction
273 * and data shadow TLB. The .bootpg section is located in the
274 * top 4k & does only what's necessary to map in the the rest
275 * of the boot rom. Once the boot rom is mapped in we can
276 * proceed with normal startup.
278 * NOTE: CS0 only covers the top 2MB of the effective address
282 #if defined(CONFIG_440)
283 #if !defined(CONFIG_NAND_SPL)
284 .section .bootpg,"ax"
288 /**************************************************************************/
290 /*--------------------------------------------------------------------+
291 | 440EPX BUP Change - Hardware team request
292 +--------------------------------------------------------------------*/
293 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
298 /*----------------------------------------------------------------+
299 | Core bug fix. Clear the esr
300 +-----------------------------------------------------------------*/
303 /*----------------------------------------------------------------*/
304 /* Clear and set up some registers. */
305 /*----------------------------------------------------------------*/
306 iccci r0,r0 /* NOTE: operands not used for 440 */
307 dccci r0,r0 /* NOTE: operands not used for 440 */
314 /* NOTE: 440GX adds machine check status regs */
315 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
322 /*----------------------------------------------------------------*/
324 /*----------------------------------------------------------------*/
325 /* Disable store gathering & broadcast, guarantee inst/data
326 * cache block touch, force load/store alignment
327 * (see errata 1.12: 440_33)
329 lis r1,0x0030 /* store gathering & broadcast disable */
330 ori r1,r1,0x6000 /* cache touch */
333 /*----------------------------------------------------------------*/
334 /* Initialize debug */
335 /*----------------------------------------------------------------*/
337 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
338 bne skip_debug_init /* if set, don't clear debug register */
351 mtspr SPRN_DBSR,r1 /* Clear all valid bits */
354 #if defined (CONFIG_440SPE)
355 /*----------------------------------------------------------------+
356 | Initialize Core Configuration Reg1.
357 | a. ICDPEI: Record even parity. Normal operation.
358 | b. ICTPEI: Record even parity. Normal operation.
359 | c. DCTPEI: Record even parity. Normal operation.
360 | d. DCDPEI: Record even parity. Normal operation.
361 | e. DCUPEI: Record even parity. Normal operation.
362 | f. DCMPEI: Record even parity. Normal operation.
363 | g. FCOM: Normal operation
364 | h. MMUPEI: Record even parity. Normal operation.
365 | i. FFF: Flush only as much data as necessary.
366 | j. TCS: Timebase increments from CPU clock.
367 +-----------------------------------------------------------------*/
371 /*----------------------------------------------------------------+
372 | Reset the timebase.
373 | The previous write to CCR1 sets the timebase source.
374 +-----------------------------------------------------------------*/
379 /*----------------------------------------------------------------*/
380 /* Setup interrupt vectors */
381 /*----------------------------------------------------------------*/
382 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
384 mtspr SPRN_IVOR0,r1 /* Critical input */
386 mtspr SPRN_IVOR1,r1 /* Machine check */
388 mtspr SPRN_IVOR2,r1 /* Data storage */
390 mtspr SPRN_IVOR3,r1 /* Instruction storage */
392 mtspr SPRN_IVOR4,r1 /* External interrupt */
394 mtspr SPRN_IVOR5,r1 /* Alignment */
396 mtspr SPRN_IVOR6,r1 /* Program check */
398 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
400 mtspr SPRN_IVOR8,r1 /* System call */
402 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
404 mtspr SPRN_IVOR10,r1 /* Decrementer */
406 mtspr SPRN_IVOR13,r1 /* Data TLB error */
408 mtspr SPRN_IVOR14,r1 /* Instr TLB error */
410 mtspr SPRN_IVOR15,r1 /* Debug */
412 /*----------------------------------------------------------------*/
413 /* Configure cache regions */
414 /*----------------------------------------------------------------*/
432 /*----------------------------------------------------------------*/
433 /* Cache victim limits */
434 /*----------------------------------------------------------------*/
435 /* floors 0, ceiling max to use the entire cache -- nothing locked
442 /*----------------------------------------------------------------+
443 |Initialize MMUCR[STID] = 0.
444 +-----------------------------------------------------------------*/
451 /*----------------------------------------------------------------*/
452 /* Clear all TLB entries -- TID = 0, TS = 0 */
453 /*----------------------------------------------------------------*/
455 #ifdef CONFIG_SYS_RAMBOOT
456 li r4,0 /* Start with TLB #0 */
458 li r4,1 /* Start with TLB #1 */
460 li r1,64 /* 64 TLB entries */
461 sub r1,r1,r4 /* calculate last TLB # */
464 #ifdef CONFIG_SYS_RAMBOOT
465 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
466 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
467 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
469 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
472 tlbnxt: addi r4,r4,1 /* Next TLB */
475 /*----------------------------------------------------------------*/
476 /* TLB entry setup -- step thru tlbtab */
477 /*----------------------------------------------------------------*/
478 #if defined(CONFIG_440SPE)
479 /*----------------------------------------------------------------*/
480 /* We have different TLB tables for revA and rev B of 440SPe */
481 /*----------------------------------------------------------------*/
493 bl tlbtab /* Get tlbtab pointer */
496 li r1,0x003f /* 64 TLB entries max */
502 #ifdef CONFIG_SYS_RAMBOOT
503 tlbre r3,r4,0 /* Read contents from TLB word #0 */
504 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
505 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
509 beq 2f /* 0 marks end */
512 tlbwe r0,r4,0 /* TLB Word 0 */
513 tlbwe r1,r4,1 /* TLB Word 1 */
514 tlbwe r2,r4,2 /* TLB Word 2 */
515 tlbnx2: addi r4,r4,1 /* Next TLB */
518 /*----------------------------------------------------------------*/
519 /* Continue from 'normal' start */
520 /*----------------------------------------------------------------*/
526 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
530 #endif /* CONFIG_440 */
533 * r3 - 1st arg to board_init(): IMMP pointer
534 * r4 - 2nd arg to board_init(): boot flag
536 #ifndef CONFIG_NAND_SPL
538 .long 0x27051956 /* U-Boot Magic Number */
539 .globl version_string
541 .ascii U_BOOT_VERSION
542 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
543 .ascii CONFIG_IDENT_STRING, "\0"
545 . = EXC_OFF_SYS_RESET
546 .globl _start_of_vectors
549 /* Critical input. */
550 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
554 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
556 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
557 #endif /* CONFIG_440 */
559 /* Data Storage exception. */
560 STD_EXCEPTION(0x300, DataStorage, UnknownException)
562 /* Instruction Storage exception. */
563 STD_EXCEPTION(0x400, InstStorage, UnknownException)
565 /* External Interrupt exception. */
566 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
568 /* Alignment exception. */
571 EXCEPTION_PROLOG(SRR0, SRR1)
576 addi r3,r1,STACK_FRAME_OVERHEAD
577 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
579 /* Program check exception */
582 EXCEPTION_PROLOG(SRR0, SRR1)
583 addi r3,r1,STACK_FRAME_OVERHEAD
584 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
588 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
589 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
590 STD_EXCEPTION(0xa00, APU, UnknownException)
592 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
595 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
596 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
598 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
599 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
600 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
602 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
604 .globl _end_of_vectors
611 /*****************************************************************************/
612 #if defined(CONFIG_440)
614 /*----------------------------------------------------------------*/
615 /* Clear and set up some registers. */
616 /*----------------------------------------------------------------*/
619 mtspr SPRN_DEC,r0 /* prevent dec exceptions */
620 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
622 mtspr SPRN_TSR,r1 /* clear all timer exception status */
623 mtspr SPRN_TCR,r0 /* disable all */
624 mtspr SPRN_ESR,r0 /* clear exception syndrome register */
625 mtxer r0 /* clear integer exception register */
627 /*----------------------------------------------------------------*/
628 /* Debug setup -- some (not very good) ice's need an event*/
629 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
630 /* value you need in this case 0x8cff 0000 should do the trick */
631 /*----------------------------------------------------------------*/
632 #if defined(CONFIG_SYS_INIT_DBCR)
635 mtspr SPRN_DBSR,r1 /* Clear all status bits */
636 lis r0,CONFIG_SYS_INIT_DBCR@h
637 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
642 /*----------------------------------------------------------------*/
643 /* Setup the internal SRAM */
644 /*----------------------------------------------------------------*/
647 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
648 /* Clear Dcache to use as RAM */
649 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
650 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
651 addis r4,r0,CONFIG_SYS_INIT_RAM_END@h
652 ori r4,r4,CONFIG_SYS_INIT_RAM_END@l
653 rlwinm. r5,r4,0,27,31
665 * Lock the init-ram/stack in d-cache, so that other regions
666 * may use d-cache as well
667 * Note, that this current implementation locks exactly 4k
668 * of d-cache, so please make sure that you don't define a
669 * bigger init-ram area. Take a look at the lwmon5 440EPx
670 * implementation as a reference.
674 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
690 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
692 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
693 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
694 /* not all PPC's have internal SRAM usable as L2-cache */
695 #if defined(CONFIG_440GX) || \
696 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
697 defined(CONFIG_460SX)
698 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
699 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
701 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
702 mtdcr L2_CACHE_CFG,r1
708 and r1,r1,r2 /* Disable parity check */
711 and r1,r1,r2 /* Disable pwr mgmt */
714 lis r1,0x8000 /* BAS = 8000_0000 */
715 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
716 ori r1,r1,0x0980 /* first 64k */
717 mtdcr ISRAM0_SB0CR,r1
719 ori r1,r1,0x0980 /* second 64k */
720 mtdcr ISRAM0_SB1CR,r1
722 ori r1,r1, 0x0980 /* third 64k */
723 mtdcr ISRAM0_SB2CR,r1
725 ori r1,r1, 0x0980 /* fourth 64k */
726 mtdcr ISRAM0_SB3CR,r1
727 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
728 lis r1,0x0000 /* BAS = X_0000_0000 */
729 ori r1,r1,0x0984 /* first 64k */
730 mtdcr ISRAM0_SB0CR,r1
732 ori r1,r1,0x0984 /* second 64k */
733 mtdcr ISRAM0_SB1CR,r1
735 ori r1,r1, 0x0984 /* third 64k */
736 mtdcr ISRAM0_SB2CR,r1
738 ori r1,r1, 0x0984 /* fourth 64k */
739 mtdcr ISRAM0_SB3CR,r1
740 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
744 and r1,r1,r2 /* Disable parity check */
747 and r1,r1,r2 /* Disable pwr mgmt */
750 lis r1,0x0004 /* BAS = 4_0004_0000 */
751 ori r1,r1,0x0984 /* 64k */
752 mtdcr ISRAM1_SB0CR,r1
754 #elif defined(CONFIG_460SX)
755 lis r1,0x0000 /* BAS = 0000_0000 */
756 ori r1,r1,0x0B84 /* first 128k */
757 mtdcr ISRAM0_SB0CR,r1
759 ori r1,r1,0x0B84 /* second 128k */
760 mtdcr ISRAM0_SB1CR,r1
762 ori r1,r1, 0x0B84 /* third 128k */
763 mtdcr ISRAM0_SB2CR,r1
765 ori r1,r1, 0x0B84 /* fourth 128k */
766 mtdcr ISRAM0_SB3CR,r1
767 #elif defined(CONFIG_440GP)
768 ori r1,r1,0x0380 /* 8k rw */
769 mtdcr ISRAM0_SB0CR,r1
770 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
772 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
774 /*----------------------------------------------------------------*/
775 /* Setup the stack in internal SRAM */
776 /*----------------------------------------------------------------*/
777 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
778 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
781 stwu r0,-4(r1) /* Terminate call chain */
783 stwu r1,-8(r1) /* Save back chain and move SP */
784 lis r0,RESET_VECTOR@h /* Address of reset vector */
785 ori r0,r0, RESET_VECTOR@l
786 stwu r1,-8(r1) /* Save back chain and move SP */
787 stw r0,+12(r1) /* Save return addr (underflow vect) */
789 #ifdef CONFIG_NAND_SPL
790 bl nand_boot_common /* will not return */
794 bl cpu_init_f /* run low-level CPU init code (from Flash) */
798 #endif /* CONFIG_440 */
800 /*****************************************************************************/
802 /*----------------------------------------------------------------------- */
803 /* Set up some machine state registers. */
804 /*----------------------------------------------------------------------- */
805 addi r0,r0,0x0000 /* initialize r0 to zero */
806 mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */
807 mttcr r0 /* timer control register */
808 mtexier r0 /* disable all interrupts */
809 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
810 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
811 mtdbsr r4 /* clear/reset the dbsr */
812 mtexisr r4 /* clear all pending interrupts */
814 mtexier r4 /* enable critical exceptions */
815 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
816 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
817 mtiocr r4 /* since bit not used) & DRC to latch */
818 /* data bus on rising edge of CAS */
819 /*----------------------------------------------------------------------- */
821 /*----------------------------------------------------------------------- */
823 /*----------------------------------------------------------------------- */
824 /* Invalidate i-cache and d-cache TAG arrays. */
825 /*----------------------------------------------------------------------- */
826 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
827 addi r4,0,1024 /* 1/4 of I-cache */
832 addic. r3,r3,-16 /* move back one cache line */
833 bne ..cloop /* loop back to do rest until r3 = 0 */
836 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
837 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
840 /* first copy IOP480 register base address into r3 */
841 addis r3,0,0x5000 /* IOP480 register base address hi */
842 /* ori r3,r3,0x0000 / IOP480 register base address lo */
845 /* use r4 as the working variable */
846 /* turn on CS3 (LOCCTL.7) */
847 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
848 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
849 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
852 #ifdef CONFIG_DASA_SIM
853 /* use r4 as the working variable */
854 /* turn on MA17 (LOCCTL.7) */
855 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
856 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
857 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
860 /* turn on MA16..13 (LCS0BRD.12 = 0) */
861 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
862 andi. r4,r4,0xefff /* make bit 12 = 0 */
863 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
865 /* make sure above stores all comlete before going on */
868 /* last thing, set local init status done bit (DEVINIT.31) */
869 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
870 oris r4,r4,0x8000 /* make bit 31 = 1 */
871 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
873 /* clear all pending interrupts and disable all interrupts */
874 li r4,-1 /* set p1 to 0xffffffff */
875 stw r4,0x1b0(r3) /* clear all pending interrupts */
876 stw r4,0x1b8(r3) /* clear all pending interrupts */
877 li r4,0 /* set r4 to 0 */
878 stw r4,0x1b4(r3) /* disable all interrupts */
879 stw r4,0x1bc(r3) /* disable all interrupts */
881 /* make sure above stores all comlete before going on */
884 /* Set-up icache cacheability. */
885 lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
886 ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
890 /* Set-up dcache cacheability. */
891 lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
892 ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
895 addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
896 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
897 li r0, 0 /* Make room for stack frame header and */
898 stwu r0, -4(r1) /* clear final stack frame so that */
899 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
901 GET_GOT /* initialize GOT access */
903 bl board_init_f /* run first part of init code (from Flash) */
905 #endif /* CONFIG_IOP480 */
907 /*****************************************************************************/
908 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
909 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
910 defined(CONFIG_405EX) || defined(CONFIG_405)
911 /*----------------------------------------------------------------------- */
912 /* Clear and set up some registers. */
913 /*----------------------------------------------------------------------- */
915 #if !defined(CONFIG_405EX)
919 * On 405EX, completely clearing the SGR leads to PPC hangup
920 * upon PCIe configuration access. The PCIe memory regions
921 * need to be guarded!
928 mtesr r4 /* clear Exception Syndrome Reg */
929 mttcr r4 /* clear Timer Control Reg */
930 mtxer r4 /* clear Fixed-Point Exception Reg */
931 mtevpr r4 /* clear Exception Vector Prefix Reg */
932 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
933 /* dbsr is cleared by setting bits to 1) */
934 mtdbsr r4 /* clear/reset the dbsr */
936 /* Invalidate the i- and d-caches. */
940 /* Set-up icache cacheability. */
941 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
942 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
946 /* Set-up dcache cacheability. */
947 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
948 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
951 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
952 && !defined (CONFIG_XILINX_405)
953 /*----------------------------------------------------------------------- */
954 /* Tune the speed and size for flash CS0 */
955 /*----------------------------------------------------------------------- */
956 bl ext_bus_cntlr_init
959 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
961 * For boards that don't have OCM and can't use the data cache
962 * for their primordial stack, setup stack here directly after the
963 * SDRAM is initialized in ext_bus_cntlr_init.
965 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
966 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
968 li r0, 0 /* Make room for stack frame header and */
969 stwu r0, -4(r1) /* clear final stack frame so that */
970 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
972 * Set up a dummy frame to store reset vector as return address.
973 * this causes stack underflow to reset board.
975 stwu r1, -8(r1) /* Save back chain and move SP */
976 lis r0, RESET_VECTOR@h /* Address of reset vector */
977 ori r0, r0, RESET_VECTOR@l
978 stwu r1, -8(r1) /* Save back chain and move SP */
979 stw r0, +12(r1) /* Save return addr (underflow vect) */
980 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
982 #if defined(CONFIG_405EP)
983 /*----------------------------------------------------------------------- */
984 /* DMA Status, clear to come up clean */
985 /*----------------------------------------------------------------------- */
986 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
990 bl ppc405ep_init /* do ppc405ep specific init */
991 #endif /* CONFIG_405EP */
993 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
994 #if defined(CONFIG_405EZ)
995 /********************************************************************
996 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
997 *******************************************************************/
999 * We can map the OCM on the PLB3, so map it at
1000 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
1002 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1003 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1004 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1005 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
1006 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1007 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
1010 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1011 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1012 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1013 mtdcr OCM0_DSRC1, r3 /* Set Data Side */
1014 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
1015 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1016 mtdcr OCM0_DSRC2, r3 /* Set Data Side */
1017 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
1018 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
1019 mtdcr OCM0_DISDPC,r3
1022 #else /* CONFIG_405EZ */
1023 /********************************************************************
1024 * Setup OCM - On Chip Memory
1025 *******************************************************************/
1029 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
1030 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
1031 and r3, r3, r0 /* disable data-side IRAM */
1032 and r4, r4, r0 /* disable data-side IRAM */
1033 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
1034 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
1037 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1038 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1039 mtdcr OCM0_DSARC, r3
1040 addis r4, 0, 0xC000 /* OCM data area enabled */
1041 mtdcr OCM0_DSCNTL, r4
1043 #endif /* CONFIG_405EZ */
1046 /*----------------------------------------------------------------------- */
1047 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1048 /*----------------------------------------------------------------------- */
1049 #ifdef CONFIG_SYS_INIT_DCACHE_CS
1051 mtdcr EBC0_CFGADDR, r4
1052 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
1053 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
1054 mtdcr EBC0_CFGDATA, r4
1057 mtdcr EBC0_CFGADDR, r4
1058 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
1059 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
1060 mtdcr EBC0_CFGDATA, r4
1063 * Enable the data cache for the 128MB storage access control region
1064 * at CONFIG_SYS_INIT_RAM_ADDR.
1067 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1068 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1072 * Preallocate data cache lines to be used to avoid a subsequent
1073 * cache miss and an ensuing machine check exception when exceptions
1078 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1079 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1081 lis r4, CONFIG_SYS_INIT_RAM_END@h
1082 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1085 * Convert the size, in bytes, to the number of cache lines/blocks
1088 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1089 srwi r5, r4, L1_CACHE_SHIFT
1095 /* Preallocate the computed number of cache blocks. */
1096 ..alloc_dcache_block:
1098 addi r3, r3, L1_CACHE_BYTES
1099 bdnz ..alloc_dcache_block
1103 * Load the initial stack pointer and data area and convert the size,
1104 * in bytes, to the number of words to initialize to a known value.
1106 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
1107 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
1109 lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
1110 ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
1113 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1114 ori r2, r2, CONFIG_SYS_INIT_RAM_END@l
1116 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1117 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1124 * Make room for stack frame header and clear final stack frame so
1125 * that stack backtraces terminate cleanly.
1131 * Set up a dummy frame to store reset vector as return address.
1132 * this causes stack underflow to reset board.
1134 stwu r1, -8(r1) /* Save back chain and move SP */
1135 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1136 ori r0, r0, RESET_VECTOR@l
1137 stwu r1, -8(r1) /* Save back chain and move SP */
1138 stw r0, +12(r1) /* Save return addr (underflow vect) */
1140 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1141 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1146 /* Set up Stack at top of OCM */
1147 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1148 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1150 /* Set up a zeroized stack frame so that backtrace works right */
1156 * Set up a dummy frame to store reset vector as return address.
1157 * this causes stack underflow to reset board.
1159 stwu r1, -8(r1) /* Save back chain and move SP */
1160 lis r0, RESET_VECTOR@h /* Address of reset vector */
1161 ori r0, r0, RESET_VECTOR@l
1162 stwu r1, -8(r1) /* Save back chain and move SP */
1163 stw r0, +12(r1) /* Save return addr (underflow vect) */
1164 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1166 #ifdef CONFIG_NAND_SPL
1167 bl nand_boot_common /* will not return */
1169 GET_GOT /* initialize GOT access */
1171 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1173 /* NEVER RETURNS! */
1174 bl board_init_f /* run first part of init code (from Flash) */
1175 #endif /* CONFIG_NAND_SPL */
1177 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1178 /*----------------------------------------------------------------------- */
1181 #ifndef CONFIG_NAND_SPL
1183 * This code finishes saving the registers to the exception frame
1184 * and jumps to the appropriate handler for the exception.
1185 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1187 .globl transfer_to_handler
1188 transfer_to_handler:
1198 andi. r24,r23,0x3f00 /* get vector offset */
1202 mtspr SPRG2,r22 /* r1 is now kernel sp */
1203 lwz r24,0(r23) /* virtual address of handler */
1204 lwz r23,4(r23) /* where to go when done */
1209 rfi /* jump to handler, enable MMU */
1212 mfmsr r28 /* Disable interrupts */
1216 SYNC /* Some chip revs need this... */
1231 lwz r2,_NIP(r1) /* Restore environment */
1242 mfmsr r28 /* Disable interrupts */
1246 SYNC /* Some chip revs need this... */
1261 lwz r2,_NIP(r1) /* Restore environment */
1273 mfmsr r28 /* Disable interrupts */
1277 SYNC /* Some chip revs need this... */
1292 lwz r2,_NIP(r1) /* Restore environment */
1294 mtspr SPRN_MCSRR0,r2
1295 mtspr SPRN_MCSRR1,r0
1301 #endif /* CONFIG_440 */
1309 /*------------------------------------------------------------------------------- */
1310 /* Function: out16 */
1311 /* Description: Output 16 bits */
1312 /*------------------------------------------------------------------------------- */
1318 /*------------------------------------------------------------------------------- */
1319 /* Function: out16r */
1320 /* Description: Byte reverse and output 16 bits */
1321 /*------------------------------------------------------------------------------- */
1327 /*------------------------------------------------------------------------------- */
1328 /* Function: out32r */
1329 /* Description: Byte reverse and output 32 bits */
1330 /*------------------------------------------------------------------------------- */
1336 /*------------------------------------------------------------------------------- */
1337 /* Function: in16 */
1338 /* Description: Input 16 bits */
1339 /*------------------------------------------------------------------------------- */
1345 /*------------------------------------------------------------------------------- */
1346 /* Function: in16r */
1347 /* Description: Input 16 bits and byte reverse */
1348 /*------------------------------------------------------------------------------- */
1354 /*------------------------------------------------------------------------------- */
1355 /* Function: in32r */
1356 /* Description: Input 32 bits and byte reverse */
1357 /*------------------------------------------------------------------------------- */
1364 * void relocate_code (addr_sp, gd, addr_moni)
1366 * This "function" does not return, instead it continues in RAM
1367 * after relocating the monitor code.
1369 * r3 = Relocated stack pointer
1370 * r4 = Relocated global data pointer
1371 * r5 = Relocated text pointer
1373 .globl relocate_code
1375 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1377 * We need to flush the initial global data (gd_t) before the dcache
1378 * will be invalidated.
1381 /* Save registers */
1386 /* Flush initial global data range */
1388 addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
1389 bl flush_dcache_range
1391 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1393 * Undo the earlier data cache set-up for the primordial stack and
1394 * data area. First, invalidate the data cache and then disable data
1395 * cacheability for that area. Finally, restore the EBC values, if
1399 /* Invalidate the primordial stack and data area in cache */
1400 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1401 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1403 lis r4, CONFIG_SYS_INIT_RAM_END@h
1404 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1407 bl invalidate_dcache_range
1409 /* Disable cacheability for the region */
1411 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1412 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1416 /* Restore the EBC parameters */
1418 mtdcr EBC0_CFGADDR, r3
1420 ori r3, r3, PBxAP_VAL@l
1421 mtdcr EBC0_CFGDATA, r3
1424 mtdcr EBC0_CFGADDR, r3
1426 ori r3, r3, PBxCR_VAL@l
1427 mtdcr EBC0_CFGDATA, r3
1428 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1430 /* Restore registers */
1434 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1436 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1438 * Unlock the previously locked d-cache
1442 /* set TFLOOR/NFLOOR to 0 again */
1458 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1460 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1461 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1462 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1463 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1464 defined(CONFIG_460SX)
1466 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1467 * to speed up the boot process. Now this cache needs to be disabled.
1469 iccci 0,0 /* Invalidate inst cache */
1470 dccci 0,0 /* Invalidate data cache, now no longer our stack */
1474 /* Clear all potential pending exceptions */
1477 #ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH
1478 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1480 addi r1,r0,0x0000 /* Default TLB entry is #0 */
1481 #endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */
1482 tlbre r0,r1,0x0002 /* Read contents */
1483 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1484 tlbwe r0,r1,0x0002 /* Save it out */
1487 #endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */
1488 mr r1, r3 /* Set new stack pointer */
1489 mr r9, r4 /* Save copy of Init Data pointer */
1490 mr r10, r5 /* Save copy of Destination Address */
1493 mr r3, r5 /* Destination Address */
1494 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1495 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1496 lwz r5, GOT(__init_end)
1498 li r6, L1_CACHE_BYTES /* Cache Line Size */
1503 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1509 /* First our own GOT */
1511 /* then the one used by the C code */
1521 beq cr1,4f /* In place copy is not necessary */
1522 beq 7f /* Protect against 0 count */
1541 * Now flush the cache: note that we must start from a cache aligned
1542 * address. Otherwise we might miss one cache line.
1546 beq 7f /* Always flush prefetch queue in any case */
1554 sync /* Wait for all dcbst to complete on bus */
1560 7: sync /* Wait for all icbi to complete on bus */
1564 * We are done. Do not return, instead branch to second part of board
1565 * initialization, now running from RAM.
1568 addi r0, r10, in_ram - _start + _START_OFFSET
1570 blr /* NEVER RETURNS! */
1575 * Relocation Function, r12 point to got2+0x8000
1577 * Adjust got2 pointers, no need to check for 0, this code
1578 * already puts a few entries in the table.
1580 li r0,__got2_entries@sectoff@l
1581 la r3,GOT(_GOT2_TABLE_)
1582 lwz r11,GOT(_GOT2_TABLE_)
1594 * Now adjust the fixups and the pointers to the fixups
1595 * in case we need to move ourselves again.
1597 li r0,__fixup_entries@sectoff@l
1598 lwz r3,GOT(_FIXUP_TABLE_)
1612 * Now clear BSS segment
1614 lwz r3,GOT(__bss_start)
1637 mr r3, r9 /* Init Data pointer */
1638 mr r4, r10 /* Destination Address */
1642 * Copy exception vector code to low memory
1645 * r7: source address, r8: end address, r9: target address
1649 mflr r4 /* save link register */
1651 lwz r7, GOT(_start_of_vectors)
1652 lwz r8, GOT(_end_of_vectors)
1654 li r9, 0x100 /* reset vector always at 0x100 */
1657 bgelr /* return if r7>=r8 - just in case */
1667 * relocate `hdlr' and `int_return' entries
1669 li r7, .L_MachineCheck - _start + _START_OFFSET
1670 li r8, Alignment - _start + _START_OFFSET
1673 addi r7, r7, 0x100 /* next exception vector */
1677 li r7, .L_Alignment - _start + _START_OFFSET
1680 li r7, .L_ProgramCheck - _start + _START_OFFSET
1684 li r7, .L_FPUnavailable - _start + _START_OFFSET
1687 li r7, .L_Decrementer - _start + _START_OFFSET
1690 li r7, .L_APU - _start + _START_OFFSET
1693 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1696 li r7, .L_DataTLBError - _start + _START_OFFSET
1698 #else /* CONFIG_440 */
1699 li r7, .L_PIT - _start + _START_OFFSET
1702 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1705 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1707 #endif /* CONFIG_440 */
1709 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1712 #if !defined(CONFIG_440)
1713 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1714 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1715 mtmsr r7 /* change MSR */
1718 b __440_msr_continue
1721 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1722 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1730 mtlr r4 /* restore link register */
1733 #if defined(CONFIG_440)
1734 /*----------------------------------------------------------------------------+
1736 +----------------------------------------------------------------------------*/
1737 function_prolog(dcbz_area)
1738 rlwinm. r5,r4,0,27,31
1739 rlwinm r5,r4,27,5,31
1748 function_epilog(dcbz_area)
1749 #endif /* CONFIG_440 */
1750 #endif /* CONFIG_NAND_SPL */
1752 /*------------------------------------------------------------------------------- */
1754 /* Description: Input 8 bits */
1755 /*------------------------------------------------------------------------------- */
1761 /*------------------------------------------------------------------------------- */
1762 /* Function: out8 */
1763 /* Description: Output 8 bits */
1764 /*------------------------------------------------------------------------------- */
1770 /*------------------------------------------------------------------------------- */
1771 /* Function: out32 */
1772 /* Description: Output 32 bits */
1773 /*------------------------------------------------------------------------------- */
1779 /*------------------------------------------------------------------------------- */
1780 /* Function: in32 */
1781 /* Description: Input 32 bits */
1782 /*------------------------------------------------------------------------------- */
1788 /**************************************************************************/
1789 /* PPC405EP specific stuff */
1790 /**************************************************************************/
1794 #ifdef CONFIG_BUBINGA
1796 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1797 * function) to support FPGA and NVRAM accesses below.
1800 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1801 ori r3,r3,GPIO0_OSRH@l
1802 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1803 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1806 ori r3,r3,GPIO0_OSRL@l
1807 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1808 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1811 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1812 ori r3,r3,GPIO0_ISR1H@l
1813 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1814 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1816 lis r3,GPIO0_ISR1L@h
1817 ori r3,r3,GPIO0_ISR1L@l
1818 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1819 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1822 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1823 ori r3,r3,GPIO0_TSRH@l
1824 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1825 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1828 ori r3,r3,GPIO0_TSRL@l
1829 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1830 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1833 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1834 ori r3,r3,GPIO0_TCR@l
1835 lis r4,CONFIG_SYS_GPIO0_TCR@h
1836 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1839 li r3,PB1AP /* program EBC bank 1 for RTC access */
1840 mtdcr EBC0_CFGADDR,r3
1841 lis r3,CONFIG_SYS_EBC_PB1AP@h
1842 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1843 mtdcr EBC0_CFGDATA,r3
1845 mtdcr EBC0_CFGADDR,r3
1846 lis r3,CONFIG_SYS_EBC_PB1CR@h
1847 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1848 mtdcr EBC0_CFGDATA,r3
1850 li r3,PB1AP /* program EBC bank 1 for RTC access */
1851 mtdcr EBC0_CFGADDR,r3
1852 lis r3,CONFIG_SYS_EBC_PB1AP@h
1853 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1854 mtdcr EBC0_CFGDATA,r3
1856 mtdcr EBC0_CFGADDR,r3
1857 lis r3,CONFIG_SYS_EBC_PB1CR@h
1858 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1859 mtdcr EBC0_CFGDATA,r3
1861 li r3,PB4AP /* program EBC bank 4 for FPGA access */
1862 mtdcr EBC0_CFGADDR,r3
1863 lis r3,CONFIG_SYS_EBC_PB4AP@h
1864 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1865 mtdcr EBC0_CFGDATA,r3
1867 mtdcr EBC0_CFGADDR,r3
1868 lis r3,CONFIG_SYS_EBC_PB4CR@h
1869 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1870 mtdcr EBC0_CFGDATA,r3
1874 !-----------------------------------------------------------------------
1875 ! Check to see if chip is in bypass mode.
1876 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1877 ! CPU reset Otherwise, skip this step and keep going.
1878 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1879 ! will not be fast enough for the SDRAM (min 66MHz)
1880 !-----------------------------------------------------------------------
1882 mfdcr r5, CPC0_PLLMR1
1883 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1886 beq pll_done /* if SSCS =b'1' then PLL has */
1887 /* already been set */
1888 /* and CPU has been reset */
1889 /* so skip to next section */
1891 #ifdef CONFIG_BUBINGA
1893 !-----------------------------------------------------------------------
1894 ! Read NVRAM to get value to write in PLLMR.
1895 ! If value has not been correctly saved, write default value
1896 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1897 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1899 ! WARNING: This code assumes the first three words in the nvram_t
1900 ! structure in openbios.h. Changing the beginning of
1901 ! the structure will break this code.
1903 !-----------------------------------------------------------------------
1905 addis r3,0,NVRAM_BASE@h
1906 addi r3,r3,NVRAM_BASE@l
1909 addis r5,0,NVRVFY1@h
1910 addi r5,r5,NVRVFY1@l
1911 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1915 addis r5,0,NVRVFY2@h
1916 addi r5,r5,NVRVFY2@l
1917 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1919 addi r3,r3,8 /* Skip over conf_size */
1920 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1921 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1922 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1923 cmpi cr0,0,r5,1 /* See if PLL is locked */
1926 #endif /* CONFIG_BUBINGA */
1930 andi. r5, r4, CPC0_BOOT_SEP@l
1931 bne strap_1 /* serial eeprom present */
1932 addis r5,0,CPLD_REG0_ADDR@h
1933 ori r5,r5,CPLD_REG0_ADDR@l
1936 #endif /* CONFIG_TAIHU */
1938 #if defined(CONFIG_ZEUS)
1940 andi. r5, r4, CPC0_BOOT_SEP@l
1941 bne strap_1 /* serial eeprom present */
1948 mfdcr r3, CPC0_PLLMR0
1949 mfdcr r4, CPC0_PLLMR1
1953 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1954 ori r3,r3,PLLMR0_DEFAULT@l /* */
1955 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1956 ori r4,r4,PLLMR1_DEFAULT@l /* */
1961 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1962 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1963 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1964 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1967 mfdcr r3, CPC0_PLLMR0
1968 mfdcr r4, CPC0_PLLMR1
1969 #endif /* CONFIG_TAIHU */
1972 b pll_write /* Write the CPC0_PLLMR with new value */
1976 !-----------------------------------------------------------------------
1977 ! Clear Soft Reset Register
1978 ! This is needed to enable PCI if not booting from serial EPROM
1979 !-----------------------------------------------------------------------
1989 blr /* return to main code */
1992 !-----------------------------------------------------------------------------
1993 ! Function: pll_write
1994 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1996 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1998 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1999 ! 4. PLL Reset is cleared
2000 ! 5. Wait 100us for PLL to lock
2001 ! 6. A core reset is performed
2002 ! Input: r3 = Value to write to CPC0_PLLMR0
2003 ! Input: r4 = Value to write to CPC0_PLLMR1
2005 !-----------------------------------------------------------------------------
2011 ori r5,r5,0x0101 /* Stop the UART clocks */
2012 mtdcr CPC0_UCR,r5 /* Before changing PLL */
2014 mfdcr r5, CPC0_PLLMR1
2015 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
2016 mtdcr CPC0_PLLMR1,r5
2017 oris r5,r5,0x4000 /* Set PLL Reset */
2018 mtdcr CPC0_PLLMR1,r5
2020 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
2021 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
2022 oris r5,r5,0x4000 /* Set PLL Reset */
2023 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2024 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
2025 mtdcr CPC0_PLLMR1,r5
2028 ! Wait min of 100us for PLL to lock.
2029 ! See CMOS 27E databook for more info.
2030 ! At 200MHz, that means waiting 20,000 instructions
2032 addi r3,0,20000 /* 2000 = 0x4e20 */
2037 oris r5,r5,0x8000 /* Enable PLL */
2038 mtdcr CPC0_PLLMR1,r5 /* Engage */
2041 * Reset CPU to guarantee timings are OK
2042 * Not sure if this is needed...
2045 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
2046 /* execution will continue from the poweron */
2047 /* vector of 0xfffffffc */
2048 #endif /* CONFIG_405EP */
2050 #if defined(CONFIG_440)
2051 /*----------------------------------------------------------------------------+
2053 +----------------------------------------------------------------------------*/
2054 function_prolog(mttlb3)
2057 function_epilog(mttlb3)
2059 /*----------------------------------------------------------------------------+
2061 +----------------------------------------------------------------------------*/
2062 function_prolog(mftlb3)
2065 function_epilog(mftlb3)
2067 /*----------------------------------------------------------------------------+
2069 +----------------------------------------------------------------------------*/
2070 function_prolog(mttlb2)
2073 function_epilog(mttlb2)
2075 /*----------------------------------------------------------------------------+
2077 +----------------------------------------------------------------------------*/
2078 function_prolog(mftlb2)
2081 function_epilog(mftlb2)
2083 /*----------------------------------------------------------------------------+
2085 +----------------------------------------------------------------------------*/
2086 function_prolog(mttlb1)
2089 function_epilog(mttlb1)
2091 /*----------------------------------------------------------------------------+
2093 +----------------------------------------------------------------------------*/
2094 function_prolog(mftlb1)
2097 function_epilog(mftlb1)
2098 #endif /* CONFIG_440 */
2100 #if defined(CONFIG_NAND_SPL)
2102 * void nand_boot_relocate(dst, src, bytes)
2104 * r3 = Destination address to copy code to (in SDRAM)
2105 * r4 = Source address to copy code from
2106 * r5 = size to copy in bytes
2114 * Copy SPL from icache into SDRAM
2126 * Calculate "corrected" link register, so that we "continue"
2127 * in execution in destination range
2129 sub r3,r7,r6 /* r3 = src - dst */
2130 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2136 * First initialize SDRAM. It has to be available *before* calling
2139 lis r3,CONFIG_SYS_SDRAM_BASE@h
2140 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
2144 * Now copy the 4k SPL code into SDRAM and continue execution
2147 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2148 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2149 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2150 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2151 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2152 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2153 bl nand_boot_relocate
2156 * We're running from SDRAM now!!!
2158 * It is necessary for 4xx systems to relocate from running at
2159 * the original location (0xfffffxxx) to somewhere else (SDRAM
2160 * preferably). This is because CS0 needs to be reconfigured for
2161 * NAND access. And we can't reconfigure this CS when currently
2162 * "running" from it.
2166 * Finally call nand_boot() to load main NAND U-Boot image from
2167 * NAND and jump to it.
2169 bl nand_boot /* will not return */
2170 #endif /* CONFIG_NAND_SPL */