2 * arch/ppc/platform/85xx/mpc85xx_cds_common.c
4 * MPC85xx CDS board specific routines
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
8 * Copyright 2004 Freescale Semiconductor, Inc
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/config.h>
17 #include <linux/stddef.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/reboot.h>
22 #include <linux/pci.h>
23 #include <linux/kdev_t.h>
24 #include <linux/major.h>
25 #include <linux/console.h>
26 #include <linux/delay.h>
27 #include <linux/irq.h>
28 #include <linux/seq_file.h>
29 #include <linux/serial.h>
30 #include <linux/module.h>
31 #include <linux/root_dev.h>
32 #include <linux/initrd.h>
33 #include <linux/tty.h>
34 #include <linux/serial_core.h>
35 #include <linux/fsl_devices.h>
37 #include <asm/system.h>
38 #include <asm/pgtable.h>
40 #include <asm/atomic.h>
44 #include <asm/machdep.h>
46 #include <asm/open_pic.h>
47 #include <asm/i8259.h>
48 #include <asm/bootinfo.h>
49 #include <asm/pci-bridge.h>
50 #include <asm/mpc85xx.h>
52 #include <asm/immap_85xx.h>
53 #include <asm/immap_cpm2.h>
54 #include <asm/ppc_sys.h>
57 #include <mm/mmu_decl.h>
58 #include <syslib/cpm2_pic.h>
59 #include <syslib/ppc85xx_common.h>
60 #include <syslib/ppc85xx_setup.h>
64 unsigned long isa_io_base = 0;
65 unsigned long isa_mem_base = 0;
68 extern unsigned long total_memory; /* in mm/init */
70 unsigned char __res[sizeof (bd_t)];
72 static int cds_pci_slot = 2;
73 static volatile u8 * cadmus;
75 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
77 static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
89 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
96 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
97 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
98 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
99 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
100 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
101 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
102 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
103 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
104 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
105 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
106 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
107 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
108 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
109 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
110 #if defined(CONFIG_PCI)
111 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
112 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
113 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */
114 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */
116 0x0, /* External 0: */
117 0x0, /* External 1: */
118 0x0, /* External 2: */
119 0x0, /* External 3: */
121 0x0, /* External 4: */
122 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
123 0x0, /* External 6: */
124 0x0, /* External 7: */
125 0x0, /* External 8: */
126 0x0, /* External 9: */
127 0x0, /* External 10: */
128 #if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
129 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */
131 0x0, /* External 11: */
135 /* ************************************************************************ */
137 mpc85xx_cds_show_cpuinfo(struct seq_file *m)
139 uint pvid, svid, phid1;
140 uint memsize = total_memory;
141 bd_t *binfo = (bd_t *) __res;
144 /* get the core frequency */
145 freq = binfo->bi_intfreq;
147 pvid = mfspr(SPRN_PVR);
148 svid = mfspr(SPRN_SVR);
150 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
151 seq_printf(m, "Machine\t\t: CDS - MPC%s (%x)\n", cur_ppc_sys_spec->ppc_sys_name, cadmus[CM_VER]);
152 seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
153 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
154 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
156 /* Display cpu Pll setting */
157 phid1 = mfspr(SPRN_HID1);
158 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
160 /* Display the amount of memory */
161 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
167 static void cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
169 while((irq = cpm2_get_irq(regs)) >= 0)
173 static struct irqaction cpm2_irqaction = {
174 .handler = cpm2_cascade,
175 .flags = SA_INTERRUPT,
176 .mask = CPU_MASK_NONE,
177 .name = "cpm2_cascade",
179 #endif /* CONFIG_CPM2 */
182 mpc85xx_cds_init_IRQ(void)
184 bd_t *binfo = (bd_t *) __res;
187 /* Determine the Physical Address of the OpenPIC regs */
188 phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
189 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
190 OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
191 OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
193 /* Skip reserved space and internal sources */
194 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
195 /* Map PIC IRQs 0-11 */
196 openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
198 /* we let openpic interrupts starting from an offset, to
199 * leave space for cascading interrupts underneath.
201 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
204 openpic_hookup_cascade(PIRQ0A, "82c59 cascade", i8259_irq);
206 for (i = 0; i < NUM_8259_INTERRUPTS; i++)
207 irq_desc[i].handler = &i8259_pic;
216 setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
227 mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
229 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
233 /* Handle PCI1 interrupts */
234 char pci_irq_table[][4] =
236 * PCI IDSEL/INTPIN->INTLINE
240 /* Note IRQ assignment for slots is based on which slot the elysium is
241 * in -- in this setup elysium is in slot #2 (this PIRQA as first
242 * interrupt on slot */
244 { 0, 1, 2, 3 }, /* 16 - PMC */
245 { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
246 { 0, 1, 2, 3 }, /* 18 - Slot 1 */
247 { 1, 2, 3, 0 }, /* 19 - Slot 2 */
248 { 2, 3, 0, 1 }, /* 20 - Slot 3 */
249 { 3, 0, 1, 2 }, /* 21 - Slot 4 */
252 const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
255 for (i = 0; i < 6; i++)
256 for (j = 0; j < 4; j++)
257 pci_irq_table[i][j] =
258 ((pci_irq_table[i][j] + 5 -
259 cds_pci_slot) & 0x3) + PIRQ0A;
261 return PCI_IRQ_TABLE_LOOKUP;
263 /* Handle PCI2 interrupts (if we have one) */
264 char pci_irq_table[][4] =
267 * We only have one slot and one interrupt
268 * going to PIRQA - PIRQD */
269 { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
272 const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;
274 return PCI_IRQ_TABLE_LOOKUP;
278 #define ARCADIA_HOST_BRIDGE_IDSEL 17
279 #define ARCADIA_2ND_BRIDGE_IDSEL 3
281 extern int mpc85xx_pci1_last_busno;
284 mpc85xx_exclude_device(u_char bus, u_char devfn)
286 if (bus == 0 && PCI_SLOT(devfn) == 0)
287 return PCIBIOS_DEVICE_NOT_FOUND;
288 #ifdef CONFIG_85xx_PCI2
289 if (mpc85xx_pci1_last_busno)
290 if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0)
291 return PCIBIOS_DEVICE_NOT_FOUND;
293 /* We explicitly do not go past the Tundra 320 Bridge */
294 if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
295 return PCIBIOS_DEVICE_NOT_FOUND;
296 if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
297 return PCIBIOS_DEVICE_NOT_FOUND;
299 return PCIBIOS_SUCCESSFUL;
303 mpc85xx_cds_enable_via(struct pci_controller *hose)
308 early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
309 if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
312 /* Configure P2P so that we can reach bus 1 */
313 early_write_config_byte(hose, 0, 0x88, PCI_PRIMARY_BUS, 0);
314 early_write_config_byte(hose, 0, 0x88, PCI_SECONDARY_BUS, 1);
315 early_write_config_byte(hose, 0, 0x88, PCI_SUBORDINATE_BUS, 0xff);
317 early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
318 early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
320 if ((vid != PCI_VENDOR_ID_VIA) ||
321 (did != PCI_DEVICE_ID_VIA_82C686))
324 /* Enable USB and IDE functions */
325 early_write_config_byte(hose, 1, 0x10, 0x48, 0x08);
329 mpc85xx_cds_fixup_via(struct pci_controller *hose)
334 early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
335 if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
339 * Force the backplane P2P bridge to have a window
340 * open from 0x00000000-0x00001fff in PCI I/O space.
341 * This allows legacy I/O (i8259, etc) on the VIA
342 * southbridge to be accessed.
344 early_write_config_byte(hose, 0, 0x88, PCI_IO_BASE, 0x00);
345 early_write_config_word(hose, 0, 0x88, PCI_IO_BASE_UPPER16, 0x0000);
346 early_write_config_byte(hose, 0, 0x88, PCI_IO_LIMIT, 0x10);
347 early_write_config_word(hose, 0, 0x88, PCI_IO_LIMIT_UPPER16, 0x0000);
349 early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
350 early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
351 if ((vid != PCI_VENDOR_ID_VIA) ||
352 (did != PCI_DEVICE_ID_VIA_82C686))
356 * Since the P2P window was forced to cover the fixed
357 * legacy I/O addresses, it is necessary to manually
358 * place the base addresses for the IDE and USB functions
359 * within this window.
361 /* Function 1, IDE */
362 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_0, 0x1ff8);
363 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_1, 0x1ff4);
364 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_2, 0x1fe8);
365 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_3, 0x1fe4);
366 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_4, 0x1fd0);
368 /* Function 2, USB ports 0-1 */
369 early_write_config_dword(hose, 1, 0x12, PCI_BASE_ADDRESS_4, 0x1fa0);
371 /* Function 3, USB ports 2-3 */
372 early_write_config_dword(hose, 1, 0x13, PCI_BASE_ADDRESS_4, 0x1f80);
374 /* Function 5, Power Management */
375 early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_0, 0x1e00);
376 early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_1, 0x1dfc);
377 early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_2, 0x1df8);
379 /* Function 6, AC97 Interface */
380 early_write_config_dword(hose, 1, 0x16, PCI_BASE_ADDRESS_0, 0x1c00);
384 mpc85xx_cds_pcibios_fixup(void)
386 struct pci_dev *dev = NULL;
389 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
390 PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
392 * U-Boot does not set the enable bits
393 * for the IDE device. Force them on here.
395 pci_read_config_byte(dev, 0x40, &c);
396 c |= 0x03; /* IDE: Chip Enable Bits */
397 pci_write_config_byte(dev, 0x40, c);
400 * Since only primary interface works, force the
401 * IDE function to standard primary IDE interrupt
405 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
409 * Force legacy USB interrupt routing
411 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
412 PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
414 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
417 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
418 PCI_DEVICE_ID_VIA_82C586_2, dev))) {
420 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
423 #endif /* CONFIG_PCI */
427 /* ************************************************************************
429 * Setup the architecture
433 mpc85xx_cds_setup_arch(void)
435 bd_t *binfo = (bd_t *) __res;
437 struct gianfar_platform_data *pdata;
439 /* get the core frequency */
440 freq = binfo->bi_intfreq;
442 printk("mpc85xx_cds_setup_arch\n");
448 cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
449 cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
450 printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);
452 /* Setup TODC access */
453 TODC_INIT(TODC_TYPE_DS1743,
456 ioremap(CDS_RTC_ADDR, CDS_RTC_SIZE),
459 /* Set loops_per_jiffy to a half-way reasonable value,
460 for use until calibrate_delay gets called. */
461 loops_per_jiffy = freq / HZ;
464 /* VIA IDE configuration */
465 ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
467 /* setup PCI host bridges */
468 mpc85xx_setup_hose();
471 #ifdef CONFIG_SERIAL_8250
472 mpc85xx_early_serial_map();
475 #ifdef CONFIG_SERIAL_TEXT_DEBUG
476 /* Invalidate the entry we stole earlier the serial ports
477 * should be properly mapped */
478 invalidate_tlbcam_entry(NUM_TLBCAMS - 1);
481 /* setup the board related information for the enet controllers */
482 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
483 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
484 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
486 /* fixup phy address */
487 pdata->phy_reg_addr += binfo->bi_immr_base;
488 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
490 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
491 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
492 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
494 /* fixup phy address */
495 pdata->phy_reg_addr += binfo->bi_immr_base;
496 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
499 #ifdef CONFIG_BLK_DEV_INITRD
501 ROOT_DEV = Root_RAM0;
504 #ifdef CONFIG_ROOT_NFS
507 ROOT_DEV = Root_HDA1;
511 /* ************************************************************************ */
513 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
514 unsigned long r6, unsigned long r7)
516 /* parse_bootinfo must always be called first */
517 parse_bootinfo(find_bootinfo());
520 * If we were passed in a board information, copy it into the
521 * residual data area.
524 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
528 #ifdef CONFIG_SERIAL_TEXT_DEBUG
530 bd_t *binfo = (bd_t *) __res;
533 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
534 settlbcam(NUM_TLBCAMS - 1, binfo->bi_immr_base,
535 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
537 memset(&p, 0, sizeof (p));
538 p.iotype = SERIAL_IO_MEM;
539 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
540 p.uartclk = binfo->bi_busfreq;
544 memset(&p, 0, sizeof (p));
545 p.iotype = SERIAL_IO_MEM;
546 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
547 p.uartclk = binfo->bi_busfreq;
553 #if defined(CONFIG_BLK_DEV_INITRD)
555 * If the init RAM disk has been configured in, and there's a valid
556 * starting address for it, set it up.
559 initrd_start = r4 + KERNELBASE;
560 initrd_end = r5 + KERNELBASE;
562 #endif /* CONFIG_BLK_DEV_INITRD */
564 /* Copy the kernel command line arguments to a safe place. */
567 *(char *) (r7 + KERNELBASE) = 0;
568 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
571 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
573 /* setup the PowerPC module struct */
574 ppc_md.setup_arch = mpc85xx_cds_setup_arch;
575 ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
577 ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
578 ppc_md.get_irq = openpic_get_irq;
580 ppc_md.restart = mpc85xx_restart;
581 ppc_md.power_off = mpc85xx_power_off;
582 ppc_md.halt = mpc85xx_halt;
584 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
586 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
588 ppc_md.time_init = todc_time_init;
589 ppc_md.set_rtc_time = todc_set_rtc_time;
590 ppc_md.get_rtc_time = todc_get_rtc_time;
592 ppc_md.nvram_read_val = todc_direct_read_val;
593 ppc_md.nvram_write_val = todc_direct_write_val;
595 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
596 ppc_md.progress = gen550_progress;
597 #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
598 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
599 ppc_md.early_serial_map = mpc85xx_early_serial_map;
600 #endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
603 ppc_md.progress("mpc85xx_cds_init(): exit", 0);