2 * arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
4 * Copyright (C) 1997 Geert Uytterhoeven
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
11 #include <linux/config.h>
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/sched.h>
15 #include <linux/init.h>
16 #include <linux/irq.h>
17 #include <linux/interrupt.h>
18 #include <linux/sysdev.h>
19 #include <linux/errno.h>
20 #include <asm/ptrace.h>
21 #include <asm/signal.h>
24 #include <asm/sections.h>
25 #include <asm/open_pic.h>
26 #include <asm/i8259.h>
28 #include "open_pic_defs.h"
30 #if defined(CONFIG_PRPMC800) || defined(CONFIG_85xx)
31 #define OPENPIC_BIG_ENDIAN
34 void __iomem *OpenPIC_Addr;
35 static volatile struct OpenPIC __iomem *OpenPIC = NULL;
38 * We define OpenPIC_InitSenses table thusly:
39 * bit 0x1: sense, 0 for edge and 1 for level.
40 * bit 0x2: polarity, 0 for negative, 1 for positive.
42 u_int OpenPIC_NumInitSenses __initdata = 0;
43 u_char *OpenPIC_InitSenses __initdata = NULL;
44 extern int use_of_interrupt_tree;
46 static u_int NumProcessors;
47 static u_int NumSources;
48 static int open_pic_irq_offset;
49 static volatile OpenPIC_Source __iomem *ISR[NR_IRQS];
50 static int openpic_cascade_irq = -1;
51 static int (*openpic_cascade_fn)(struct pt_regs *);
53 /* Global Operations */
54 static void openpic_disable_8259_pass_through(void);
55 static void openpic_set_spurious(u_int vector);
58 /* Interprocessor Interrupts */
59 static void openpic_initipi(u_int ipi, u_int pri, u_int vector);
60 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *);
63 /* Timer Interrupts */
64 static void openpic_inittimer(u_int timer, u_int pri, u_int vector);
65 static void openpic_maptimer(u_int timer, cpumask_t cpumask);
67 /* Interrupt Sources */
68 static void openpic_enable_irq(u_int irq);
69 static void openpic_disable_irq(u_int irq);
70 static void openpic_initirq(u_int irq, u_int pri, u_int vector, int polarity,
72 static void openpic_mapirq(u_int irq, cpumask_t cpumask, cpumask_t keepmask);
75 * These functions are not used but the code is kept here
76 * for completeness and future reference.
79 static void openpic_enable_8259_pass_through(void);
80 static u_int openpic_get_spurious(void);
81 static void openpic_set_sense(u_int irq, int sense);
85 * Description of the openpic for the higher-level irq code
87 static void openpic_end_irq(unsigned int irq_nr);
88 static void openpic_ack_irq(unsigned int irq_nr);
89 static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask);
91 struct hw_interrupt_type open_pic = {
92 .typename = " OpenPIC ",
93 .enable = openpic_enable_irq,
94 .disable = openpic_disable_irq,
95 .ack = openpic_ack_irq,
96 .end = openpic_end_irq,
97 .set_affinity = openpic_set_affinity,
101 static void openpic_end_ipi(unsigned int irq_nr);
102 static void openpic_ack_ipi(unsigned int irq_nr);
103 static void openpic_enable_ipi(unsigned int irq_nr);
104 static void openpic_disable_ipi(unsigned int irq_nr);
106 struct hw_interrupt_type open_pic_ipi = {
107 .typename = " OpenPIC ",
108 .enable = openpic_enable_ipi,
109 .disable = openpic_disable_ipi,
110 .ack = openpic_ack_ipi,
111 .end = openpic_end_ipi,
113 #endif /* CONFIG_SMP */
116 * Accesses to the current processor's openpic registers
119 #define THIS_CPU Processor[cpu]
120 #define DECL_THIS_CPU int cpu = smp_hw_index[smp_processor_id()]
121 #define CHECK_THIS_CPU check_arg_cpu(cpu)
123 #define THIS_CPU Processor[0]
124 #define DECL_THIS_CPU
125 #define CHECK_THIS_CPU
126 #endif /* CONFIG_SMP */
129 #define check_arg_ipi(ipi) \
130 if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \
131 printk("open_pic.c:%d: invalid ipi %d\n", __LINE__, ipi);
132 #define check_arg_timer(timer) \
133 if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \
134 printk("open_pic.c:%d: invalid timer %d\n", __LINE__, timer);
135 #define check_arg_vec(vec) \
136 if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \
137 printk("open_pic.c:%d: invalid vector %d\n", __LINE__, vec);
138 #define check_arg_pri(pri) \
139 if (pri < 0 || pri >= OPENPIC_NUM_PRI) \
140 printk("open_pic.c:%d: invalid priority %d\n", __LINE__, pri);
142 * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
143 * data has probably been corrupted and we're going to panic or deadlock later
146 #define check_arg_irq(irq) \
147 if (irq < open_pic_irq_offset || irq >= NumSources+open_pic_irq_offset \
148 || ISR[irq - open_pic_irq_offset] == 0) { \
149 printk("open_pic.c:%d: invalid irq %d\n", __LINE__, irq); \
151 #define check_arg_cpu(cpu) \
152 if (cpu < 0 || cpu >= NumProcessors){ \
153 printk("open_pic.c:%d: invalid cpu %d\n", __LINE__, cpu); \
156 #define check_arg_ipi(ipi) do {} while (0)
157 #define check_arg_timer(timer) do {} while (0)
158 #define check_arg_vec(vec) do {} while (0)
159 #define check_arg_pri(pri) do {} while (0)
160 #define check_arg_irq(irq) do {} while (0)
161 #define check_arg_cpu(cpu) do {} while (0)
164 u_int openpic_read(volatile u_int __iomem *addr)
168 #ifdef OPENPIC_BIG_ENDIAN
176 static inline void openpic_write(volatile u_int __iomem *addr, u_int val)
178 #ifdef OPENPIC_BIG_ENDIAN
185 static inline u_int openpic_readfield(volatile u_int __iomem *addr, u_int mask)
187 u_int val = openpic_read(addr);
191 inline void openpic_writefield(volatile u_int __iomem *addr, u_int mask,
194 u_int val = openpic_read(addr);
195 openpic_write(addr, (val & ~mask) | (field & mask));
198 static inline void openpic_clearfield(volatile u_int __iomem *addr, u_int mask)
200 openpic_writefield(addr, mask, 0);
203 static inline void openpic_setfield(volatile u_int __iomem *addr, u_int mask)
205 openpic_writefield(addr, mask, mask);
208 static void openpic_safe_writefield(volatile u_int __iomem *addr, u_int mask,
211 openpic_setfield(addr, OPENPIC_MASK);
212 while (openpic_read(addr) & OPENPIC_ACTIVITY);
213 openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
217 /* yes this is right ... bug, feature, you decide! -- tgall */
218 u_int openpic_read_IPI(volatile u_int __iomem * addr)
221 #if defined(OPENPIC_BIG_ENDIAN) || defined(CONFIG_POWER3)
229 /* because of the power3 be / le above, this is needed */
230 inline void openpic_writefield_IPI(volatile u_int __iomem * addr, u_int mask, u_int field)
232 u_int val = openpic_read_IPI(addr);
233 openpic_write(addr, (val & ~mask) | (field & mask));
236 static inline void openpic_clearfield_IPI(volatile u_int __iomem *addr, u_int mask)
238 openpic_writefield_IPI(addr, mask, 0);
241 static inline void openpic_setfield_IPI(volatile u_int __iomem *addr, u_int mask)
243 openpic_writefield_IPI(addr, mask, mask);
246 static void openpic_safe_writefield_IPI(volatile u_int __iomem *addr, u_int mask, u_int field)
248 openpic_setfield_IPI(addr, OPENPIC_MASK);
250 /* wait until it's not in use */
251 /* BenH: Is this code really enough ? I would rather check the result
252 * and eventually retry ...
254 while(openpic_read_IPI(addr) & OPENPIC_ACTIVITY);
256 openpic_writefield_IPI(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
258 #endif /* CONFIG_SMP */
260 #ifdef CONFIG_EPIC_SERIAL_MODE
261 /* On platforms that may use EPIC serial mode, the default is enabled. */
262 int epic_serial_mode = 1;
264 static void __init openpic_eicr_set_clk(u_int clkval)
266 openpic_writefield(&OpenPIC->Global.Global_Configuration1,
267 OPENPIC_EICR_S_CLK_MASK, (clkval << 28));
270 static void __init openpic_enable_sie(void)
272 openpic_setfield(&OpenPIC->Global.Global_Configuration1,
277 #if defined(CONFIG_EPIC_SERIAL_MODE)
278 static void openpic_reset(void)
280 openpic_setfield(&OpenPIC->Global.Global_Configuration0,
281 OPENPIC_CONFIG_RESET);
282 while (openpic_readfield(&OpenPIC->Global.Global_Configuration0,
283 OPENPIC_CONFIG_RESET))
288 void __init openpic_set_sources(int first_irq, int num_irqs, void __iomem *first_ISR)
290 volatile OpenPIC_Source __iomem *src = first_ISR;
293 last_irq = first_irq + num_irqs;
294 if (last_irq > NumSources)
295 NumSources = last_irq;
297 src = &((struct OpenPIC __iomem *)OpenPIC_Addr)->Source[first_irq];
298 for (i = first_irq; i < last_irq; ++i, ++src)
303 * The `offset' parameter defines where the interrupts handled by the
304 * OpenPIC start in the space of interrupt numbers that the kernel knows
305 * about. In other words, the OpenPIC's IRQ0 is numbered `offset' in the
306 * kernel's interrupt numbering scheme.
307 * We assume there is only one OpenPIC.
309 void __init openpic_init(int offset)
316 printk("No OpenPIC found !\n");
319 OpenPIC = (volatile struct OpenPIC __iomem *)OpenPIC_Addr;
321 #ifdef CONFIG_EPIC_SERIAL_MODE
322 /* Have to start from ground zero.
327 if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122);
329 t = openpic_read(&OpenPIC->Global.Feature_Reporting0);
330 switch (t & OPENPIC_FEATURE_VERSION_MASK) {
344 NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>
345 OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
347 openpic_set_sources(0,
348 ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
349 OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1,
351 printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at %p\n",
352 version, NumProcessors, NumSources, OpenPIC);
353 timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency);
355 printk("OpenPIC timer frequency is %d.%06d MHz\n",
356 timerfreq / 1000000, timerfreq % 1000000);
358 open_pic_irq_offset = offset;
360 /* Initialize timer interrupts */
361 if ( ppc_md.progress ) ppc_md.progress("openpic: timer",0x3ba);
362 for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
363 /* Disabled, Priority 0 */
364 openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+offset);
366 openpic_maptimer(i, CPU_MASK_NONE);
370 /* Initialize IPI interrupts */
371 if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb);
372 for (i = 0; i < OPENPIC_NUM_IPI; i++) {
373 /* Disabled, Priority 10..13 */
374 openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+offset);
375 /* IPIs are per-CPU */
376 irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
377 irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
381 /* Initialize external interrupts */
382 if (ppc_md.progress) ppc_md.progress("openpic: external",0x3bc);
384 openpic_set_priority(0xf);
386 /* Init all external sources, including possibly the cascade. */
387 for (i = 0; i < NumSources; i++) {
393 /* the bootloader may have left it enabled (bad !) */
394 openpic_disable_irq(i+offset);
396 sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \
397 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE);
399 if (sense & IRQ_SENSE_MASK)
400 irq_desc[i+offset].status = IRQ_LEVEL;
402 /* Enabled, Priority 8 */
403 openpic_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK),
404 (sense & IRQ_SENSE_MASK));
406 openpic_mapirq(i, CPU_MASK_CPU0, CPU_MASK_NONE);
409 /* Init descriptors */
410 for (i = offset; i < NumSources + offset; i++)
411 irq_desc[i].handler = &open_pic;
413 /* Initialize the spurious interrupt */
414 if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd);
415 openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
416 openpic_disable_8259_pass_through();
417 #ifdef CONFIG_EPIC_SERIAL_MODE
418 if (epic_serial_mode) {
419 openpic_eicr_set_clk(7); /* Slowest value until we know better */
420 openpic_enable_sie();
423 openpic_set_priority(0);
425 if (ppc_md.progress) ppc_md.progress("openpic: exit",0x222);
429 static void openpic_enable_8259_pass_through(void)
431 openpic_clearfield(&OpenPIC->Global.Global_Configuration0,
432 OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
436 static void openpic_disable_8259_pass_through(void)
438 openpic_setfield(&OpenPIC->Global.Global_Configuration0,
439 OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
443 * Find out the current interrupt
445 u_int openpic_irq(void)
451 vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge,
452 OPENPIC_VECTOR_MASK);
456 void openpic_eoi(void)
461 openpic_write(&OpenPIC->THIS_CPU.EOI, 0);
462 /* Handle PCI write posting */
463 (void)openpic_read(&OpenPIC->THIS_CPU.EOI);
466 u_int openpic_get_priority(void)
471 return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority,
472 OPENPIC_CURRENT_TASK_PRIORITY_MASK);
475 void openpic_set_priority(u_int pri)
481 openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority,
482 OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);
486 * Get/set the spurious vector
489 static u_int openpic_get_spurious(void)
491 return openpic_readfield(&OpenPIC->Global.Spurious_Vector,
492 OPENPIC_VECTOR_MASK);
496 static void openpic_set_spurious(u_int vec)
499 openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
505 * Convert a cpu mask from logical to physical cpu numbers.
507 static inline cpumask_t physmask(cpumask_t cpumask)
510 cpumask_t mask = CPU_MASK_NONE;
512 cpus_and(cpumask, cpu_online_map, cpumask);
514 for (i = 0; i < NR_CPUS; i++)
515 if (cpu_isset(i, cpumask))
516 cpu_set(smp_hw_index[i], mask);
521 #define physmask(cpumask) (cpumask)
524 void openpic_reset_processor_phys(u_int mask)
526 openpic_write(&OpenPIC->Global.Processor_Initialization, mask);
529 #if defined(CONFIG_SMP) || defined(CONFIG_PM)
530 static DEFINE_SPINLOCK(openpic_setup_lock);
535 * Initialize an interprocessor interrupt (and disable it)
537 * ipi: OpenPIC interprocessor interrupt number
538 * pri: interrupt source priority
539 * vec: the vector it will produce
541 static void __init openpic_initipi(u_int ipi, u_int pri, u_int vec)
546 openpic_safe_writefield_IPI(&OpenPIC->Global.IPI_Vector_Priority(ipi),
547 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
548 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
552 * Send an IPI to one or more CPUs
554 * Externally called, however, it takes an IPI number (0...OPENPIC_NUM_IPI)
555 * and not a system-wide interrupt number
557 void openpic_cause_IPI(u_int ipi, cpumask_t cpumask)
563 openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi),
564 cpus_addr(physmask(cpumask))[0]);
567 void openpic_request_IPIs(void)
572 * Make sure this matches what is defined in smp.c for
573 * smp_message_{pass|recv}() or what shows up in
574 * /proc/interrupts will be wrong!!! --Troy */
579 /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
580 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset,
581 openpic_ipi_action, SA_INTERRUPT,
582 "IPI0 (call function)", NULL);
583 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+1,
584 openpic_ipi_action, SA_INTERRUPT,
585 "IPI1 (reschedule)", NULL);
586 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+2,
587 openpic_ipi_action, SA_INTERRUPT,
588 "IPI2 (invalidate tlb)", NULL);
589 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+3,
590 openpic_ipi_action, SA_INTERRUPT,
591 "IPI3 (xmon break)", NULL);
593 for ( i = 0; i < OPENPIC_NUM_IPI ; i++ )
594 openpic_enable_ipi(OPENPIC_VEC_IPI+open_pic_irq_offset+i);
598 * Do per-cpu setup for SMP systems.
600 * Get IPI's working and start taking interrupts.
604 void __devinit do_openpic_setup_cpu(void)
606 #ifdef CONFIG_IRQ_ALL_CPUS
608 cpumask_t msk = CPU_MASK_NONE;
610 spin_lock(&openpic_setup_lock);
612 #ifdef CONFIG_IRQ_ALL_CPUS
613 cpu_set(smp_hw_index[smp_processor_id()], msk);
615 /* let the openpic know we want intrs. default affinity
616 * is 0xffffffff until changed via /proc
617 * That's how it's done on x86. If we want it differently, then
618 * we should make sure we also change the default values of irq_affinity
621 for (i = 0; i < NumSources; i++)
622 openpic_mapirq(i, msk, CPU_MASK_ALL);
623 #endif /* CONFIG_IRQ_ALL_CPUS */
624 openpic_set_priority(0);
626 spin_unlock(&openpic_setup_lock);
628 #endif /* CONFIG_SMP */
631 * Initialize a timer interrupt (and disable it)
633 * timer: OpenPIC timer number
634 * pri: interrupt source priority
635 * vec: the vector it will produce
637 static void __init openpic_inittimer(u_int timer, u_int pri, u_int vec)
639 check_arg_timer(timer);
642 openpic_safe_writefield(&OpenPIC->Global.Timer[timer].Vector_Priority,
643 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
644 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
648 * Map a timer interrupt to one or more CPUs
650 static void __init openpic_maptimer(u_int timer, cpumask_t cpumask)
652 cpumask_t phys = physmask(cpumask);
653 check_arg_timer(timer);
654 openpic_write(&OpenPIC->Global.Timer[timer].Destination,
659 * Initalize the interrupt source which will generate an NMI.
660 * This raises the interrupt's priority from 8 to 9.
662 * irq: The logical IRQ which generates an NMI.
665 openpic_init_nmi_irq(u_int irq)
668 openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
669 OPENPIC_PRIORITY_MASK,
670 9 << OPENPIC_PRIORITY_SHIFT);
675 * All functions below take an offset'ed irq argument
680 * Hookup a cascade to the OpenPIC.
683 static struct irqaction openpic_cascade_irqaction = {
684 .handler = no_action,
685 .flags = SA_INTERRUPT,
686 .mask = CPU_MASK_NONE,
690 openpic_hookup_cascade(u_int irq, char *name,
691 int (*cascade_fn)(struct pt_regs *))
693 openpic_cascade_irq = irq;
694 openpic_cascade_fn = cascade_fn;
696 if (setup_irq(irq, &openpic_cascade_irqaction))
697 printk("Unable to get OpenPIC IRQ %d for cascade\n",
698 irq - open_pic_irq_offset);
702 * Enable/disable an external interrupt source
704 * Externally called, irq is an offseted system-wide interrupt number
706 static void openpic_enable_irq(u_int irq)
708 volatile u_int __iomem *vpp;
711 vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
712 openpic_clearfield(vpp, OPENPIC_MASK);
713 /* make sure mask gets to controller before we return to user */
715 mb(); /* sync is probably useless here */
716 } while (openpic_readfield(vpp, OPENPIC_MASK));
719 static void openpic_disable_irq(u_int irq)
721 volatile u_int __iomem *vpp;
725 vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
726 openpic_setfield(vpp, OPENPIC_MASK);
727 /* make sure mask gets to controller before we return to user */
729 mb(); /* sync is probably useless here */
730 vp = openpic_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY);
731 } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
736 * Enable/disable an IPI interrupt source
738 * Externally called, irq is an offseted system-wide interrupt number
740 void openpic_enable_ipi(u_int irq)
742 irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
744 openpic_clearfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
748 void openpic_disable_ipi(u_int irq)
750 irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
752 openpic_setfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
757 * Initialize an interrupt source (and disable it!)
759 * irq: OpenPIC interrupt number
760 * pri: interrupt source priority
761 * vec: the vector it will produce
762 * pol: polarity (1 for positive, 0 for negative)
763 * sense: 1 for level, 0 for edge
766 openpic_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
768 openpic_safe_writefield(&ISR[irq]->Vector_Priority,
769 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
770 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
771 (pri << OPENPIC_PRIORITY_SHIFT) | vec |
772 (pol ? OPENPIC_POLARITY_POSITIVE :
773 OPENPIC_POLARITY_NEGATIVE) |
774 (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE));
778 * Map an interrupt source to one or more CPUs
780 static void openpic_mapirq(u_int irq, cpumask_t physmask, cpumask_t keepmask)
784 if (!cpus_empty(keepmask)) {
785 cpumask_t irqdest = { .bits[0] = openpic_read(&ISR[irq]->Destination) };
786 cpus_and(irqdest, irqdest, keepmask);
787 cpus_or(physmask, physmask, irqdest);
789 openpic_write(&ISR[irq]->Destination, cpus_addr(physmask)[0]);
794 * Set the sense for an interrupt source (and disable it!)
796 * sense: 1 for level, 0 for edge
798 static void openpic_set_sense(u_int irq, int sense)
801 openpic_safe_writefield(&ISR[irq]->Vector_Priority,
803 (sense ? OPENPIC_SENSE_LEVEL : 0));
807 /* No spinlocks, should not be necessary with the OpenPIC
808 * (1 register = 1 interrupt and we have the desc lock).
810 static void openpic_ack_irq(unsigned int irq_nr)
812 #ifdef __SLOW_VERSION__
813 openpic_disable_irq(irq_nr);
816 if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
821 static void openpic_end_irq(unsigned int irq_nr)
823 #ifdef __SLOW_VERSION__
824 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
825 && irq_desc[irq_nr].action)
826 openpic_enable_irq(irq_nr);
828 if ((irq_desc[irq_nr].status & IRQ_LEVEL) != 0)
833 static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask)
835 openpic_mapirq(irq_nr - open_pic_irq_offset, physmask(cpumask), CPU_MASK_NONE);
839 static void openpic_ack_ipi(unsigned int irq_nr)
844 static void openpic_end_ipi(unsigned int irq_nr)
848 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *regs)
850 smp_message_recv(cpl-OPENPIC_VEC_IPI-open_pic_irq_offset, regs);
854 #endif /* CONFIG_SMP */
857 openpic_get_irq(struct pt_regs *regs)
859 int irq = openpic_irq();
862 * Check for the cascade interrupt and call the cascaded
863 * interrupt controller function (usually i8259_irq) if so.
864 * This should move to irq.c eventually. -- paulus
866 if (irq == openpic_cascade_irq && openpic_cascade_fn != NULL) {
867 int cirq = openpic_cascade_fn(regs);
869 /* Allow for the cascade being shared with other devices */
874 } else if (irq == OPENPIC_VEC_SPURIOUS)
881 smp_openpic_message_pass(int target, int msg, unsigned long data, int wait)
883 cpumask_t mask = CPU_MASK_ALL;
884 /* make sure we're sending something that translates to an IPI */
886 printk("SMP %d: smp_message_pass: unknown msg %d\n",
887 smp_processor_id(), msg);
892 openpic_cause_IPI(msg, mask);
894 case MSG_ALL_BUT_SELF:
895 cpu_clear(smp_processor_id(), mask);
896 openpic_cause_IPI(msg, mask);
899 openpic_cause_IPI(msg, cpumask_of_cpu(target));
903 #endif /* CONFIG_SMP */
908 * We implement the IRQ controller as a sysdev and put it
909 * to sleep at powerdown stage (the callback is named suspend,
910 * but it's old semantics, for the Device Model, it's really
911 * powerdown). The possible problem is that another sysdev that
912 * happens to be suspend after this one will have interrupts off,
913 * that may be an issue... For now, this isn't an issue on pmac
917 static u32 save_ipi_vp[OPENPIC_NUM_IPI];
918 static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES];
919 static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];
920 static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];
921 static int openpic_suspend_count;
923 static void openpic_cached_enable_irq(u_int irq)
926 save_irq_src_vp[irq - open_pic_irq_offset] &= ~OPENPIC_MASK;
929 static void openpic_cached_disable_irq(u_int irq)
932 save_irq_src_vp[irq - open_pic_irq_offset] |= OPENPIC_MASK;
935 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
936 * we need something better to deal with that... Maybe switch to S1 for
939 int openpic_suspend(struct sys_device *sysdev, u32 state)
944 spin_lock_irqsave(&openpic_setup_lock, flags);
946 if (openpic_suspend_count++ > 0) {
947 spin_unlock_irqrestore(&openpic_setup_lock, flags);
951 openpic_set_priority(0xf);
953 open_pic.enable = openpic_cached_enable_irq;
954 open_pic.disable = openpic_cached_disable_irq;
956 for (i=0; i<NumProcessors; i++) {
957 save_cpu_task_pri[i] = openpic_read(&OpenPIC->Processor[i].Current_Task_Priority);
958 openpic_writefield(&OpenPIC->Processor[i].Current_Task_Priority,
959 OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf);
962 for (i=0; i<OPENPIC_NUM_IPI; i++)
963 save_ipi_vp[i] = openpic_read(&OpenPIC->Global.IPI_Vector_Priority(i));
964 for (i=0; i<NumSources; i++) {
967 save_irq_src_vp[i] = openpic_read(&ISR[i]->Vector_Priority) & ~OPENPIC_ACTIVITY;
968 save_irq_src_dest[i] = openpic_read(&ISR[i]->Destination);
971 spin_unlock_irqrestore(&openpic_setup_lock, flags);
976 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
977 * we need something better to deal with that... Maybe switch to S1 for
980 int openpic_resume(struct sys_device *sysdev)
984 u32 vppmask = OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
985 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK |
988 spin_lock_irqsave(&openpic_setup_lock, flags);
990 if ((--openpic_suspend_count) > 0) {
991 spin_unlock_irqrestore(&openpic_setup_lock, flags);
995 /* OpenPIC sometimes seem to need some time to be fully back up... */
997 openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
998 } while(openpic_readfield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK)
999 != OPENPIC_VEC_SPURIOUS);
1001 openpic_disable_8259_pass_through();
1003 for (i=0; i<OPENPIC_NUM_IPI; i++)
1004 openpic_write(&OpenPIC->Global.IPI_Vector_Priority(i),
1006 for (i=0; i<NumSources; i++) {
1009 openpic_write(&ISR[i]->Destination, save_irq_src_dest[i]);
1010 openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1011 /* make sure mask gets to controller before we return to user */
1013 openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1014 } while (openpic_readfield(&ISR[i]->Vector_Priority, vppmask)
1015 != (save_irq_src_vp[i] & vppmask));
1017 for (i=0; i<NumProcessors; i++)
1018 openpic_write(&OpenPIC->Processor[i].Current_Task_Priority,
1019 save_cpu_task_pri[i]);
1021 open_pic.enable = openpic_enable_irq;
1022 open_pic.disable = openpic_disable_irq;
1024 openpic_set_priority(0);
1026 spin_unlock_irqrestore(&openpic_setup_lock, flags);
1031 #endif /* CONFIG_PM */
1033 static struct sysdev_class openpic_sysclass = {
1034 set_kset_name("openpic"),
1037 static struct sys_device device_openpic = {
1039 .cls = &openpic_sysclass,
1042 static struct sysdev_driver driver_openpic = {
1044 .suspend = &openpic_suspend,
1045 .resume = &openpic_resume,
1046 #endif /* CONFIG_PM */
1049 static int __init init_openpic_sysfs(void)
1055 printk(KERN_DEBUG "Registering openpic with sysfs...\n");
1056 rc = sysdev_class_register(&openpic_sysclass);
1058 printk(KERN_ERR "Failed registering openpic sys class\n");
1061 rc = sysdev_register(&device_openpic);
1063 printk(KERN_ERR "Failed registering openpic sys device\n");
1066 rc = sysdev_driver_register(&openpic_sysclass, &driver_openpic);
1068 printk(KERN_ERR "Failed registering openpic sys driver\n");
1074 subsys_initcall(init_openpic_sysfs);