2 * arch/ppc64/kernel/mpic.c
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
17 #include <linux/config.h>
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/irq.h>
22 #include <linux/smp.h>
23 #include <linux/interrupt.h>
24 #include <linux/bootmem.h>
25 #include <linux/spinlock.h>
26 #include <linux/pci.h>
28 #include <asm/ptrace.h>
29 #include <asm/signal.h>
31 #include <asm/pgtable.h>
33 #include <asm/machdep.h>
37 #define DBG(fmt...) printk(fmt)
42 static struct mpic *mpics;
43 static struct mpic *mpic_primary;
44 static DEFINE_SPINLOCK(mpic_lock);
48 * Register accessor functions
52 static inline u32 _mpic_read(unsigned int be, volatile u32 __iomem *base,
56 return in_be32(base + (reg >> 2));
58 return in_le32(base + (reg >> 2));
61 static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base,
62 unsigned int reg, u32 value)
65 out_be32(base + (reg >> 2), value);
67 out_le32(base + (reg >> 2), value);
70 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
72 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
73 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
75 if (mpic->flags & MPIC_BROKEN_IPI)
77 return _mpic_read(be, mpic->gregs, offset);
80 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
82 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
84 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value);
87 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
91 if (mpic->flags & MPIC_PRIMARY)
92 cpu = hard_smp_processor_id();
94 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg);
97 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
101 if (mpic->flags & MPIC_PRIMARY)
102 cpu = hard_smp_processor_id();
104 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg, value);
107 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
109 unsigned int isu = src_no >> mpic->isu_shift;
110 unsigned int idx = src_no & mpic->isu_mask;
112 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
113 reg + (idx * MPIC_IRQ_STRIDE));
116 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
117 unsigned int reg, u32 value)
119 unsigned int isu = src_no >> mpic->isu_shift;
120 unsigned int idx = src_no & mpic->isu_mask;
122 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
123 reg + (idx * MPIC_IRQ_STRIDE), value);
126 #define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
127 #define mpic_write(b,r,v) _mpic_write(mpic->flags & MPIC_BIG_ENDIAN,(b),(r),(v))
128 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
129 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
130 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
131 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
132 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
133 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
137 * Low level utility functions
142 /* Check if we have one of those nice broken MPICs with a flipped endian on
143 * reads from IPI registers
145 static void __init mpic_test_broken_ipi(struct mpic *mpic)
149 mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK);
150 r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0);
152 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
153 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
154 mpic->flags |= MPIC_BROKEN_IPI;
158 #ifdef CONFIG_MPIC_BROKEN_U3
160 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
161 * to force the edge setting on the MPIC and do the ack workaround.
163 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source_no)
165 if (source_no >= 128 || !mpic->fixups)
167 return mpic->fixups[source_no].base != NULL;
170 static inline void mpic_apic_end_irq(struct mpic *mpic, unsigned int source_no)
172 struct mpic_irq_fixup *fixup = &mpic->fixups[source_no];
175 spin_lock(&mpic->fixup_lock);
176 writeb(0x11 + 2 * fixup->irq, fixup->base);
177 tmp = readl(fixup->base + 2);
178 writel(tmp | 0x80000000ul, fixup->base + 2);
179 /* config writes shouldn't be posted but let's be safe ... */
180 (void)readl(fixup->base + 2);
181 spin_unlock(&mpic->fixup_lock);
185 static void __init mpic_amd8111_read_irq(struct mpic *mpic, u8 __iomem *devbase)
190 printk(KERN_INFO "mpic: - Workarounds on AMD 8111 @ %p\n", devbase);
192 for (i=0; i < 24; i++) {
193 writeb(0x10 + 2*i, devbase + 0xf2);
194 tmp = readl(devbase + 0xf4);
195 if ((tmp & 0x1) || !(tmp & 0x20))
197 irq = (tmp >> 16) & 0xff;
198 mpic->fixups[irq].irq = i;
199 mpic->fixups[irq].base = devbase + 0xf2;
203 static void __init mpic_amd8131_read_irq(struct mpic *mpic, u8 __iomem *devbase)
208 printk(KERN_INFO "mpic: - Workarounds on AMD 8131 @ %p\n", devbase);
210 for (i=0; i < 4; i++) {
211 writeb(0x10 + 2*i, devbase + 0xba);
212 tmp = readl(devbase + 0xbc);
213 if ((tmp & 0x1) || !(tmp & 0x20))
215 irq = (tmp >> 16) & 0xff;
216 mpic->fixups[irq].irq = i;
217 mpic->fixups[irq].base = devbase + 0xba;
221 static void __init mpic_scan_ioapics(struct mpic *mpic)
224 u8 __iomem *cfgspace;
226 printk(KERN_INFO "mpic: Setting up IO-APICs workarounds for U3\n");
228 /* Allocate fixups array */
229 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
230 BUG_ON(mpic->fixups == NULL);
231 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
234 spin_lock_init(&mpic->fixup_lock);
236 /* Map u3 config space. We assume all IO-APICs are on the primary bus
237 * and slot will never be above "0xf" so we only need to map 32k
239 cfgspace = (unsigned char __iomem *)ioremap(0xf2000000, 0x8000);
240 BUG_ON(cfgspace == NULL);
242 /* Now we scan all slots. We do a very quick scan, we read the header type,
243 * vendor ID and device ID only, that's plenty enough
245 for (devfn = 0; devfn < PCI_DEVFN(0x10,0); devfn ++) {
246 u8 __iomem *devbase = cfgspace + (devfn << 8);
247 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
248 u32 l = readl(devbase + PCI_VENDOR_ID);
249 u16 vendor_id, device_id;
252 DBG("devfn %x, l: %x\n", devfn, l);
254 /* If no device, skip */
255 if (l == 0xffffffff || l == 0x00000000 ||
256 l == 0x0000ffff || l == 0xffff0000)
259 /* Check if it's a multifunction device (only really used
260 * to function 0 though
262 multifunc = !!(hdr_type & 0x80);
263 vendor_id = l & 0xffff;
264 device_id = (l >> 16) & 0xffff;
266 /* If a known device, go to fixup setup code */
267 if (vendor_id == PCI_VENDOR_ID_AMD && device_id == 0x7460)
268 mpic_amd8111_read_irq(mpic, devbase);
269 if (vendor_id == PCI_VENDOR_ID_AMD && device_id == 0x7450)
270 mpic_amd8131_read_irq(mpic, devbase);
272 /* next device, if function 0 */
273 if ((PCI_FUNC(devfn) == 0) && !multifunc)
278 #endif /* CONFIG_MPIC_BROKEN_U3 */
281 /* Find an mpic associated with a given linux interrupt */
282 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
284 struct mpic *mpic = mpics;
287 /* search IPIs first since they may override the main interrupts */
288 if (irq >= mpic->ipi_offset && irq < (mpic->ipi_offset + 4)) {
293 if (irq >= mpic->irq_offset &&
294 irq < (mpic->irq_offset + mpic->irq_count)) {
304 /* Convert a cpu mask from logical to physical cpu numbers. */
305 static inline u32 mpic_physmask(u32 cpumask)
310 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
311 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
316 /* Get the mpic structure from the IPI number */
317 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
319 return container_of(irq_desc[ipi].handler, struct mpic, hc_ipi);
323 /* Get the mpic structure from the irq number */
324 static inline struct mpic * mpic_from_irq(unsigned int irq)
326 return container_of(irq_desc[irq].handler, struct mpic, hc_irq);
330 static inline void mpic_eoi(struct mpic *mpic)
332 mpic_cpu_write(MPIC_CPU_EOI, 0);
333 (void)mpic_cpu_read(MPIC_CPU_WHOAMI);
337 static irqreturn_t mpic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
339 struct mpic *mpic = dev_id;
341 smp_message_recv(irq - mpic->ipi_offset, regs);
344 #endif /* CONFIG_SMP */
347 * Linux descriptor level callbacks
351 static void mpic_enable_irq(unsigned int irq)
353 unsigned int loops = 100000;
354 struct mpic *mpic = mpic_from_irq(irq);
355 unsigned int src = irq - mpic->irq_offset;
357 DBG("%s: enable_irq: %d (src %d)\n", mpic->name, irq, src);
359 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
360 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & ~MPIC_VECPRI_MASK);
362 /* make sure mask gets to controller before we return to user */
365 printk(KERN_ERR "mpic_enable_irq timeout\n");
368 } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK);
371 static void mpic_disable_irq(unsigned int irq)
373 unsigned int loops = 100000;
374 struct mpic *mpic = mpic_from_irq(irq);
375 unsigned int src = irq - mpic->irq_offset;
377 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
379 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
380 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) | MPIC_VECPRI_MASK);
382 /* make sure mask gets to controller before we return to user */
385 printk(KERN_ERR "mpic_enable_irq timeout\n");
388 } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK));
391 static void mpic_end_irq(unsigned int irq)
393 struct mpic *mpic = mpic_from_irq(irq);
395 DBG("%s: end_irq: %d\n", mpic->name, irq);
397 /* We always EOI on end_irq() even for edge interrupts since that
398 * should only lower the priority, the MPIC should have properly
399 * latched another edge interrupt coming in anyway
402 #ifdef CONFIG_MPIC_BROKEN_U3
403 if (mpic->flags & MPIC_BROKEN_U3) {
404 unsigned int src = irq - mpic->irq_offset;
405 if (mpic_is_ht_interrupt(mpic, src))
406 mpic_apic_end_irq(mpic, src);
408 #endif /* CONFIG_MPIC_BROKEN_U3 */
415 static void mpic_enable_ipi(unsigned int irq)
417 struct mpic *mpic = mpic_from_ipi(irq);
418 unsigned int src = irq - mpic->ipi_offset;
420 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
421 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
424 static void mpic_disable_ipi(unsigned int irq)
426 /* NEVER disable an IPI... that's just plain wrong! */
429 static void mpic_end_ipi(unsigned int irq)
431 struct mpic *mpic = mpic_from_ipi(irq);
434 * IPIs are marked IRQ_PER_CPU. This has the side effect of
435 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
436 * applying to them. We EOI them late to avoid re-entering.
437 * We mark IPI's with SA_INTERRUPT as they must run with
443 #endif /* CONFIG_SMP */
445 static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
447 struct mpic *mpic = mpic_from_irq(irq);
451 cpus_and(tmp, cpumask, cpu_online_map);
453 mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_DESTINATION,
454 mpic_physmask(cpus_addr(tmp)[0]));
463 struct mpic * __init mpic_alloc(unsigned long phys_addr,
465 unsigned int isu_size,
466 unsigned int irq_offset,
467 unsigned int irq_count,
468 unsigned int ipi_offset,
469 unsigned char *senses,
470 unsigned int senses_count,
478 mpic = alloc_bootmem(sizeof(struct mpic));
482 memset(mpic, 0, sizeof(struct mpic));
485 mpic->hc_irq.typename = name;
486 mpic->hc_irq.enable = mpic_enable_irq;
487 mpic->hc_irq.disable = mpic_disable_irq;
488 mpic->hc_irq.end = mpic_end_irq;
489 if (flags & MPIC_PRIMARY)
490 mpic->hc_irq.set_affinity = mpic_set_affinity;
492 mpic->hc_ipi.typename = name;
493 mpic->hc_ipi.enable = mpic_enable_ipi;
494 mpic->hc_ipi.disable = mpic_disable_ipi;
495 mpic->hc_ipi.end = mpic_end_ipi;
496 #endif /* CONFIG_SMP */
499 mpic->isu_size = isu_size;
500 mpic->irq_offset = irq_offset;
501 mpic->irq_count = irq_count;
502 mpic->ipi_offset = ipi_offset;
503 mpic->num_sources = 0; /* so far */
504 mpic->senses = senses;
505 mpic->senses_count = senses_count;
507 /* Map the global registers */
508 mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000);
509 mpic->tmregs = mpic->gregs + (MPIC_TIMER_BASE >> 2);
510 BUG_ON(mpic->gregs == NULL);
513 if (flags & MPIC_WANTS_RESET) {
514 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
515 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
516 | MPIC_GREG_GCONF_RESET);
517 while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
518 & MPIC_GREG_GCONF_RESET)
522 /* Read feature register, calculate num CPUs and, for non-ISU
523 * MPICs, num sources as well. On ISU MPICs, sources are counted
526 reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0);
527 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
528 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
530 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
531 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
533 /* Map the per-CPU registers */
534 for (i = 0; i < mpic->num_cpus; i++) {
535 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE +
536 i * MPIC_CPU_STRIDE, 0x1000);
537 BUG_ON(mpic->cpuregs[i] == NULL);
540 /* Initialize main ISU if none provided */
541 if (mpic->isu_size == 0) {
542 mpic->isu_size = mpic->num_sources;
543 mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE,
544 MPIC_IRQ_STRIDE * mpic->isu_size);
545 BUG_ON(mpic->isus[0] == NULL);
547 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
548 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
550 /* Display version */
551 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
565 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %lx, max %d CPUs\n",
566 name, vers, phys_addr, mpic->num_cpus);
567 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", mpic->isu_size,
568 mpic->isu_shift, mpic->isu_mask);
573 if (flags & MPIC_PRIMARY)
579 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
580 unsigned long phys_addr)
582 unsigned int isu_first = isu_num * mpic->isu_size;
584 BUG_ON(isu_num >= MPIC_MAX_ISU);
586 mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size);
587 if ((isu_first + mpic->isu_size) > mpic->num_sources)
588 mpic->num_sources = isu_first + mpic->isu_size;
591 void __init mpic_setup_cascade(unsigned int irq, mpic_cascade_t handler,
594 struct mpic *mpic = mpic_find(irq, NULL);
597 /* Synchronization here is a bit dodgy, so don't try to replace cascade
598 * interrupts on the fly too often ... but normally it's set up at boot.
600 spin_lock_irqsave(&mpic_lock, flags);
602 mpic_disable_irq(mpic->cascade_vec + mpic->irq_offset);
603 mpic->cascade = NULL;
605 mpic->cascade_vec = irq - mpic->irq_offset;
606 mpic->cascade_data = data;
608 mpic->cascade = handler;
609 mpic_enable_irq(irq);
610 spin_unlock_irqrestore(&mpic_lock, flags);
613 void __init mpic_init(struct mpic *mpic)
617 BUG_ON(mpic->num_sources == 0);
619 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
621 /* Set current processor priority to max */
622 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
624 /* Initialize timers: just disable them all */
625 for (i = 0; i < 4; i++) {
626 mpic_write(mpic->tmregs,
627 i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0);
628 mpic_write(mpic->tmregs,
629 i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI,
631 (MPIC_VEC_TIMER_0 + i));
634 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
635 mpic_test_broken_ipi(mpic);
636 for (i = 0; i < 4; i++) {
639 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
640 (MPIC_VEC_IPI_0 + i));
642 if (!(mpic->flags & MPIC_PRIMARY))
644 irq_desc[mpic->ipi_offset+i].status |= IRQ_PER_CPU;
645 irq_desc[mpic->ipi_offset+i].handler = &mpic->hc_ipi;
647 #endif /* CONFIG_SMP */
650 /* Initialize interrupt sources */
651 if (mpic->irq_count == 0)
652 mpic->irq_count = mpic->num_sources;
654 #ifdef CONFIG_MPIC_BROKEN_U3
655 /* Do the ioapic fixups on U3 broken mpic */
656 DBG("MPIC flags: %x\n", mpic->flags);
657 if ((mpic->flags & MPIC_BROKEN_U3) && (mpic->flags & MPIC_PRIMARY))
658 mpic_scan_ioapics(mpic);
659 #endif /* CONFIG_MPIC_BROKEN_U3 */
661 for (i = 0; i < mpic->num_sources; i++) {
662 /* start with vector = source number, and masked */
663 u32 vecpri = MPIC_VECPRI_MASK | i | (8 << MPIC_VECPRI_PRIORITY_SHIFT);
666 /* if it's an IPI, we skip it */
667 if ((mpic->irq_offset + i) >= (mpic->ipi_offset + i) &&
668 (mpic->irq_offset + i) < (mpic->ipi_offset + i + 4))
671 /* do senses munging */
672 if (mpic->senses && i < mpic->senses_count) {
673 if (mpic->senses[i] & IRQ_SENSE_LEVEL)
674 vecpri |= MPIC_VECPRI_SENSE_LEVEL;
675 if (mpic->senses[i] & IRQ_POLARITY_POSITIVE)
676 vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;
678 vecpri |= MPIC_VECPRI_SENSE_LEVEL;
680 /* remember if it was a level interrupts */
681 level = (vecpri & MPIC_VECPRI_SENSE_LEVEL);
683 /* deal with broken U3 */
684 if (mpic->flags & MPIC_BROKEN_U3) {
685 #ifdef CONFIG_MPIC_BROKEN_U3
686 if (mpic_is_ht_interrupt(mpic, i)) {
687 vecpri &= ~(MPIC_VECPRI_SENSE_MASK |
688 MPIC_VECPRI_POLARITY_MASK);
689 vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;
692 printk(KERN_ERR "mpic: BROKEN_U3 set, but CONFIG doesn't match\n");
696 DBG("setup source %d, vecpri: %08x, level: %d\n", i, vecpri,
700 mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri);
701 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
702 1 << get_hard_smp_processor_id(boot_cpuid));
704 /* init linux descriptors */
705 if (i < mpic->irq_count) {
706 irq_desc[mpic->irq_offset+i].status = level ? IRQ_LEVEL : 0;
707 irq_desc[mpic->irq_offset+i].handler = &mpic->hc_irq;
711 /* Init spurrious vector */
712 mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS);
714 /* Disable 8259 passthrough */
715 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
716 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
717 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
719 /* Set current processor priority to 0 */
720 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
725 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
728 struct mpic *mpic = mpic_find(irq, &is_ipi);
732 spin_lock_irqsave(&mpic_lock, flags);
734 reg = mpic_ipi_read(irq - mpic->ipi_offset) & MPIC_VECPRI_PRIORITY_MASK;
735 mpic_ipi_write(irq - mpic->ipi_offset,
736 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
738 reg = mpic_irq_read(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI)
739 & MPIC_VECPRI_PRIORITY_MASK;
740 mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI,
741 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
743 spin_unlock_irqrestore(&mpic_lock, flags);
746 unsigned int mpic_irq_get_priority(unsigned int irq)
749 struct mpic *mpic = mpic_find(irq, &is_ipi);
753 spin_lock_irqsave(&mpic_lock, flags);
755 reg = mpic_ipi_read(irq - mpic->ipi_offset);
757 reg = mpic_irq_read(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI);
758 spin_unlock_irqrestore(&mpic_lock, flags);
759 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
762 void mpic_setup_this_cpu(void)
765 struct mpic *mpic = mpic_primary;
767 u32 msk = 1 << hard_smp_processor_id();
770 BUG_ON(mpic == NULL);
772 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
774 spin_lock_irqsave(&mpic_lock, flags);
776 /* let the mpic know we want intrs. default affinity is 0xffffffff
777 * until changed via /proc. That's how it's done on x86. If we want
778 * it differently, then we should make sure we also change the default
779 * values of irq_affinity in irq.c.
781 if (distribute_irqs) {
782 for (i = 0; i < mpic->num_sources ; i++)
783 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
784 mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk);
787 /* Set current processor priority to 0 */
788 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
790 spin_unlock_irqrestore(&mpic_lock, flags);
791 #endif /* CONFIG_SMP */
795 * XXX: someone who knows mpic should check this.
796 * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
797 * or can we reset the mpic in the new kernel?
799 void mpic_teardown_this_cpu(int secondary)
801 struct mpic *mpic = mpic_primary;
803 u32 msk = 1 << hard_smp_processor_id();
806 BUG_ON(mpic == NULL);
808 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
809 spin_lock_irqsave(&mpic_lock, flags);
811 /* let the mpic know we don't want intrs. */
812 for (i = 0; i < mpic->num_sources ; i++)
813 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
814 mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk);
816 /* Set current processor priority to max */
817 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
819 spin_unlock_irqrestore(&mpic_lock, flags);
823 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
825 struct mpic *mpic = mpic_primary;
827 BUG_ON(mpic == NULL);
829 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
831 mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10,
832 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
835 int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs)
839 irq = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK;
840 DBG("%s: get_one_irq(): %d\n", mpic->name, irq);
842 if (mpic->cascade && irq == mpic->cascade_vec) {
843 DBG("%s: cascading ...\n", mpic->name);
844 irq = mpic->cascade(regs, mpic->cascade_data);
848 if (unlikely(irq == MPIC_VEC_SPURRIOUS))
850 if (irq < MPIC_VEC_IPI_0)
851 return irq + mpic->irq_offset;
852 DBG("%s: ipi %d !\n", mpic->name, irq - MPIC_VEC_IPI_0);
853 return irq - MPIC_VEC_IPI_0 + mpic->ipi_offset;
856 int mpic_get_irq(struct pt_regs *regs)
858 struct mpic *mpic = mpic_primary;
860 BUG_ON(mpic == NULL);
862 return mpic_get_one_irq(mpic, regs);
867 void mpic_request_ipis(void)
869 struct mpic *mpic = mpic_primary;
871 BUG_ON(mpic == NULL);
873 printk("requesting IPIs ... \n");
875 /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
876 request_irq(mpic->ipi_offset+0, mpic_ipi_action, SA_INTERRUPT,
877 "IPI0 (call function)", mpic);
878 request_irq(mpic->ipi_offset+1, mpic_ipi_action, SA_INTERRUPT,
879 "IPI1 (reschedule)", mpic);
880 request_irq(mpic->ipi_offset+2, mpic_ipi_action, SA_INTERRUPT,
881 "IPI2 (unused)", mpic);
882 request_irq(mpic->ipi_offset+3, mpic_ipi_action, SA_INTERRUPT,
883 "IPI3 (debugger break)", mpic);
885 printk("IPIs requested... \n");
887 #endif /* CONFIG_SMP */