2 * arch/ppc64/kernel/pSeries_iommu.c
4 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
8 * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
10 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/config.h>
29 #include <linux/init.h>
30 #include <linux/types.h>
31 #include <linux/slab.h>
33 #include <linux/spinlock.h>
34 #include <linux/string.h>
35 #include <linux/pci.h>
36 #include <linux/dma-mapping.h>
40 #include <asm/ppcdebug.h>
41 #include <asm/iommu.h>
42 #include <asm/pci-bridge.h>
43 #include <asm/machdep.h>
44 #include <asm/abs_addr.h>
45 #include <asm/plpar_wrappers.h>
46 #include <asm/pSeries_reconfig.h>
47 #include <asm/systemcfg.h>
48 #include <asm/firmware.h>
53 extern int is_python(struct device_node *);
55 static void tce_build_pSeries(struct iommu_table *tbl, long index,
56 long npages, unsigned long uaddr,
57 enum dma_data_direction direction)
63 t.te_rdwr = 1; // Read allowed
65 if (direction != DMA_TO_DEVICE)
68 tp = ((union tce_entry *)tbl->it_base) + index;
71 /* can't move this out since we might cross LMB boundary */
72 t.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT;
74 tp->te_word = t.te_word;
82 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
88 tp = ((union tce_entry *)tbl->it_base) + index;
91 tp->te_word = t.te_word;
98 static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
99 long npages, unsigned long uaddr,
100 enum dma_data_direction direction)
106 tce.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT;
108 if (direction != DMA_TO_DEVICE)
112 rc = plpar_tce_put((u64)tbl->it_index,
116 if (rc && printk_ratelimit()) {
117 printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
118 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
119 printk("\ttcenum = 0x%lx\n", (u64)tcenum);
120 printk("\ttce val = 0x%lx\n", tce.te_word );
121 show_stack(current, (unsigned long *)__get_SP());
129 static DEFINE_PER_CPU(void *, tce_page) = NULL;
131 static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
132 long npages, unsigned long uaddr,
133 enum dma_data_direction direction)
136 union tce_entry tce, *tcep;
140 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
143 tcep = __get_cpu_var(tce_page);
145 /* This is safe to do since interrupts are off when we're called
146 * from iommu_alloc{,_sg}()
149 tcep = (void *)__get_free_page(GFP_ATOMIC);
150 /* If allocation fails, fall back to the loop implementation */
152 return tce_build_pSeriesLP(tbl, tcenum, npages,
154 __get_cpu_var(tce_page) = tcep;
158 tce.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT;
160 if (direction != DMA_TO_DEVICE)
163 /* We can map max one pageful of TCEs at a time */
166 * Set up the page with TCE data, looping through and setting
169 limit = min_t(long, npages, PAGE_SIZE/sizeof(union tce_entry));
171 for (l = 0; l < limit; l++) {
176 rc = plpar_tce_put_indirect((u64)tbl->it_index,
178 (u64)virt_to_abs(tcep),
183 } while (npages > 0 && !rc);
185 if (rc && printk_ratelimit()) {
186 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
187 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
188 printk("\tnpages = 0x%lx\n", (u64)npages);
189 printk("\ttce[0] val = 0x%lx\n", tcep[0].te_word);
190 show_stack(current, (unsigned long *)__get_SP());
194 static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
202 rc = plpar_tce_put((u64)tbl->it_index,
206 if (rc && printk_ratelimit()) {
207 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
208 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
209 printk("\ttcenum = 0x%lx\n", (u64)tcenum);
210 printk("\ttce val = 0x%lx\n", tce.te_word );
211 show_stack(current, (unsigned long *)__get_SP());
219 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
226 rc = plpar_tce_stuff((u64)tbl->it_index,
231 if (rc && printk_ratelimit()) {
232 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
233 printk("\trc = %ld\n", rc);
234 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
235 printk("\tnpages = 0x%lx\n", (u64)npages);
236 printk("\ttce val = 0x%lx\n", tce.te_word );
237 show_stack(current, (unsigned long *)__get_SP());
241 static void iommu_table_setparms(struct pci_controller *phb,
242 struct device_node *dn,
243 struct iommu_table *tbl)
245 struct device_node *node;
246 unsigned long *basep;
249 node = (struct device_node *)phb->arch_data;
251 basep = (unsigned long *)get_property(node, "linux,tce-base", NULL);
252 sizep = (unsigned int *)get_property(node, "linux,tce-size", NULL);
253 if (basep == NULL || sizep == NULL) {
254 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
255 "missing tce entries !\n", dn->full_name);
259 tbl->it_base = (unsigned long)__va(*basep);
260 memset((void *)tbl->it_base, 0, *sizep);
262 tbl->it_busno = phb->bus->number;
264 /* Units of tce entries */
265 tbl->it_offset = phb->dma_window_base_cur >> PAGE_SHIFT;
267 /* Test if we are going over 2GB of DMA space */
268 if (phb->dma_window_base_cur + phb->dma_window_size > (1L << 31))
269 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
271 phb->dma_window_base_cur += phb->dma_window_size;
273 /* Set the tce table size - measured in entries */
274 tbl->it_size = phb->dma_window_size >> PAGE_SHIFT;
277 tbl->it_blocksize = 16;
278 tbl->it_type = TCE_PCI;
282 * iommu_table_setparms_lpar
284 * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
286 * ToDo: properly interpret the ibm,dma-window property. The definition is:
287 * logical-bus-number (1 word)
288 * phys-address (#address-cells words)
289 * size (#cell-size words)
291 * Currently we hard code these sizes (more or less).
293 static void iommu_table_setparms_lpar(struct pci_controller *phb,
294 struct device_node *dn,
295 struct iommu_table *tbl,
296 unsigned int *dma_window)
298 tbl->it_busno = dn->bussubno;
300 /* TODO: Parse field size properties properly. */
301 tbl->it_size = (((unsigned long)dma_window[4] << 32) |
302 (unsigned long)dma_window[5]) >> PAGE_SHIFT;
303 tbl->it_offset = (((unsigned long)dma_window[2] << 32) |
304 (unsigned long)dma_window[3]) >> PAGE_SHIFT;
306 tbl->it_index = dma_window[0];
307 tbl->it_blocksize = 16;
308 tbl->it_type = TCE_PCI;
311 static void iommu_bus_setup_pSeries(struct pci_bus *bus)
313 struct device_node *dn, *pdn;
314 struct iommu_table *tbl;
316 DBG("iommu_bus_setup_pSeries, bus %p, bus->self %p\n", bus, bus->self);
318 /* For each (root) bus, we carve up the available DMA space in 256MB
319 * pieces. Since each piece is used by one (sub) bus/device, that would
320 * give a maximum of 7 devices per PHB. In most cases, this is plenty.
322 * The exception is on Python PHBs (pre-POWER4). Here we don't have EADS
323 * bridges below the PHB to allocate the sectioned tables to, so instead
324 * we allocate a 1GB table at the PHB level.
327 dn = pci_bus_to_OF_node(bus);
332 unsigned int *iohole;
334 DBG("Python root bus %s\n", bus->name);
336 iohole = (unsigned int *)get_property(dn, "io-hole", 0);
339 /* On first bus we need to leave room for the
340 * ISA address space. Just skip the first 256MB
341 * alltogether. This leaves 768MB for the window.
343 DBG("PHB has io-hole, reserving 256MB\n");
344 dn->phb->dma_window_size = 3 << 28;
345 dn->phb->dma_window_base_cur = 1 << 28;
347 /* 1GB window by default */
348 dn->phb->dma_window_size = 1 << 30;
349 dn->phb->dma_window_base_cur = 0;
352 tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL);
354 iommu_table_setparms(dn->phb, dn, tbl);
355 dn->iommu_table = iommu_init_table(tbl);
357 /* Do a 128MB table at root. This is used for the IDE
358 * controller on some SMP-mode POWER4 machines. It
359 * doesn't hurt to allocate it on other machines
360 * -- it'll just be unused since new tables are
361 * allocated on the EADS level.
363 * Allocate at offset 128MB to avoid having to deal
364 * with ISA holes; 128MB table for IDE is plenty.
366 dn->phb->dma_window_size = 1 << 27;
367 dn->phb->dma_window_base_cur = 1 << 27;
369 tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL);
371 iommu_table_setparms(dn->phb, dn, tbl);
372 dn->iommu_table = iommu_init_table(tbl);
374 /* All child buses have 256MB tables */
375 dn->phb->dma_window_size = 1 << 28;
378 pdn = pci_bus_to_OF_node(bus->parent);
380 if (!bus->parent->self && !is_python(pdn)) {
381 struct iommu_table *tbl;
382 /* First child and not python means this is the EADS
383 * level. Allocate new table for this slot with 256MB
387 tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL);
389 iommu_table_setparms(dn->phb, dn, tbl);
391 dn->iommu_table = iommu_init_table(tbl);
393 /* Lower than first child or under python, use parent table */
394 dn->iommu_table = pdn->iommu_table;
400 static void iommu_bus_setup_pSeriesLP(struct pci_bus *bus)
402 struct iommu_table *tbl;
403 struct device_node *dn, *pdn;
404 unsigned int *dma_window = NULL;
406 DBG("iommu_bus_setup_pSeriesLP, bus %p, bus->self %p\n", bus, bus->self);
408 dn = pci_bus_to_OF_node(bus);
410 /* Find nearest ibm,dma-window, walking up the device tree */
411 for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
412 dma_window = (unsigned int *)get_property(pdn, "ibm,dma-window", NULL);
413 if (dma_window != NULL)
417 if (dma_window == NULL) {
418 DBG("iommu_bus_setup_pSeriesLP: bus %s seems to have no ibm,dma-window property\n", dn->full_name);
422 if (!pdn->iommu_table) {
423 /* Bussubno hasn't been copied yet.
424 * Do it now because iommu_table_setparms_lpar needs it.
426 pdn->bussubno = bus->number;
428 tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table),
431 iommu_table_setparms_lpar(pdn->phb, pdn, tbl, dma_window);
433 pdn->iommu_table = iommu_init_table(tbl);
437 dn->iommu_table = pdn->iommu_table;
441 static void iommu_dev_setup_pSeries(struct pci_dev *dev)
443 struct device_node *dn, *mydn;
445 DBG("iommu_dev_setup_pSeries, dev %p (%s)\n", dev, dev->pretty_name);
446 /* Now copy the iommu_table ptr from the bus device down to the
447 * pci device_node. This means get_iommu_table() won't need to search
448 * up the device tree to find it.
450 mydn = dn = pci_device_to_OF_node(dev);
452 while (dn && dn->iommu_table == NULL)
456 mydn->iommu_table = dn->iommu_table;
458 DBG("iommu_dev_setup_pSeries, dev %p (%s) has no iommu table\n", dev, dev->pretty_name);
462 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
465 struct device_node *np = node;
468 case PSERIES_RECONFIG_REMOVE:
469 if (np->iommu_table &&
470 get_property(np, "ibm,dma-window", NULL))
471 iommu_free_table(np);
480 static struct notifier_block iommu_reconfig_nb = {
481 .notifier_call = iommu_reconfig_notifier,
484 static void iommu_dev_setup_pSeriesLP(struct pci_dev *dev)
486 struct device_node *pdn, *dn;
487 struct iommu_table *tbl;
488 int *dma_window = NULL;
490 DBG("iommu_dev_setup_pSeriesLP, dev %p (%s)\n", dev, dev->pretty_name);
492 /* dev setup for LPAR is a little tricky, since the device tree might
493 * contain the dma-window properties per-device and not neccesarily
494 * for the bus. So we need to search upwards in the tree until we
495 * either hit a dma-window property, OR find a parent with a table
498 dn = pci_device_to_OF_node(dev);
500 for (pdn = dn; pdn && !pdn->iommu_table; pdn = pdn->parent) {
501 dma_window = (unsigned int *)get_property(pdn, "ibm,dma-window", NULL);
506 /* Check for parent == NULL so we don't try to setup the empty EADS
507 * slots on POWER4 machines.
509 if (dma_window == NULL || pdn->parent == NULL) {
510 /* Fall back to regular (non-LPAR) dev setup */
511 DBG("No dma window for device, falling back to regular setup\n");
512 iommu_dev_setup_pSeries(dev);
515 DBG("Found DMA window, allocating table\n");
518 if (!pdn->iommu_table) {
519 /* iommu_table_setparms_lpar needs bussubno. */
520 pdn->bussubno = pdn->phb->bus->number;
522 tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table),
525 iommu_table_setparms_lpar(pdn->phb, pdn, tbl, dma_window);
527 pdn->iommu_table = iommu_init_table(tbl);
531 dn->iommu_table = pdn->iommu_table;
534 static void iommu_bus_setup_null(struct pci_bus *b) { }
535 static void iommu_dev_setup_null(struct pci_dev *d) { }
537 /* These are called very early. */
538 void iommu_init_early_pSeries(void)
540 if (of_chosen && get_property(of_chosen, "linux,iommu-off", NULL)) {
541 /* Direct I/O, IOMMU off */
542 ppc_md.iommu_dev_setup = iommu_dev_setup_null;
543 ppc_md.iommu_bus_setup = iommu_bus_setup_null;
544 pci_direct_iommu_init();
549 if (systemcfg->platform & PLATFORM_LPAR) {
550 if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
551 ppc_md.tce_build = tce_buildmulti_pSeriesLP;
552 ppc_md.tce_free = tce_freemulti_pSeriesLP;
554 ppc_md.tce_build = tce_build_pSeriesLP;
555 ppc_md.tce_free = tce_free_pSeriesLP;
557 ppc_md.iommu_bus_setup = iommu_bus_setup_pSeriesLP;
558 ppc_md.iommu_dev_setup = iommu_dev_setup_pSeriesLP;
560 ppc_md.tce_build = tce_build_pSeries;
561 ppc_md.tce_free = tce_free_pSeries;
562 ppc_md.iommu_bus_setup = iommu_bus_setup_pSeries;
563 ppc_md.iommu_dev_setup = iommu_dev_setup_pSeries;
567 pSeries_reconfig_notifier_register(&iommu_reconfig_nb);