2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
23 #include <linux/list.h>
24 #include <linux/syscalls.h>
26 #include <asm/processor.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/byteorder.h>
32 #include <asm/machdep.h>
34 #include <asm/ppc-pci.h>
37 #define DBG(fmt...) udbg_printf(fmt)
42 unsigned long pci_probe_only = 1;
43 unsigned long pci_assign_all_buses = 0;
46 * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
47 * devices we don't have access to.
49 unsigned long io_page_mask;
51 EXPORT_SYMBOL(io_page_mask);
53 #ifdef CONFIG_PPC_MULTIPLATFORM
54 static void fixup_resource(struct resource *res, struct pci_dev *dev);
55 static void do_bus_setup(struct pci_bus *bus);
58 unsigned int pcibios_assign_all_busses(void)
60 return pci_assign_all_buses;
63 /* pci_io_base -- the base address from which io bars are offsets.
64 * This is the lowest I/O base address (so bar values are always positive),
65 * and it *must* be the start of ISA space if an ISA bus exists because
66 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
67 * page is mapped and isa_io_limit prevents access to it.
69 unsigned long isa_io_base; /* NULL if no ISA bus */
70 EXPORT_SYMBOL(isa_io_base);
71 unsigned long pci_io_base;
72 EXPORT_SYMBOL(pci_io_base);
74 void iSeries_pcibios_init(void);
78 struct dma_mapping_ops pci_dma_ops;
79 EXPORT_SYMBOL(pci_dma_ops);
81 int global_phb_number; /* Global phb counter */
83 /* Cached ISA bridge dev. */
84 struct pci_dev *ppc64_isabridge_dev = NULL;
86 static void fixup_broken_pcnet32(struct pci_dev* dev)
88 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
89 dev->vendor = PCI_VENDOR_ID_AMD;
90 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
93 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
95 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
98 unsigned long offset = 0;
99 struct pci_controller *hose = pci_bus_to_host(dev->bus);
104 if (res->flags & IORESOURCE_IO)
105 offset = (unsigned long)hose->io_base_virt - pci_io_base;
107 if (res->flags & IORESOURCE_MEM)
108 offset = hose->pci_mem_offset;
110 region->start = res->start - offset;
111 region->end = res->end - offset;
114 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
115 struct pci_bus_region *region)
117 unsigned long offset = 0;
118 struct pci_controller *hose = pci_bus_to_host(dev->bus);
123 if (res->flags & IORESOURCE_IO)
124 offset = (unsigned long)hose->io_base_virt - pci_io_base;
126 if (res->flags & IORESOURCE_MEM)
127 offset = hose->pci_mem_offset;
129 res->start = region->start + offset;
130 res->end = region->end + offset;
133 #ifdef CONFIG_HOTPLUG
134 EXPORT_SYMBOL(pcibios_resource_to_bus);
135 EXPORT_SYMBOL(pcibios_bus_to_resource);
139 * We need to avoid collisions with `mirrored' VGA ports
140 * and other strange ISA hardware, so we always want the
141 * addresses to be allocated in the 0x000-0x0ff region
144 * Why? Because some silly external IO cards only decode
145 * the low 10 bits of the IO address. The 0x00-0xff region
146 * is reserved for motherboard devices that decode all 16
147 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
148 * but we want to try to avoid allocating at 0x2900-0x2bff
149 * which might have be mirrored at 0x0100-0x03ff..
151 void pcibios_align_resource(void *data, struct resource *res,
152 unsigned long size, unsigned long align)
154 struct pci_dev *dev = data;
155 struct pci_controller *hose = pci_bus_to_host(dev->bus);
156 unsigned long start = res->start;
157 unsigned long alignto;
159 if (res->flags & IORESOURCE_IO) {
160 unsigned long offset = (unsigned long)hose->io_base_virt -
162 /* Make sure we start at our min on all hoses */
163 if (start - offset < PCIBIOS_MIN_IO)
164 start = PCIBIOS_MIN_IO + offset;
167 * Put everything into 0x00-0xff region modulo 0x400
170 start = (start + 0x3ff) & ~0x3ff;
172 } else if (res->flags & IORESOURCE_MEM) {
173 /* Make sure we start at our min on all hoses */
174 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
175 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
177 /* Align to multiple of size of minimum base. */
178 alignto = max(0x1000UL, align);
179 start = ALIGN(start, alignto);
185 static DEFINE_SPINLOCK(hose_spinlock);
188 * pci_controller(phb) initialized common variables.
190 void __devinit pci_setup_pci_controller(struct pci_controller *hose)
192 memset(hose, 0, sizeof(struct pci_controller));
194 spin_lock(&hose_spinlock);
195 hose->global_number = global_phb_number++;
196 list_add_tail(&hose->list_node, &hose_list);
197 spin_unlock(&hose_spinlock);
200 static void __init pcibios_claim_one_bus(struct pci_bus *b)
203 struct pci_bus *child_bus;
205 list_for_each_entry(dev, &b->devices, bus_list) {
208 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
209 struct resource *r = &dev->resource[i];
211 if (r->parent || !r->start || !r->flags)
213 pci_claim_resource(dev, i);
217 list_for_each_entry(child_bus, &b->children, node)
218 pcibios_claim_one_bus(child_bus);
221 #ifndef CONFIG_PPC_ISERIES
222 static void __init pcibios_claim_of_setup(void)
226 list_for_each_entry(b, &pci_root_buses, node)
227 pcibios_claim_one_bus(b);
231 #ifdef CONFIG_PPC_MULTIPLATFORM
232 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
237 prop = (u32 *) get_property(np, name, &len);
238 if (prop && len >= 4)
243 static unsigned int pci_parse_of_flags(u32 addr0)
245 unsigned int flags = 0;
247 if (addr0 & 0x02000000) {
248 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
249 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
250 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
251 if (addr0 & 0x40000000)
252 flags |= IORESOURCE_PREFETCH
253 | PCI_BASE_ADDRESS_MEM_PREFETCH;
254 } else if (addr0 & 0x01000000)
255 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
259 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
261 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
265 struct resource *res;
269 addrs = (u32 *) get_property(node, "assigned-addresses", &proplen);
272 for (; proplen >= 20; proplen -= 20, addrs += 5) {
273 flags = pci_parse_of_flags(addrs[0]);
276 base = GET_64BIT(addrs, 1);
277 size = GET_64BIT(addrs, 3);
281 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
282 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
283 } else if (i == dev->rom_base_reg) {
284 res = &dev->resource[PCI_ROM_RESOURCE];
285 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
287 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
291 res->end = base + size - 1;
293 res->name = pci_name(dev);
294 fixup_resource(res, dev);
298 struct pci_dev *of_create_pci_dev(struct device_node *node,
299 struct pci_bus *bus, int devfn)
304 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
307 type = get_property(node, "device_type", NULL);
311 memset(dev, 0, sizeof(struct pci_dev));
314 dev->dev.parent = bus->bridge;
315 dev->dev.bus = &pci_bus_type;
317 dev->multifunction = 0; /* maybe a lie? */
319 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
320 dev->device = get_int_prop(node, "device-id", 0xffff);
321 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
322 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
324 dev->cfg_size = 256; /*pci_cfg_space_size(dev);*/
326 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
327 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
328 dev->class = get_int_prop(node, "class-code", 0);
330 dev->current_state = 4; /* unknown power state */
332 if (!strcmp(type, "pci")) {
333 /* a PCI-PCI bridge */
334 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
335 dev->rom_base_reg = PCI_ROM_ADDRESS1;
336 } else if (!strcmp(type, "cardbus")) {
337 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
339 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
340 dev->rom_base_reg = PCI_ROM_ADDRESS;
342 if (node->n_intrs > 0) {
343 dev->irq = node->intrs[0].line;
344 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
349 pci_parse_of_addrs(node, dev);
351 pci_device_add(dev, bus);
353 /* XXX pci_scan_msi_device(dev); */
357 EXPORT_SYMBOL(of_create_pci_dev);
359 void __devinit of_scan_bus(struct device_node *node,
362 struct device_node *child = NULL;
367 while ((child = of_get_next_child(node, child)) != NULL) {
368 reg = (u32 *) get_property(child, "reg", ®len);
369 if (reg == NULL || reglen < 20)
371 devfn = (reg[0] >> 8) & 0xff;
372 /* create a new pci_dev for this device */
373 dev = of_create_pci_dev(child, bus, devfn);
376 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
377 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
378 of_scan_pci_bridge(child, dev);
383 EXPORT_SYMBOL(of_scan_bus);
385 void __devinit of_scan_pci_bridge(struct device_node *node,
389 u32 *busrange, *ranges;
391 struct resource *res;
395 /* parse bus-range property */
396 busrange = (u32 *) get_property(node, "bus-range", &len);
397 if (busrange == NULL || len != 8) {
398 printk(KERN_ERR "Can't get bus-range for PCI-PCI bridge %s\n",
402 ranges = (u32 *) get_property(node, "ranges", &len);
403 if (ranges == NULL) {
404 printk(KERN_ERR "Can't get ranges for PCI-PCI bridge %s\n",
409 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
411 printk(KERN_ERR "Failed to create pci bus for %s\n",
416 bus->primary = dev->bus->number;
417 bus->subordinate = busrange[1];
421 /* parse ranges property */
422 /* PCI #address-cells == 3 and #size-cells == 2 always */
423 res = &dev->resource[PCI_BRIDGE_RESOURCES];
424 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
426 bus->resource[i] = res;
430 for (; len >= 32; len -= 32, ranges += 8) {
431 flags = pci_parse_of_flags(ranges[0]);
432 size = GET_64BIT(ranges, 6);
433 if (flags == 0 || size == 0)
435 if (flags & IORESOURCE_IO) {
436 res = bus->resource[0];
438 printk(KERN_ERR "PCI: ignoring extra I/O range"
439 " for bridge %s\n", node->full_name);
443 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
444 printk(KERN_ERR "PCI: too many memory ranges"
445 " for bridge %s\n", node->full_name);
448 res = bus->resource[i];
451 res->start = GET_64BIT(ranges, 1);
452 res->end = res->start + size - 1;
454 fixup_resource(res, dev);
456 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
459 mode = PCI_PROBE_NORMAL;
460 if (ppc_md.pci_probe_mode)
461 mode = ppc_md.pci_probe_mode(bus);
462 if (mode == PCI_PROBE_DEVTREE)
463 of_scan_bus(node, bus);
464 else if (mode == PCI_PROBE_NORMAL)
465 pci_scan_child_bus(bus);
467 EXPORT_SYMBOL(of_scan_pci_bridge);
468 #endif /* CONFIG_PPC_MULTIPLATFORM */
470 void __devinit scan_phb(struct pci_controller *hose)
473 struct device_node *node = hose->arch_data;
475 struct resource *res;
477 bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node);
479 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
480 hose->global_number);
483 bus->secondary = hose->first_busno;
486 bus->resource[0] = res = &hose->io_resource;
487 if (res->flags && request_resource(&ioport_resource, res))
488 printk(KERN_ERR "Failed to request PCI IO region "
489 "on PCI domain %04x\n", hose->global_number);
491 for (i = 0; i < 3; ++i) {
492 res = &hose->mem_resources[i];
493 bus->resource[i+1] = res;
494 if (res->flags && request_resource(&iomem_resource, res))
495 printk(KERN_ERR "Failed to request PCI memory region "
496 "on PCI domain %04x\n", hose->global_number);
499 mode = PCI_PROBE_NORMAL;
500 #ifdef CONFIG_PPC_MULTIPLATFORM
501 if (ppc_md.pci_probe_mode)
502 mode = ppc_md.pci_probe_mode(bus);
503 if (mode == PCI_PROBE_DEVTREE) {
504 bus->subordinate = hose->last_busno;
505 of_scan_bus(node, bus);
507 #endif /* CONFIG_PPC_MULTIPLATFORM */
508 if (mode == PCI_PROBE_NORMAL)
509 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
510 pci_bus_add_devices(bus);
513 static int __init pcibios_init(void)
515 struct pci_controller *hose, *tmp;
517 /* For now, override phys_mem_access_prot. If we need it,
518 * later, we may move that initialization to each ppc_md
520 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
522 #ifdef CONFIG_PPC_ISERIES
523 iSeries_pcibios_init();
526 printk("PCI: Probing PCI hardware\n");
528 /* Scan all of the recorded PCI controllers. */
529 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
532 #ifndef CONFIG_PPC_ISERIES
534 pcibios_claim_of_setup();
536 /* FIXME: `else' will be removed when
537 pci_assign_unassigned_resources() is able to work
538 correctly with [partially] allocated PCI tree. */
539 pci_assign_unassigned_resources();
540 #endif /* !CONFIG_PPC_ISERIES */
542 /* Call machine dependent final fixup */
543 if (ppc_md.pcibios_fixup)
544 ppc_md.pcibios_fixup();
546 /* Cache the location of the ISA bridge (if we have one) */
547 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
548 if (ppc64_isabridge_dev != NULL)
549 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
551 printk("PCI: Probing PCI hardware done\n");
556 subsys_initcall(pcibios_init);
558 char __init *pcibios_setup(char *str)
563 int pcibios_enable_device(struct pci_dev *dev, int mask)
568 pci_read_config_word(dev, PCI_COMMAND, &cmd);
571 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
572 struct resource *res = &dev->resource[i];
574 /* Only set up the requested stuff */
575 if (!(mask & (1<<i)))
578 if (res->flags & IORESOURCE_IO)
579 cmd |= PCI_COMMAND_IO;
580 if (res->flags & IORESOURCE_MEM)
581 cmd |= PCI_COMMAND_MEMORY;
585 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
587 /* Enable the appropriate bits in the PCI command register. */
588 pci_write_config_word(dev, PCI_COMMAND, cmd);
594 * Return the domain number for this bus.
596 int pci_domain_nr(struct pci_bus *bus)
598 #ifdef CONFIG_PPC_ISERIES
601 struct pci_controller *hose = pci_bus_to_host(bus);
603 return hose->global_number;
607 EXPORT_SYMBOL(pci_domain_nr);
609 /* Decide whether to display the domain number in /proc */
610 int pci_proc_domain(struct pci_bus *bus)
612 #ifdef CONFIG_PPC_ISERIES
615 struct pci_controller *hose = pci_bus_to_host(bus);
621 * Platform support for /proc/bus/pci/X/Y mmap()s,
622 * modelled on the sparc64 implementation by Dave Miller.
627 * Adjust vm_pgoff of VMA such that it is the physical page offset
628 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
630 * Basically, the user finds the base address for his device which he wishes
631 * to mmap. They read the 32-bit value from the config space base register,
632 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
633 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
635 * Returns negative error code on failure, zero on success.
637 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
638 unsigned long *offset,
639 enum pci_mmap_state mmap_state)
641 struct pci_controller *hose = pci_bus_to_host(dev->bus);
642 unsigned long io_offset = 0;
646 return NULL; /* should never happen */
648 /* If memory, add on the PCI bridge address offset */
649 if (mmap_state == pci_mmap_mem) {
650 *offset += hose->pci_mem_offset;
651 res_bit = IORESOURCE_MEM;
653 io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
654 *offset += io_offset;
655 res_bit = IORESOURCE_IO;
659 * Check that the offset requested corresponds to one of the
660 * resources of the device.
662 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
663 struct resource *rp = &dev->resource[i];
664 int flags = rp->flags;
666 /* treat ROM as memory (should be already) */
667 if (i == PCI_ROM_RESOURCE)
668 flags |= IORESOURCE_MEM;
670 /* Active and same type? */
671 if ((flags & res_bit) == 0)
674 /* In the range of this resource? */
675 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
678 /* found it! construct the final physical address */
679 if (mmap_state == pci_mmap_io)
680 *offset += hose->io_base_phys - io_offset;
688 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
691 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
693 enum pci_mmap_state mmap_state,
696 unsigned long prot = pgprot_val(protection);
698 /* Write combine is always 0 on non-memory space mappings. On
699 * memory space, if the user didn't pass 1, we check for a
700 * "prefetchable" resource. This is a bit hackish, but we use
701 * this to workaround the inability of /sysfs to provide a write
704 if (mmap_state != pci_mmap_mem)
706 else if (write_combine == 0) {
707 if (rp->flags & IORESOURCE_PREFETCH)
711 /* XXX would be nice to have a way to ask for write-through */
712 prot |= _PAGE_NO_CACHE;
714 prot &= ~_PAGE_GUARDED;
716 prot |= _PAGE_GUARDED;
718 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
721 return __pgprot(prot);
725 * This one is used by /dev/mem and fbdev who have no clue about the
726 * PCI device, it tries to find the PCI device first and calls the
729 pgprot_t pci_phys_mem_access_prot(struct file *file,
734 struct pci_dev *pdev = NULL;
735 struct resource *found = NULL;
736 unsigned long prot = pgprot_val(protection);
737 unsigned long offset = pfn << PAGE_SHIFT;
740 if (page_is_ram(pfn))
741 return __pgprot(prot);
743 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
745 for_each_pci_dev(pdev) {
746 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
747 struct resource *rp = &pdev->resource[i];
748 int flags = rp->flags;
750 /* Active and same type? */
751 if ((flags & IORESOURCE_MEM) == 0)
753 /* In the range of this resource? */
754 if (offset < (rp->start & PAGE_MASK) ||
764 if (found->flags & IORESOURCE_PREFETCH)
765 prot &= ~_PAGE_GUARDED;
769 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
771 return __pgprot(prot);
776 * Perform the actual remap of the pages for a PCI device mapping, as
777 * appropriate for this architecture. The region in the process to map
778 * is described by vm_start and vm_end members of VMA, the base physical
779 * address is found in vm_pgoff.
780 * The pci device structure is provided so that architectures may make mapping
781 * decisions on a per-device or per-bus basis.
783 * Returns a negative error code on failure, zero on success.
785 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
786 enum pci_mmap_state mmap_state,
789 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
793 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
797 vma->vm_pgoff = offset >> PAGE_SHIFT;
798 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
799 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
801 mmap_state, write_combine);
803 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
804 vma->vm_end - vma->vm_start, vma->vm_page_prot);
809 #ifdef CONFIG_PPC_MULTIPLATFORM
810 static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
812 struct pci_dev *pdev;
813 struct device_node *np;
815 pdev = to_pci_dev (dev);
816 np = pci_device_to_OF_node(pdev);
817 if (np == NULL || np->full_name == NULL)
819 return sprintf(buf, "%s", np->full_name);
821 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
822 #endif /* CONFIG_PPC_MULTIPLATFORM */
824 void pcibios_add_platform_entries(struct pci_dev *pdev)
826 #ifdef CONFIG_PPC_MULTIPLATFORM
827 device_create_file(&pdev->dev, &dev_attr_devspec);
828 #endif /* CONFIG_PPC_MULTIPLATFORM */
831 #ifdef CONFIG_PPC_MULTIPLATFORM
833 #define ISA_SPACE_MASK 0x1
834 #define ISA_SPACE_IO 0x1
836 static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
837 unsigned long phb_io_base_phys,
838 void __iomem * phb_io_base_virt)
840 struct isa_range *range;
841 unsigned long pci_addr;
842 unsigned int isa_addr;
846 range = (struct isa_range *) get_property(isa_node, "ranges", &rlen);
847 if (range == NULL || (rlen < sizeof(struct isa_range))) {
848 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
850 __ioremap_explicit(phb_io_base_phys,
851 (unsigned long)phb_io_base_virt,
852 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
856 /* From "ISA Binding to 1275"
857 * The ranges property is laid out as an array of elements,
858 * each of which comprises:
859 * cells 0 - 1: an ISA address
860 * cells 2 - 4: a PCI address
861 * (size depending on dev->n_addr_cells)
862 * cell 5: the size of the range
864 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
865 isa_addr = range->isa_addr.a_lo;
866 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
867 range->pci_addr.a_lo;
869 /* Assume these are both zero */
870 if ((pci_addr != 0) || (isa_addr != 0)) {
871 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
876 size = PAGE_ALIGN(range->size);
878 __ioremap_explicit(phb_io_base_phys,
879 (unsigned long) phb_io_base_virt,
880 size, _PAGE_NO_CACHE | _PAGE_GUARDED);
884 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
885 struct device_node *dev, int prim)
887 unsigned int *ranges, pci_space;
891 struct resource *res;
892 int np, na = prom_n_addr_cells(dev);
893 unsigned long pci_addr, cpu_phys_addr;
897 /* From "PCI Binding to 1275"
898 * The ranges property is laid out as an array of elements,
899 * each of which comprises:
900 * cells 0 - 2: a PCI address
901 * cells 3 or 3+4: a CPU physical address
902 * (size depending on dev->n_addr_cells)
903 * cells 4+5 or 5+6: the size of the range
906 hose->io_base_phys = 0;
907 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
908 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
910 pci_space = ranges[0];
911 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
913 cpu_phys_addr = ranges[3];
915 cpu_phys_addr = (cpu_phys_addr << 32) | ranges[4];
917 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
922 /* Now consume following elements while they are contiguous */
923 while (rlen >= np * sizeof(unsigned int)) {
924 unsigned long addr, phys;
926 if (ranges[0] != pci_space)
928 addr = ((unsigned long)ranges[1] << 32) | ranges[2];
931 phys = (phys << 32) | ranges[4];
932 if (addr != pci_addr + size ||
933 phys != cpu_phys_addr + size)
936 size += ((unsigned long)ranges[na+3] << 32)
939 rlen -= np * sizeof(unsigned int);
942 switch ((pci_space >> 24) & 0x3) {
943 case 1: /* I/O space */
944 hose->io_base_phys = cpu_phys_addr;
945 hose->pci_io_size = size;
947 res = &hose->io_resource;
948 res->flags = IORESOURCE_IO;
949 res->start = pci_addr;
950 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
951 res->start, res->start + size - 1);
953 case 2: /* memory space */
955 while (memno < 3 && hose->mem_resources[memno].flags)
959 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
961 res = &hose->mem_resources[memno];
962 res->flags = IORESOURCE_MEM;
963 res->start = cpu_phys_addr;
964 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
965 res->start, res->start + size - 1);
970 res->name = dev->full_name;
971 res->end = res->start + size - 1;
979 void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
981 unsigned long size = hose->pci_io_size;
982 unsigned long io_virt_offset;
983 struct resource *res;
984 struct device_node *isa_dn;
986 hose->io_base_virt = reserve_phb_iospace(size);
987 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
988 hose->global_number, hose->io_base_phys,
989 (unsigned long) hose->io_base_virt);
992 pci_io_base = (unsigned long)hose->io_base_virt;
993 isa_dn = of_find_node_by_type(NULL, "isa");
995 isa_io_base = pci_io_base;
996 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
1004 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1005 res = &hose->io_resource;
1006 res->start += io_virt_offset;
1007 res->end += io_virt_offset;
1010 void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
1013 unsigned long size = hose->pci_io_size;
1014 unsigned long io_virt_offset;
1015 struct resource *res;
1017 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
1018 _PAGE_NO_CACHE | _PAGE_GUARDED);
1019 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1020 hose->global_number, hose->io_base_phys,
1021 (unsigned long) hose->io_base_virt);
1024 pci_io_base = (unsigned long)hose->io_base_virt;
1026 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1027 res = &hose->io_resource;
1028 res->start += io_virt_offset;
1029 res->end += io_virt_offset;
1033 static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
1034 unsigned long *start_virt, unsigned long *size)
1036 struct pci_controller *hose = pci_bus_to_host(bus);
1037 struct pci_bus_region region;
1038 struct resource *res;
1041 res = bus->resource[0];
1042 pcibios_resource_to_bus(bus->self, ®ion, res);
1043 *start_phys = hose->io_base_phys + region.start;
1044 *start_virt = (unsigned long) hose->io_base_virt +
1046 if (region.end > region.start)
1047 *size = region.end - region.start + 1;
1049 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1050 __FUNCTION__, region.start, region.end);
1056 res = &hose->io_resource;
1057 *start_phys = hose->io_base_phys;
1058 *start_virt = (unsigned long) hose->io_base_virt;
1059 if (res->end > res->start)
1060 *size = res->end - res->start + 1;
1062 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1063 __FUNCTION__, res->start, res->end);
1071 int unmap_bus_range(struct pci_bus *bus)
1073 unsigned long start_phys;
1074 unsigned long start_virt;
1078 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1082 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1084 if (iounmap_explicit((void __iomem *) start_virt, size))
1089 EXPORT_SYMBOL(unmap_bus_range);
1091 int remap_bus_range(struct pci_bus *bus)
1093 unsigned long start_phys;
1094 unsigned long start_virt;
1098 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1103 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1105 printk("mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
1106 if (__ioremap_explicit(start_phys, start_virt, size,
1107 _PAGE_NO_CACHE | _PAGE_GUARDED))
1112 EXPORT_SYMBOL(remap_bus_range);
1114 void phbs_remap_io(void)
1116 struct pci_controller *hose, *tmp;
1118 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1119 remap_bus_range(hose->bus);
1123 * ppc64 can have multifunction devices that do not respond to function 0.
1124 * In this case we must scan all functions.
1125 * XXX this can go now, we use the OF device tree in all the
1126 * cases that caused problems. -- paulus
1128 int pcibios_scan_all_fns(struct pci_bus *bus, int devfn)
1133 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
1135 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1136 unsigned long start, end, mask, offset;
1138 if (res->flags & IORESOURCE_IO) {
1139 offset = (unsigned long)hose->io_base_virt - pci_io_base;
1141 start = res->start += offset;
1142 end = res->end += offset;
1144 /* Need to allow IO access to pages that are in the
1146 if (start < MAX_ISA_PORT) {
1147 if (end > MAX_ISA_PORT)
1150 start >>= PAGE_SHIFT;
1153 /* get the range of pages for the map */
1154 mask = ((1 << (end+1)) - 1) ^ ((1 << start) - 1);
1155 io_page_mask |= mask;
1157 } else if (res->flags & IORESOURCE_MEM) {
1158 res->start += hose->pci_mem_offset;
1159 res->end += hose->pci_mem_offset;
1163 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
1164 struct pci_bus *bus)
1166 /* Update device resources. */
1169 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1170 if (dev->resource[i].flags)
1171 fixup_resource(&dev->resource[i], dev);
1173 EXPORT_SYMBOL(pcibios_fixup_device_resources);
1175 static void __devinit do_bus_setup(struct pci_bus *bus)
1177 struct pci_dev *dev;
1179 ppc_md.iommu_bus_setup(bus);
1181 list_for_each_entry(dev, &bus->devices, bus_list)
1182 ppc_md.iommu_dev_setup(dev);
1184 if (ppc_md.irq_bus_setup)
1185 ppc_md.irq_bus_setup(bus);
1188 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1190 struct pci_dev *dev = bus->self;
1192 if (dev && pci_probe_only &&
1193 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1194 /* This is a subordinate bridge */
1196 pci_read_bridge_bases(bus);
1197 pcibios_fixup_device_resources(dev, bus);
1202 if (!pci_probe_only)
1205 list_for_each_entry(dev, &bus->devices, bus_list)
1206 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1207 pcibios_fixup_device_resources(dev, bus);
1209 EXPORT_SYMBOL(pcibios_fixup_bus);
1212 * Reads the interrupt pin to determine if interrupt is use by card.
1213 * If the interrupt is used, then gets the interrupt line from the
1214 * openfirmware and sets it in the pci_dev and pci_config line.
1216 int pci_read_irq_line(struct pci_dev *pci_dev)
1219 struct device_node *node;
1221 pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin);
1225 node = pci_device_to_OF_node(pci_dev);
1229 if (node->n_intrs == 0)
1232 pci_dev->irq = node->intrs[0].line;
1234 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq);
1238 EXPORT_SYMBOL(pci_read_irq_line);
1240 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1241 const struct resource *rsrc,
1242 u64 *start, u64 *end)
1244 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1245 unsigned long offset = 0;
1250 if (rsrc->flags & IORESOURCE_IO)
1251 offset = pci_io_base - (unsigned long)hose->io_base_virt +
1254 *start = rsrc->start + offset;
1255 *end = rsrc->end + offset;
1258 #endif /* CONFIG_PPC_MULTIPLATFORM */
1261 #define IOBASE_BRIDGE_NUMBER 0
1262 #define IOBASE_MEMORY 1
1264 #define IOBASE_ISA_IO 3
1265 #define IOBASE_ISA_MEM 4
1267 long sys_pciconfig_iobase(long which, unsigned long in_bus,
1268 unsigned long in_devfn)
1270 struct pci_controller* hose;
1271 struct list_head *ln;
1272 struct pci_bus *bus = NULL;
1273 struct device_node *hose_node;
1275 /* Argh ! Please forgive me for that hack, but that's the
1276 * simplest way to get existing XFree to not lockup on some
1277 * G5 machines... So when something asks for bus 0 io base
1278 * (bus 0 is HT root), we return the AGP one instead.
1280 #ifdef CONFIG_PPC_PMAC
1281 if (systemcfg->platform == PLATFORM_POWERMAC &&
1282 machine_is_compatible("MacRISC4"))
1285 #endif /* CONFIG_PPC_PMAC */
1287 /* That syscall isn't quite compatible with PCI domains, but it's
1288 * used on pre-domains setup. We return the first match
1291 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
1292 bus = pci_bus_b(ln);
1293 if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate))
1297 if (bus == NULL || bus->sysdata == NULL)
1300 hose_node = (struct device_node *)bus->sysdata;
1301 hose = PCI_DN(hose_node)->phb;
1304 case IOBASE_BRIDGE_NUMBER:
1305 return (long)hose->first_busno;
1307 return (long)hose->pci_mem_offset;
1309 return (long)hose->io_base_phys;
1311 return (long)isa_io_base;
1312 case IOBASE_ISA_MEM: