2 * Copyright IBM Corp. 1999, 2009
4 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
10 #include <linux/kernel.h>
11 #include <linux/errno.h>
12 #include <asm/types.h>
13 #include <asm/ptrace.h>
14 #include <asm/setup.h>
15 #include <asm/processor.h>
16 #include <asm/lowcore.h>
22 extern struct task_struct *__switch_to(void *, void *);
24 static inline void save_fp_regs(s390_fp_regs *fpregs)
28 " std 2,%O0+24(%R0)\n"
29 " std 4,%O0+40(%R0)\n"
31 : "=Q" (*fpregs) : "Q" (*fpregs));
32 if (!MACHINE_HAS_IEEE)
36 " std 1,%O0+16(%R0)\n"
37 " std 3,%O0+32(%R0)\n"
38 " std 5,%O0+48(%R0)\n"
39 " std 7,%O0+64(%R0)\n"
40 " std 8,%O0+72(%R0)\n"
41 " std 9,%O0+80(%R0)\n"
42 " std 10,%O0+88(%R0)\n"
43 " std 11,%O0+96(%R0)\n"
44 " std 12,%O0+104(%R0)\n"
45 " std 13,%O0+112(%R0)\n"
46 " std 14,%O0+120(%R0)\n"
47 " std 15,%O0+128(%R0)\n"
48 : "=Q" (*fpregs) : "Q" (*fpregs));
51 static inline void restore_fp_regs(s390_fp_regs *fpregs)
59 if (!MACHINE_HAS_IEEE)
69 " ld 10,%O0+88(%R0)\n"
70 " ld 11,%O0+96(%R0)\n"
71 " ld 12,%O0+104(%R0)\n"
72 " ld 13,%O0+112(%R0)\n"
73 " ld 14,%O0+120(%R0)\n"
74 " ld 15,%O0+128(%R0)\n"
78 static inline void save_access_regs(unsigned int *acrs)
80 asm volatile("stam 0,15,%0" : "=Q" (*acrs));
83 static inline void restore_access_regs(unsigned int *acrs)
85 asm volatile("lam 0,15,%0" : : "Q" (*acrs));
88 #define switch_to(prev,next,last) do { \
91 save_fp_regs(&prev->thread.fp_regs); \
92 restore_fp_regs(&next->thread.fp_regs); \
93 save_access_regs(&prev->thread.acrs[0]); \
94 restore_access_regs(&next->thread.acrs[0]); \
95 prev = __switch_to(prev,next); \
98 extern void account_vtime(struct task_struct *, struct task_struct *);
99 extern void account_tick_vtime(struct task_struct *);
102 extern void pfault_irq_init(void);
103 extern int pfault_init(void);
104 extern void pfault_fini(void);
105 #else /* CONFIG_PFAULT */
106 #define pfault_irq_init() do { } while (0)
107 #define pfault_init() ({-1;})
108 #define pfault_fini() do { } while (0)
109 #endif /* CONFIG_PFAULT */
111 extern void cmma_init(void);
112 extern int memcpy_real(void *, void *, size_t);
114 #define finish_arch_switch(prev) do { \
115 set_fs(current->thread.mm_segment); \
116 account_vtime(prev, current); \
119 #define nop() asm volatile("nop")
121 #define xchg(ptr,x) \
123 __typeof__(*(ptr)) __ret; \
124 __ret = (__typeof__(*(ptr))) \
125 __xchg((unsigned long)(x), (void *)(ptr),sizeof(*(ptr))); \
129 extern void __xchg_called_with_bad_pointer(void);
131 static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
133 unsigned long addr, old;
138 addr = (unsigned long) ptr;
139 shift = (3 ^ (addr & 3)) << 3;
148 : "=&d" (old), "=Q" (*(int *) addr)
149 : "d" (x << shift), "d" (~(255 << shift)),
150 "Q" (*(int *) addr) : "memory", "cc", "0");
153 addr = (unsigned long) ptr;
154 shift = (2 ^ (addr & 2)) << 3;
163 : "=&d" (old), "=Q" (*(int *) addr)
164 : "d" (x << shift), "d" (~(65535 << shift)),
165 "Q" (*(int *) addr) : "memory", "cc", "0");
172 : "=&d" (old), "=Q" (*(int *) ptr)
173 : "d" (x), "Q" (*(int *) ptr)
182 : "=&d" (old), "=m" (*(long *) ptr)
183 : "d" (x), "Q" (*(long *) ptr)
186 #endif /* __s390x__ */
188 __xchg_called_with_bad_pointer();
193 * Atomic compare and exchange. Compare OLD with MEM, if identical,
194 * store NEW in MEM. Return the initial value in MEM. Success is
195 * indicated by comparing RETURN with OLD.
198 #define __HAVE_ARCH_CMPXCHG 1
200 #define cmpxchg(ptr, o, n) \
201 ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
202 (unsigned long)(n), sizeof(*(ptr))))
204 extern void __cmpxchg_called_with_bad_pointer(void);
206 static inline unsigned long
207 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
209 unsigned long addr, prev, tmp;
214 addr = (unsigned long) ptr;
215 shift = (3 ^ (addr & 3)) << 3;
229 : "=&d" (prev), "=&d" (tmp), "=Q" (*(int *) ptr)
230 : "d" (old << shift), "d" (new << shift),
231 "d" (~(255 << shift)), "Q" (*(int *) ptr)
233 return prev >> shift;
235 addr = (unsigned long) ptr;
236 shift = (2 ^ (addr & 2)) << 3;
250 : "=&d" (prev), "=&d" (tmp), "=Q" (*(int *) ptr)
251 : "d" (old << shift), "d" (new << shift),
252 "d" (~(65535 << shift)), "Q" (*(int *) ptr)
254 return prev >> shift;
258 : "=&d" (prev), "=Q" (*(int *) ptr)
259 : "0" (old), "d" (new), "Q" (*(int *) ptr)
266 : "=&d" (prev), "=Q" (*(long *) ptr)
267 : "0" (old), "d" (new), "Q" (*(long *) ptr)
270 #endif /* __s390x__ */
272 __cmpxchg_called_with_bad_pointer();
277 * Force strict CPU ordering.
278 * And yes, this is required on UP too when we're talking
281 * This is very similar to the ppc eieio/sync instruction in that is
282 * does a checkpoint syncronisation & makes sure that
283 * all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ).
286 #define eieio() asm volatile("bcr 15,0" : : : "memory")
287 #define SYNC_OTHER_CORES(x) eieio()
289 #define rmb() eieio()
290 #define wmb() eieio()
291 #define read_barrier_depends() do { } while(0)
292 #define smp_mb() mb()
293 #define smp_rmb() rmb()
294 #define smp_wmb() wmb()
295 #define smp_read_barrier_depends() read_barrier_depends()
296 #define smp_mb__before_clear_bit() smp_mb()
297 #define smp_mb__after_clear_bit() smp_mb()
300 #define set_mb(var, value) do { var = value; mb(); } while (0)
304 #define __ctl_load(array, low, high) ({ \
305 typedef struct { char _[sizeof(array)]; } addrtype; \
307 " lctlg %1,%2,%0\n" \
308 : : "Q" (*(addrtype *)(&array)), \
309 "i" (low), "i" (high)); \
312 #define __ctl_store(array, low, high) ({ \
313 typedef struct { char _[sizeof(array)]; } addrtype; \
315 " stctg %1,%2,%0\n" \
316 : "=Q" (*(addrtype *)(&array)) \
317 : "i" (low), "i" (high)); \
320 #else /* __s390x__ */
322 #define __ctl_load(array, low, high) ({ \
323 typedef struct { char _[sizeof(array)]; } addrtype; \
326 : : "Q" (*(addrtype *)(&array)), \
327 "i" (low), "i" (high)); \
330 #define __ctl_store(array, low, high) ({ \
331 typedef struct { char _[sizeof(array)]; } addrtype; \
333 " stctl %1,%2,%0\n" \
334 : "=Q" (*(addrtype *)(&array)) \
335 : "i" (low), "i" (high)); \
338 #endif /* __s390x__ */
340 #define __ctl_set_bit(cr, bit) ({ \
341 unsigned long __dummy; \
342 __ctl_store(__dummy, cr, cr); \
343 __dummy |= 1UL << (bit); \
344 __ctl_load(__dummy, cr, cr); \
347 #define __ctl_clear_bit(cr, bit) ({ \
348 unsigned long __dummy; \
349 __ctl_store(__dummy, cr, cr); \
350 __dummy &= ~(1UL << (bit)); \
351 __ctl_load(__dummy, cr, cr); \
354 #include <linux/irqflags.h>
356 #include <asm-generic/cmpxchg-local.h>
358 static inline unsigned long __cmpxchg_local(volatile void *ptr,
360 unsigned long new, int size)
369 return __cmpxchg(ptr, old, new, size);
371 return __cmpxchg_local_generic(ptr, old, new, size);
378 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
381 #define cmpxchg_local(ptr, o, n) \
382 ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
383 (unsigned long)(n), sizeof(*(ptr))))
385 #define cmpxchg64_local(ptr, o, n) \
387 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
388 cmpxchg_local((ptr), (o), (n)); \
391 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
395 * Use to set psw mask except for the first byte which
396 * won't be changed by this function.
399 __set_psw_mask(unsigned long mask)
401 __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
404 #define local_mcck_enable() __set_psw_mask(psw_kernel_bits)
405 #define local_mcck_disable() __set_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK)
409 extern void smp_ctl_set_bit(int cr, int bit);
410 extern void smp_ctl_clear_bit(int cr, int bit);
411 #define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
412 #define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
416 #define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
417 #define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
419 #endif /* CONFIG_SMP */
421 static inline unsigned int stfl(void)
424 " .insn s,0xb2b10000,0(0)\n" /* stfl */
427 return S390_lowcore.stfl_fac_list;
430 static inline int __stfle(unsigned long long *list, int doublewords)
432 typedef struct { unsigned long long _[doublewords]; } addrtype;
433 register unsigned long __nr asm("0") = doublewords - 1;
435 asm volatile(".insn s,0xb2b00000,%0" /* stfle */
436 : "=m" (*(addrtype *) list), "+d" (__nr) : : "cc");
440 static inline int stfle(unsigned long long *list, int doublewords)
442 if (!(stfl() & (1UL << 24)))
444 return __stfle(list, doublewords);
447 static inline unsigned short stap(void)
449 unsigned short cpu_address;
451 asm volatile("stap %0" : "=m" (cpu_address));
455 extern void (*_machine_restart)(char *command);
456 extern void (*_machine_halt)(void);
457 extern void (*_machine_power_off)(void);
459 #define arch_align_stack(x) (x)
461 static inline int tprot(unsigned long addr)
471 : "+d" (rc) : "a" (addr) : "cc");
475 #endif /* __KERNEL__ */