2 * arch/s390/kernel/entry64.S
3 * S390 low-level entry points.
5 * Copyright (C) IBM Corp. 1999,2010
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
12 #include <linux/linkage.h>
13 #include <linux/init.h>
14 #include <asm/cache.h>
15 #include <asm/errno.h>
16 #include <asm/ptrace.h>
17 #include <asm/thread_info.h>
18 #include <asm/asm-offsets.h>
19 #include <asm/unistd.h>
23 * Stack layout for the system_call stack entry.
24 * The first few entries are identical to the user_regs_struct.
26 SP_PTREGS = STACK_FRAME_OVERHEAD
27 SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS
28 SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW
29 SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS
30 SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8
31 SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16
32 SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24
33 SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32
34 SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40
35 SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48
36 SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56
37 SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 64
38 SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 72
39 SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 80
40 SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 88
41 SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 96
42 SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 104
43 SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112
44 SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120
45 SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2
46 SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC
47 SP_SVCNR = STACK_FRAME_OVERHEAD + __PT_SVCNR
48 SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE
50 STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
51 STACK_SIZE = 1 << STACK_SHIFT
53 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
54 _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
55 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
57 _TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | \
58 _TIF_SECCOMP>>8 | _TIF_SYSCALL_TRACEPOINT>>8)
60 #define BASED(name) name-system_call(%r13)
62 .macro HANDLE_SIE_INTERCEPT
63 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
72 #ifdef CONFIG_TRACE_IRQFLAGS
75 brasl %r14,trace_hardirqs_on_caller
80 brasl %r14,trace_hardirqs_off_caller
83 .macro TRACE_IRQS_CHECK_ON
84 tm SP_PSW(%r15),0x03 # irqs enabled?
90 .macro TRACE_IRQS_CHECK_OFF
91 tm SP_PSW(%r15),0x03 # irqs enabled?
98 #define TRACE_IRQS_OFF
99 #define TRACE_IRQS_CHECK_ON
100 #define TRACE_IRQS_CHECK_OFF
103 #ifdef CONFIG_LOCKDEP
104 .macro LOCKDEP_SYS_EXIT
105 tm SP_PSW+1(%r15),0x01 # returning to user ?
107 brasl %r14,lockdep_sys_exit
111 #define LOCKDEP_SYS_EXIT
114 .macro UPDATE_VTIME lc_from,lc_to,lc_sum
122 * Register usage in interrupt handlers:
123 * R9 - pointer to current task structure
124 * R13 - pointer to literal pool
125 * R14 - return register for function calls
126 * R15 - kernel stack pointer
129 .macro SAVE_ALL_SVC psworg,savearea
130 stmg %r11,%r15,\savearea
131 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
132 aghi %r15,-SP_SIZE # make room for registers & psw
133 lg %r11,__LC_LAST_BREAK
136 .macro SAVE_ALL_PGM psworg,savearea
137 stmg %r11,%r15,\savearea
138 tm \psworg+1,0x01 # test problem state bit
139 #ifdef CONFIG_CHECK_STACK
141 tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
148 1: lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
149 2: aghi %r15,-SP_SIZE # make room for registers & psw
150 larl %r13,system_call
151 lg %r11,__LC_LAST_BREAK
154 .macro SAVE_ALL_ASYNC psworg,savearea
155 stmg %r11,%r15,\savearea
156 larl %r13,system_call
157 lg %r11,__LC_LAST_BREAK
159 tm \psworg+1,0x01 # test problem state bit
160 jnz 1f # from user -> load kernel stack
161 clc \psworg+8(8),BASED(.Lcritical_end)
163 clc \psworg+8(8),BASED(.Lcritical_start)
165 brasl %r14,cleanup_critical
166 tm 1(%r12),0x01 # retest problem state after cleanup
168 0: lg %r14,__LC_ASYNC_STACK # are we already on the async. stack ?
170 srag %r14,%r14,STACK_SHIFT
171 #ifdef CONFIG_CHECK_STACK
173 tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
179 1: lg %r15,__LC_ASYNC_STACK # load async stack
180 2: aghi %r15,-SP_SIZE # make room for registers & psw
183 .macro CREATE_STACK_FRAME savearea
184 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
185 stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
186 mvc SP_R11(40,%r15),\savearea # move %r11-%r15 to stack
187 stmg %r0,%r10,SP_R0(%r15) # store gprs %r0-%r10 to kernel stack
190 .macro RESTORE_ALL psworg,sync
191 mvc \psworg(16),SP_PSW(%r15) # move user PSW to lowcore
193 ni \psworg+1,0xfd # clear wait state bit
195 lg %r14,__LC_VDSO_PER_CPU
196 lmg %r0,%r13,SP_R0(%r15) # load gprs 0-13 of user
198 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
199 lmg %r14,%r15,SP_R14(%r15) # load grps 14-15 of user
200 lpswe \psworg # back to caller
206 stg %r11,__TI_last_break(%r12)
211 * Scheduler resume function, called by switch_to
212 * gpr2 = (task_struct *) prev
213 * gpr3 = (task_struct *) next
219 tm __THREAD_per+4(%r3),0xe8 # is the new process using per ?
220 jz __switch_to_noper # if not we're fine
221 stctg %c9,%c11,__SF_EMPTY(%r15)# We are using per stuff
222 clc __THREAD_per(24,%r3),__SF_EMPTY(%r15)
223 je __switch_to_noper # we got away without bashing TLB's
224 lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't
226 lg %r4,__THREAD_info(%r2) # get thread_info of prev
227 tm __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending?
228 jz __switch_to_no_mcck
229 ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
230 lg %r4,__THREAD_info(%r3) # get thread_info of next
231 oi __TI_flags+7(%r4),_TIF_MCCK_PENDING # set it in next
233 stmg %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task
234 stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp
235 lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp
236 lmg %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task
237 stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct
238 lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
239 lg %r3,__THREAD_info(%r3) # load thread_info from task struct
240 stg %r3,__LC_THREAD_INFO
242 stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack
247 * SVC interrupt handler routine. System calls are synchronous events and
248 * are executed with interrupts enabled.
253 stpt __LC_SYNC_ENTER_TIMER
255 SAVE_ALL_SVC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
256 CREATE_STACK_FRAME __LC_SAVE_AREA
257 mvc SP_PSW(16,%r15),__LC_SVC_OLD_PSW
258 mvc SP_ILC(4,%r15),__LC_SVC_ILC
259 stg %r7,SP_ARGS(%r15)
260 lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct
262 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
264 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
266 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
269 llgh %r7,SP_SVCNR(%r15)
270 slag %r7,%r7,2 # shift and test for svc 0
272 # svc 0: system call number in %r1
273 llgfr %r1,%r1 # clear high word in r1
276 sth %r1,SP_SVCNR(%r15)
277 slag %r7,%r1,2 # shift and test for svc 0
279 larl %r10,sys_call_table
281 tm __TI_flags+5(%r12),(_TIF_31BIT>>16) # running in 31 bit mode ?
283 larl %r10,sys_call_table_emu # use 31 bit emulation system calls
286 tm __TI_flags+6(%r12),_TIF_SYSCALL
287 lgf %r8,0(%r7,%r10) # load address of system call routine
289 basr %r14,%r8 # call sys_xxxx
290 stg %r2,SP_R2(%r15) # store return value (change R2 on stack)
295 tm __TI_flags+7(%r12),_TIF_WORK_SVC
296 jnz sysc_work # there is work to do (signals etc.)
298 RESTORE_ALL __LC_RETURN_PSW,1
302 # There is work to do, but first we need to check if we return to userspace.
305 tm SP_PSW+1(%r15),0x01 # returning to user ?
309 # One of the work bits is on. Find out which one.
312 tm __TI_flags+7(%r12),_TIF_MCCK_PENDING
314 tm __TI_flags+7(%r12),_TIF_NEED_RESCHED
316 tm __TI_flags+7(%r12),_TIF_SIGPENDING
318 tm __TI_flags+7(%r12),_TIF_NOTIFY_RESUME
319 jo sysc_notify_resume
320 tm __TI_flags+7(%r12),_TIF_RESTART_SVC
322 tm __TI_flags+7(%r12),_TIF_SINGLE_STEP
324 j sysc_return # beware of critical section cleanup
327 # _TIF_NEED_RESCHED is set, call schedule
330 larl %r14,sysc_return
331 jg schedule # return point is sysc_return
334 # _TIF_MCCK_PENDING is set, call handler
337 larl %r14,sysc_return
338 jg s390_handle_mcck # TIF bit will be cleared by handler
341 # _TIF_SIGPENDING is set, call do_signal
344 ni __TI_flags+7(%r12),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
345 la %r2,SP_PTREGS(%r15) # load pt_regs
346 brasl %r14,do_signal # call do_signal
347 tm __TI_flags+7(%r12),_TIF_RESTART_SVC
349 tm __TI_flags+7(%r12),_TIF_SINGLE_STEP
354 # _TIF_NOTIFY_RESUME is set, call do_notify_resume
357 la %r2,SP_PTREGS(%r15) # load pt_regs
358 larl %r14,sysc_return
359 jg do_notify_resume # call do_notify_resume
362 # _TIF_RESTART_SVC is set, set up registers and restart svc
365 ni __TI_flags+7(%r12),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC
366 lg %r7,SP_R2(%r15) # load new svc number
367 mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument
368 lmg %r2,%r6,SP_R2(%r15) # load svc arguments
369 sth %r7,SP_SVCNR(%r15)
371 j sysc_nr_ok # restart svc
374 # _TIF_SINGLE_STEP is set, call do_single_step
377 ni __TI_flags+7(%r12),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
378 xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number
379 la %r2,SP_PTREGS(%r15) # address of register-save area
380 larl %r14,sysc_return # load adr. of system return
381 jg do_single_step # branch to do_sigtrap
384 # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
385 # and after the system call
388 la %r2,SP_PTREGS(%r15) # load pt_regs
390 llgh %r0,SP_SVCNR(%r15)
392 brasl %r14,do_syscall_trace_enter
396 sllg %r7,%r2,2 # svc number *4
399 lmg %r3,%r6,SP_R3(%r15)
400 lg %r2,SP_ORIG_R2(%r15)
401 basr %r14,%r8 # call sys_xxx
402 stg %r2,SP_R2(%r15) # store return value
404 tm __TI_flags+6(%r12),_TIF_SYSCALL
406 la %r2,SP_PTREGS(%r15) # load pt_regs
407 larl %r14,sysc_return # return point is sysc_return
408 jg do_syscall_trace_exit
411 # a new process exits the kernel with ret_from_fork
415 lg %r13,__LC_SVC_NEW_PSW+8
416 lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct
417 tm SP_PSW+1(%r15),0x01 # forking a kernel thread ?
419 stg %r15,SP_R15(%r15) # store stack pointer for new kthread
420 0: brasl %r14,schedule_tail
422 stosm 24(%r15),0x03 # reenable interrupts
426 # kernel_execve function needs to deal with pt_regs that is not
431 stmg %r12,%r15,96(%r15)
434 stg %r14,__SF_BACKCHAIN(%r15)
435 la %r12,SP_PTREGS(%r15)
436 xc 0(__PT_SIZE,%r12),0(%r12)
442 lmg %r12,%r15,96(%r15)
445 0: stnsm __SF_EMPTY(%r15),0xfc # disable interrupts
447 lg %r15,__LC_KERNEL_STACK # load ksp
448 aghi %r15,-SP_SIZE # make room for registers & psw
449 lg %r13,__LC_SVC_NEW_PSW+8
450 mvc SP_PTREGS(__PT_SIZE,%r15),0(%r12) # copy pt_regs
451 lg %r12,__LC_THREAD_INFO
452 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
454 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
455 brasl %r14,execve_tail
459 * Program check handler routine
462 .globl pgm_check_handler
465 * First we need to check for a special case:
466 * Single stepping an instruction that disables the PER event mask will
467 * cause a PER event AFTER the mask has been set. Example: SVC or LPSW.
468 * For a single stepped SVC the program check handler gets control after
469 * the SVC new PSW has been loaded. But we want to execute the SVC first and
470 * then handle the PER event. Therefore we update the SVC old PSW to point
471 * to the pgm_check_handler and branch to the SVC handler after we checked
472 * if we have to load the kernel stack register.
473 * For every other possible cause for PER event without the PER mask set
474 * we just ignore the PER event (FIXME: is there anything we have to do
477 stpt __LC_SYNC_ENTER_TIMER
478 tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
479 jnz pgm_per # got per exception -> special case
480 SAVE_ALL_PGM __LC_PGM_OLD_PSW,__LC_SAVE_AREA
481 CREATE_STACK_FRAME __LC_SAVE_AREA
482 xc SP_ILC(4,%r15),SP_ILC(%r15)
483 mvc SP_PSW(16,%r15),__LC_PGM_OLD_PSW
484 lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct
485 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
487 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
488 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
489 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
494 stg %r11,SP_ARGS(%r15)
495 lgf %r3,__LC_PGM_ILC # load program interruption code
500 larl %r1,pgm_check_table
501 lg %r1,0(%r8,%r1) # load address of handler routine
502 la %r2,SP_PTREGS(%r15) # address of register-save area
503 basr %r14,%r1 # branch to interrupt-handler
509 # handle per exception
512 tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on
513 jnz pgm_per_std # ok, normal per event from user space
514 # ok its one of the special cases, now we need to find out which one
515 clc __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW
517 # no interesting special case, ignore PER event
518 lpswe __LC_PGM_OLD_PSW
521 # Normal per exception
524 SAVE_ALL_PGM __LC_PGM_OLD_PSW,__LC_SAVE_AREA
525 CREATE_STACK_FRAME __LC_SAVE_AREA
526 mvc SP_PSW(16,%r15),__LC_PGM_OLD_PSW
527 lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct
528 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
530 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
531 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
532 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
537 lg %r1,__TI_task(%r12)
538 tm SP_PSW+1(%r15),0x01 # kernel per event ?
540 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
541 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
542 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
543 oi __TI_flags+7(%r12),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
544 lgf %r3,__LC_PGM_ILC # load program interruption code
546 ngr %r8,%r3 # clear per-event-bit and ilc
549 larl %r1,pgm_check_table
550 lg %r1,0(%r8,%r1) # load address of handler routine
551 la %r2,SP_PTREGS(%r15) # address of register-save area
552 basr %r14,%r1 # branch to interrupt-handler
555 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
559 # it was a single stepped SVC that is causing all the trouble
562 SAVE_ALL_PGM __LC_SVC_OLD_PSW,__LC_SAVE_AREA
563 CREATE_STACK_FRAME __LC_SAVE_AREA
564 mvc SP_PSW(16,%r15),__LC_SVC_OLD_PSW
565 mvc SP_ILC(4,%r15),__LC_SVC_ILC
566 lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct
567 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
568 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
569 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
572 lg %r8,__TI_task(%r12)
573 mvc __THREAD_per+__PER_atmid(2,%r8),__LC_PER_ATMID
574 mvc __THREAD_per+__PER_address(8,%r8),__LC_PER_ADDRESS
575 mvc __THREAD_per+__PER_access_id(1,%r8),__LC_PER_ACCESS_ID
576 oi __TI_flags+7(%r12),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
578 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
579 lmg %r2,%r6,SP_R2(%r15) # load svc arguments
583 # per was called from kernel, must be kprobes
586 xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number
587 la %r2,SP_PTREGS(%r15) # address of register-save area
588 brasl %r14,do_single_step
592 * IO interrupt handler routine
594 .globl io_int_handler
597 stpt __LC_ASYNC_ENTER_TIMER
598 SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+40
599 CREATE_STACK_FRAME __LC_SAVE_AREA+40
600 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
601 lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct
602 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
604 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
605 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
606 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
611 la %r2,SP_PTREGS(%r15) # address of register-save area
612 brasl %r14,do_IRQ # call standard irq handler
617 tm __TI_flags+7(%r12),_TIF_WORK_INT
618 jnz io_work # there is work to do (signals etc.)
620 RESTORE_ALL __LC_RETURN_PSW,0
624 # There is work todo, find out in which context we have been interrupted:
625 # 1) if we return to user space we can do all _TIF_WORK_INT work
626 # 2) if we return to kernel code and kvm is enabled check if we need to
627 # modify the psw to leave SIE
628 # 3) if we return to kernel code and preemptive scheduling is enabled check
629 # the preemption counter and if it is zero call preempt_schedule_irq
630 # Before any work can be done, a switch to the kernel stack is required.
633 tm SP_PSW+1(%r15),0x01 # returning to user ?
634 jo io_work_user # yes -> do resched & signal
635 #ifdef CONFIG_PREEMPT
636 # check for preemptive scheduling
637 icm %r0,15,__TI_precount(%r12)
638 jnz io_restore # preemption is disabled
639 tm __TI_flags+7(%r12),_TIF_NEED_RESCHED
641 # switch to kernel stack
644 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
645 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
647 # TRACE_IRQS_ON already done at io_return, call
648 # TRACE_IRQS_OFF to keep things symmetrical
650 brasl %r14,preempt_schedule_irq
657 # Need to do work before returning to userspace, switch to kernel stack
660 lg %r1,__LC_KERNEL_STACK
662 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
663 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
667 # One of the work bits is on. Find out which one.
668 # Checked are: _TIF_SIGPENDING, _TIF_NOTIFY_RESUME, _TIF_NEED_RESCHED
669 # and _TIF_MCCK_PENDING
672 tm __TI_flags+7(%r12),_TIF_MCCK_PENDING
674 tm __TI_flags+7(%r12),_TIF_NEED_RESCHED
676 tm __TI_flags+7(%r12),_TIF_SIGPENDING
678 tm __TI_flags+7(%r12),_TIF_NOTIFY_RESUME
680 j io_return # beware of critical section cleanup
683 # _TIF_MCCK_PENDING is set, call handler
686 # TRACE_IRQS_ON already done at io_return
687 brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler
692 # _TIF_NEED_RESCHED is set, call schedule
695 # TRACE_IRQS_ON already done at io_return
696 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
697 brasl %r14,schedule # call scheduler
698 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
703 # _TIF_SIGPENDING or is set, call do_signal
706 # TRACE_IRQS_ON already done at io_return
707 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
708 la %r2,SP_PTREGS(%r15) # load pt_regs
709 brasl %r14,do_signal # call do_signal
710 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
715 # _TIF_NOTIFY_RESUME or is set, call do_notify_resume
718 # TRACE_IRQS_ON already done at io_return
719 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
720 la %r2,SP_PTREGS(%r15) # load pt_regs
721 brasl %r14,do_notify_resume # call do_notify_resume
722 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
727 * External interrupt handler routine
729 .globl ext_int_handler
732 stpt __LC_ASYNC_ENTER_TIMER
733 SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+40
734 CREATE_STACK_FRAME __LC_SAVE_AREA+40
735 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
736 lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct
737 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
739 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
740 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
741 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
746 la %r2,SP_PTREGS(%r15) # address of register-save area
747 llgh %r3,__LC_EXT_INT_CODE # get interruption code
754 * Machine check handler routines
756 .globl mcck_int_handler
759 la %r1,4095 # revalidate r1
760 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer
761 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
762 stmg %r11,%r15,__LC_SAVE_AREA+80
763 larl %r13,system_call
764 lg %r11,__LC_LAST_BREAK
765 la %r12,__LC_MCK_OLD_PSW
766 tm __LC_MCCK_CODE,0x80 # system damage?
767 jo mcck_int_main # yes -> rest of mcck code invalid
769 mvc __LC_MCCK_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA-4095(%r14)
770 tm __LC_MCCK_CODE+5,0x02 # stored cpu timer value valid?
772 la %r14,__LC_SYNC_ENTER_TIMER
773 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
775 la %r14,__LC_ASYNC_ENTER_TIMER
776 0: clc 0(8,%r14),__LC_EXIT_TIMER
778 la %r14,__LC_EXIT_TIMER
779 0: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
781 la %r14,__LC_LAST_UPDATE_TIMER
783 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
784 1: tm __LC_MCCK_CODE+2,0x09 # mwp + ia of old psw valid?
785 jno mcck_int_main # no -> skip cleanup critical
786 tm __LC_MCK_OLD_PSW+1,0x01 # test problem state bit
787 jnz mcck_int_main # from user -> load kernel stack
788 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_end)
790 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_start)
792 brasl %r14,cleanup_critical
794 lg %r14,__LC_PANIC_STACK # are we already on the panic stack?
796 srag %r14,%r14,PAGE_SHIFT
798 lg %r15,__LC_PANIC_STACK # load panic stack
799 0: aghi %r15,-SP_SIZE # make room for registers & psw
800 CREATE_STACK_FRAME __LC_SAVE_AREA+80
801 mvc SP_PSW(16,%r15),0(%r12)
802 lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct
803 tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid?
804 jno mcck_no_vtime # no -> no timer update
805 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
807 UPDATE_VTIME __LC_EXIT_TIMER,__LC_MCCK_ENTER_TIMER,__LC_USER_TIMER
808 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
809 mvc __LC_LAST_UPDATE_TIMER(8),__LC_MCCK_ENTER_TIMER
812 la %r2,SP_PTREGS(%r15) # load pt_regs
813 brasl %r14,s390_do_machine_check
814 tm SP_PSW+1(%r15),0x01 # returning to user ?
816 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
818 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
819 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
821 stosm __SF_EMPTY(%r15),0x04 # turn dat on
822 tm __TI_flags+7(%r12),_TIF_MCCK_PENDING
826 brasl %r14,s390_handle_mcck
829 mvc __LC_RETURN_MCCK_PSW(16),SP_PSW(%r15) # move return PSW
830 ni __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit
831 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15
832 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
835 0: lpswe __LC_RETURN_MCCK_PSW # back to caller
839 * Restart interruption handler, kick starter for additional CPUs
843 .globl restart_int_handler
847 spt restart_vtime-restart_base(%r1)
848 stck __LC_LAST_UPDATE_CLOCK
849 mvc __LC_LAST_UPDATE_TIMER(8),restart_vtime-restart_base(%r1)
850 mvc __LC_EXIT_TIMER(8),restart_vtime-restart_base(%r1)
851 lg %r15,__LC_SAVE_AREA+120 # load ksp
852 lghi %r10,__LC_CREGS_SAVE_AREA
853 lctlg %c0,%c15,0(%r10) # get new ctl regs
854 lghi %r10,__LC_AREGS_SAVE_AREA
856 lmg %r6,%r15,__SF_GPRS(%r15) # load registers from clone
857 lg %r1,__LC_THREAD_INFO
858 mvc __LC_USER_TIMER(8),__TI_user_timer(%r1)
859 mvc __LC_SYSTEM_TIMER(8),__TI_system_timer(%r1)
860 xc __LC_STEAL_TIMER(8),__LC_STEAL_TIMER
861 stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on
865 .long 0x7fffffff,0xffffffff
869 * If we do not run with SMP enabled, let the new CPU crash ...
871 .globl restart_int_handler
875 lpswe restart_crash-restart_base(%r1)
878 .long 0x000a0000,0x00000000,0x00000000,0x00000000
882 #ifdef CONFIG_CHECK_STACK
884 * The synchronous or the asynchronous stack overflowed. We are dead.
885 * No need to properly save the registers, we are going to panic anyway.
886 * Setup a pt_regs so that show_trace can provide a good call trace.
889 lg %r15,__LC_PANIC_STACK # change to panic stack
891 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
892 stmg %r0,%r10,SP_R0(%r15) # store gprs %r0-%r10 to kernel stack
893 la %r1,__LC_SAVE_AREA
894 chi %r12,__LC_SVC_OLD_PSW
896 chi %r12,__LC_PGM_OLD_PSW
898 la %r1,__LC_SAVE_AREA+40
899 0: mvc SP_R11(40,%r15),0(%r1) # move %r11-%r15 to stack
900 mvc SP_ARGS(8,%r15),__LC_LAST_BREAK
901 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # clear back chain
902 la %r2,SP_PTREGS(%r15) # load pt_regs
903 jg kernel_stack_overflow
906 cleanup_table_system_call:
907 .quad system_call, sysc_do_svc
908 cleanup_table_sysc_tif:
909 .quad sysc_tif, sysc_restore
910 cleanup_table_sysc_restore:
911 .quad sysc_restore, sysc_done
912 cleanup_table_io_tif:
913 .quad io_tif, io_restore
914 cleanup_table_io_restore:
915 .quad io_restore, io_done
918 clc 8(8,%r12),BASED(cleanup_table_system_call)
920 clc 8(8,%r12),BASED(cleanup_table_system_call+8)
921 jl cleanup_system_call
923 clc 8(8,%r12),BASED(cleanup_table_sysc_tif)
925 clc 8(8,%r12),BASED(cleanup_table_sysc_tif+8)
928 clc 8(8,%r12),BASED(cleanup_table_sysc_restore)
930 clc 8(8,%r12),BASED(cleanup_table_sysc_restore+8)
931 jl cleanup_sysc_restore
933 clc 8(8,%r12),BASED(cleanup_table_io_tif)
935 clc 8(8,%r12),BASED(cleanup_table_io_tif+8)
938 clc 8(8,%r12),BASED(cleanup_table_io_restore)
940 clc 8(8,%r12),BASED(cleanup_table_io_restore+8)
941 jl cleanup_io_restore
946 mvc __LC_RETURN_PSW(16),0(%r12)
947 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+8)
949 mvc __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
950 cghi %r12,__LC_MCK_OLD_PSW
952 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
953 0: cghi %r12,__LC_MCK_OLD_PSW
954 la %r12,__LC_SAVE_AREA+80
956 la %r12,__LC_SAVE_AREA+40
957 0: clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+16)
959 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn)
961 mvc __LC_SAVE_AREA(40),0(%r12)
962 0: lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
963 aghi %r15,-SP_SIZE # make room for registers & psw
966 CREATE_STACK_FRAME __LC_SAVE_AREA
967 mvc SP_PSW(16,%r15),__LC_SVC_OLD_PSW
968 mvc SP_ILC(4,%r15),__LC_SVC_ILC
969 stg %r7,SP_ARGS(%r15)
970 mvc 8(8,%r12),__LC_THREAD_INFO
972 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+24)
974 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
976 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+32)
978 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
980 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
982 lg %r12,__LC_THREAD_INFO
984 stg %r11,__TI_last_break(%r12)
985 0: mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8)
986 la %r12,__LC_RETURN_PSW
988 cleanup_system_call_insn:
996 mvc __LC_RETURN_PSW(8),0(%r12)
997 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_tif)
998 la %r12,__LC_RETURN_PSW
1001 cleanup_sysc_restore:
1002 clc 8(8,%r12),BASED(cleanup_sysc_restore_insn)
1004 clc 8(8,%r12),BASED(cleanup_sysc_restore_insn+8)
1006 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
1007 cghi %r12,__LC_MCK_OLD_PSW
1009 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
1010 0: mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
1011 cghi %r12,__LC_MCK_OLD_PSW
1012 la %r12,__LC_SAVE_AREA+80
1014 la %r12,__LC_SAVE_AREA+40
1015 1: mvc 0(40,%r12),SP_R11(%r15)
1016 lmg %r0,%r10,SP_R0(%r15)
1017 lg %r15,SP_R15(%r15)
1018 2: la %r12,__LC_RETURN_PSW
1020 cleanup_sysc_restore_insn:
1022 .quad sysc_done - 16
1025 mvc __LC_RETURN_PSW(8),0(%r12)
1026 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_io_tif)
1027 la %r12,__LC_RETURN_PSW
1031 clc 8(8,%r12),BASED(cleanup_io_restore_insn)
1033 clc 8(8,%r12),BASED(cleanup_io_restore_insn+8)
1035 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
1036 0: mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
1037 mvc __LC_SAVE_AREA+80(40),SP_R11(%r15)
1038 lmg %r0,%r10,SP_R0(%r15)
1039 lg %r15,SP_R15(%r15)
1040 1: la %r12,__LC_RETURN_PSW
1042 cleanup_io_restore_insn:
1051 .quad __critical_start
1053 .quad __critical_end
1055 .section .rodata, "a"
1056 #define SYSCALL(esa,esame,emu) .long esame
1057 .globl sys_call_table
1059 #include "syscalls.S"
1062 #ifdef CONFIG_COMPAT
1064 #define SYSCALL(esa,esame,emu) .long emu
1066 #include "syscalls.S"