2 * linux/arch/sh/boards/se/7724/setup.c
4 * Copyright (C) 2009 Renesas Solutions Corp.
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
14 #include <linux/device.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
17 #include <linux/mfd/sh_mobile_sdhi.h>
18 #include <linux/mtd/physmap.h>
19 #include <linux/delay.h>
20 #include <linux/smc91x.h>
21 #include <linux/gpio.h>
22 #include <linux/input.h>
23 #include <linux/input/sh_keysc.h>
24 #include <linux/usb/r8a66597.h>
25 #include <video/sh_mobile_lcdc.h>
26 #include <media/sh_mobile_ceu.h>
27 #include <sound/sh_fsi.h>
29 #include <asm/heartbeat.h>
30 #include <asm/sh_eth.h>
31 #include <asm/clock.h>
32 #include <asm/suspend.h>
33 #include <cpu/sh7724.h>
34 #include <mach-se/mach/se7724.h>
38 * ------------------------------------
39 * SW31 : 1001 1100 : default
40 * SW32 : 0111 1111 : use on board flash
42 * SW41 : abxx xxxx -> a = 0 : Analog monitor
51 * When you use 1280 x 720 lcdc output,
52 * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz,
53 * and change SW41 to use 720p
59 * This setup.c supports FSI slave mode.
60 * Please change J20, J21, J22 pin to 1-2 connection.
64 static struct resource heartbeat_resource = {
67 .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
70 static struct platform_device heartbeat_device = {
74 .resource = &heartbeat_resource,
78 static struct smc91x_platdata smc91x_info = {
79 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
82 static struct resource smc91x_eth_resources[] = {
87 .flags = IORESOURCE_MEM,
91 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
95 static struct platform_device smc91x_eth_device = {
97 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
98 .resource = smc91x_eth_resources,
100 .platform_data = &smc91x_info,
105 static struct mtd_partition nor_flash_partitions[] = {
109 .size = (1 * 1024 * 1024),
110 .mask_flags = MTD_WRITEABLE, /* Read-only */
113 .offset = MTDPART_OFS_APPEND,
114 .size = (2 * 1024 * 1024),
117 .offset = MTDPART_OFS_APPEND,
118 .size = MTDPART_SIZ_FULL,
122 static struct physmap_flash_data nor_flash_data = {
124 .parts = nor_flash_partitions,
125 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
128 static struct resource nor_flash_resources[] = {
133 .flags = IORESOURCE_MEM,
137 static struct platform_device nor_flash_device = {
138 .name = "physmap-flash",
139 .resource = nor_flash_resources,
140 .num_resources = ARRAY_SIZE(nor_flash_resources),
142 .platform_data = &nor_flash_data,
147 const static struct fb_videomode lcdc_720p_modes[] = {
150 .sync = 0, /* hsync and vsync are active low */
162 const static struct fb_videomode lcdc_vga_modes[] = {
165 .sync = 0, /* hsync and vsync are active low */
177 static struct sh_mobile_lcdc_info lcdc_info = {
178 .clock_source = LCDC_CLK_EXTERNAL,
180 .chan = LCDC_CHAN_MAINLCD,
183 .lcd_size_cfg = { /* 7.0 inch */
192 static struct resource lcdc_resources[] = {
197 .flags = IORESOURCE_MEM,
201 .flags = IORESOURCE_IRQ,
205 static struct platform_device lcdc_device = {
206 .name = "sh_mobile_lcdc_fb",
207 .num_resources = ARRAY_SIZE(lcdc_resources),
208 .resource = lcdc_resources,
210 .platform_data = &lcdc_info,
213 .hwblk_id = HWBLK_LCDC,
218 static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
219 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
222 static struct resource ceu0_resources[] = {
227 .flags = IORESOURCE_MEM,
231 .flags = IORESOURCE_IRQ,
234 /* place holder for contiguous memory */
238 static struct platform_device ceu0_device = {
239 .name = "sh_mobile_ceu",
240 .id = 0, /* "ceu0" clock */
241 .num_resources = ARRAY_SIZE(ceu0_resources),
242 .resource = ceu0_resources,
244 .platform_data = &sh_mobile_ceu0_info,
247 .hwblk_id = HWBLK_CEU0,
252 static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
253 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
256 static struct resource ceu1_resources[] = {
261 .flags = IORESOURCE_MEM,
265 .flags = IORESOURCE_IRQ,
268 /* place holder for contiguous memory */
272 static struct platform_device ceu1_device = {
273 .name = "sh_mobile_ceu",
274 .id = 1, /* "ceu1" clock */
275 .num_resources = ARRAY_SIZE(ceu1_resources),
276 .resource = ceu1_resources,
278 .platform_data = &sh_mobile_ceu1_info,
281 .hwblk_id = HWBLK_CEU1,
286 /* change J20, J21, J22 pin to 1-2 connection to use slave mode */
287 static struct sh_fsi_platform_info fsi_info = {
288 .porta_flags = SH_FSI_BRS_INV |
289 SH_FSI_OUT_SLAVE_MODE |
290 SH_FSI_IN_SLAVE_MODE |
295 static struct resource fsi_resources[] = {
300 .flags = IORESOURCE_MEM,
304 .flags = IORESOURCE_IRQ,
308 static struct platform_device fsi_device = {
311 .num_resources = ARRAY_SIZE(fsi_resources),
312 .resource = fsi_resources,
314 .platform_data = &fsi_info,
317 .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */
321 static struct platform_device fsi_ak4642_device = {
322 .name = "sh_fsi_a_ak4642",
325 /* KEYSC in SoC (Needs SW33-2 set to ON) */
326 static struct sh_keysc_info keysc_info = {
327 .mode = SH_KEYSC_MODE_1,
331 KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
332 KEY_6, KEY_7, KEY_8, KEY_9, KEY_A,
333 KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
334 KEY_G, KEY_H, KEY_I, KEY_K, KEY_L,
335 KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q,
336 KEY_R, KEY_S, KEY_T, KEY_U, KEY_V,
340 static struct resource keysc_resources[] = {
345 .flags = IORESOURCE_MEM,
349 .flags = IORESOURCE_IRQ,
353 static struct platform_device keysc_device = {
355 .id = 0, /* "keysc0" clock */
356 .num_resources = ARRAY_SIZE(keysc_resources),
357 .resource = keysc_resources,
359 .platform_data = &keysc_info,
362 .hwblk_id = HWBLK_KEYSC,
367 static struct resource sh_eth_resources[] = {
369 .start = SH_ETH_ADDR,
370 .end = SH_ETH_ADDR + 0x1FC,
371 .flags = IORESOURCE_MEM,
375 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
379 static struct sh_eth_plat_data sh_eth_plat = {
380 .phy = 0x1f, /* SMSC LAN8187 */
381 .edmac_endian = EDMAC_LITTLE_ENDIAN,
384 static struct platform_device sh_eth_device = {
388 .platform_data = &sh_eth_plat,
390 .num_resources = ARRAY_SIZE(sh_eth_resources),
391 .resource = sh_eth_resources,
393 .hwblk_id = HWBLK_ETHER,
397 static struct r8a66597_platdata sh7724_usb0_host_data = {
401 static struct resource sh7724_usb0_host_resources[] = {
404 .end = 0xa4d80124 - 1,
405 .flags = IORESOURCE_MEM,
410 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
414 static struct platform_device sh7724_usb0_host_device = {
415 .name = "r8a66597_hcd",
418 .dma_mask = NULL, /* not use dma */
419 .coherent_dma_mask = 0xffffffff,
420 .platform_data = &sh7724_usb0_host_data,
422 .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources),
423 .resource = sh7724_usb0_host_resources,
425 .hwblk_id = HWBLK_USB0,
429 static struct r8a66597_platdata sh7724_usb1_gadget_data = {
433 static struct resource sh7724_usb1_gadget_resources[] = {
437 .flags = IORESOURCE_MEM,
442 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
446 static struct platform_device sh7724_usb1_gadget_device = {
447 .name = "r8a66597_udc",
450 .dma_mask = NULL, /* not use dma */
451 .coherent_dma_mask = 0xffffffff,
452 .platform_data = &sh7724_usb1_gadget_data,
454 .num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources),
455 .resource = sh7724_usb1_gadget_resources,
458 static struct resource sdhi0_cn7_resources[] = {
463 .flags = IORESOURCE_MEM,
467 .flags = IORESOURCE_IRQ,
471 static struct sh_mobile_sdhi_info sh7724_sdhi0_data = {
472 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
473 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
476 static struct platform_device sdhi0_cn7_device = {
477 .name = "sh_mobile_sdhi",
479 .num_resources = ARRAY_SIZE(sdhi0_cn7_resources),
480 .resource = sdhi0_cn7_resources,
482 .platform_data = &sh7724_sdhi0_data,
485 .hwblk_id = HWBLK_SDHI0,
489 static struct resource sdhi1_cn8_resources[] = {
494 .flags = IORESOURCE_MEM,
498 .flags = IORESOURCE_IRQ,
502 static struct sh_mobile_sdhi_info sh7724_sdhi1_data = {
503 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
504 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
507 static struct platform_device sdhi1_cn8_device = {
508 .name = "sh_mobile_sdhi",
510 .num_resources = ARRAY_SIZE(sdhi1_cn8_resources),
511 .resource = sdhi1_cn8_resources,
513 .platform_data = &sh7724_sdhi1_data,
516 .hwblk_id = HWBLK_SDHI1,
521 static struct resource irda_resources[] = {
526 .flags = IORESOURCE_MEM,
530 .flags = IORESOURCE_IRQ,
534 static struct platform_device irda_device = {
536 .num_resources = ARRAY_SIZE(irda_resources),
537 .resource = irda_resources,
540 #include <media/ak881x.h>
541 #include <media/sh_vou.h>
543 static struct ak881x_pdata ak881x_pdata = {
544 .flags = AK881X_IF_MODE_SLAVE,
547 static struct i2c_board_info ak8813 = {
548 /* With open J18 jumper address is 0x21 */
549 I2C_BOARD_INFO("ak8813", 0x20),
550 .platform_data = &ak881x_pdata,
553 static struct sh_vou_pdata sh_vou_pdata = {
554 .bus_fmt = SH_VOU_BUS_8BIT,
555 .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
556 .board_info = &ak8813,
560 static struct resource sh_vou_resources[] = {
564 .flags = IORESOURCE_MEM,
568 .flags = IORESOURCE_IRQ,
572 static struct platform_device vou_device = {
575 .num_resources = ARRAY_SIZE(sh_vou_resources),
576 .resource = sh_vou_resources,
578 .platform_data = &sh_vou_pdata,
581 .hwblk_id = HWBLK_VOU,
585 static struct platform_device *ms7724se_devices[] __initdata = {
594 &sh7724_usb0_host_device,
595 &sh7724_usb1_gadget_device,
605 static struct i2c_board_info i2c0_devices[] = {
607 I2C_BOARD_INFO("ak4642", 0x12),
611 #define EEPROM_OP 0xBA206000
612 #define EEPROM_ADR 0xBA206004
613 #define EEPROM_DATA 0xBA20600C
614 #define EEPROM_STAT 0xBA206010
615 #define EEPROM_STRT 0xBA206014
616 static int __init sh_eth_is_eeprom_ready(void)
621 if (!__raw_readw(EEPROM_STAT))
626 printk(KERN_ERR "ms7724se can not access to eeprom\n");
630 static void __init sh_eth_init(void)
635 /* check EEPROM status */
636 if (!sh_eth_is_eeprom_ready())
639 /* read MAC addr from EEPROM */
640 for (i = 0 ; i < 3 ; i++) {
641 __raw_writew(0x0, EEPROM_OP); /* read */
642 __raw_writew(i*2, EEPROM_ADR);
643 __raw_writew(0x1, EEPROM_STRT);
644 if (!sh_eth_is_eeprom_ready())
647 mac = __raw_readw(EEPROM_DATA);
648 sh_eth_plat.mac_addr[i << 1] = mac & 0xff;
649 sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8;
653 #define SW4140 0xBA201000
654 #define FPGA_OUT 0xBA200400
655 #define PORT_HIZA 0xA4050158
656 #define PORT_MSELCRB 0xA4050182
658 #define SW41_A 0x0100
659 #define SW41_B 0x0200
660 #define SW41_C 0x0400
661 #define SW41_D 0x0800
662 #define SW41_E 0x1000
663 #define SW41_F 0x2000
664 #define SW41_G 0x4000
665 #define SW41_H 0x8000
667 extern char ms7724se_sdram_enter_start;
668 extern char ms7724se_sdram_enter_end;
669 extern char ms7724se_sdram_leave_start;
670 extern char ms7724se_sdram_leave_end;
673 static int __init arch_setup(void)
675 /* enable I2C device */
676 i2c_register_board_info(0, i2c0_devices,
677 ARRAY_SIZE(i2c0_devices));
680 arch_initcall(arch_setup);
682 static int __init devices_setup(void)
684 u16 sw = __raw_readw(SW4140); /* select camera, monitor */
688 /* register board specific self-refresh code */
689 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
691 &ms7724se_sdram_enter_start,
692 &ms7724se_sdram_enter_end,
693 &ms7724se_sdram_leave_start,
694 &ms7724se_sdram_leave_end);
696 fpga_out = __raw_readw(FPGA_OUT);
697 /* bit4: NTSC_PDN, bit5: NTSC_RESET */
698 fpga_out &= ~((1 << 1) | /* LAN */
699 (1 << 4) | /* AK8813 PDN */
700 (1 << 5) | /* AK8813 RESET */
701 (1 << 6) | /* VIDEO DAC */
702 (1 << 7) | /* AK4643 */
703 (1 << 8) | /* IrDA */
704 (1 << 12) | /* USB0 */
705 (1 << 14)); /* RMII */
706 __raw_writew(fpga_out | (1 << 4), FPGA_OUT);
711 __raw_writew(fpga_out | (1 << 5), FPGA_OUT);
715 __raw_writew(fpga_out, FPGA_OUT);
717 /* turn on USB clocks, use external clock */
718 __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
720 /* Let LED9 show STATUS2 */
721 gpio_request(GPIO_FN_STATUS2, NULL);
723 /* Lit LED10 show STATUS0 */
724 gpio_request(GPIO_FN_STATUS0, NULL);
726 /* Lit LED11 show PDSTATUS */
727 gpio_request(GPIO_FN_PDSTATUS, NULL);
729 /* enable USB0 port */
730 __raw_writew(0x0600, 0xa40501d4);
732 /* enable USB1 port */
733 __raw_writew(0x0600, 0xa4050192);
735 /* enable IRQ 0,1,2 */
736 gpio_request(GPIO_FN_INTC_IRQ0, NULL);
737 gpio_request(GPIO_FN_INTC_IRQ1, NULL);
738 gpio_request(GPIO_FN_INTC_IRQ2, NULL);
741 gpio_request(GPIO_FN_SCIF3_I_SCK, NULL);
742 gpio_request(GPIO_FN_SCIF3_I_RXD, NULL);
743 gpio_request(GPIO_FN_SCIF3_I_TXD, NULL);
744 gpio_request(GPIO_FN_SCIF3_I_CTS, NULL);
745 gpio_request(GPIO_FN_SCIF3_I_RTS, NULL);
748 gpio_request(GPIO_FN_LCDD23, NULL);
749 gpio_request(GPIO_FN_LCDD22, NULL);
750 gpio_request(GPIO_FN_LCDD21, NULL);
751 gpio_request(GPIO_FN_LCDD20, NULL);
752 gpio_request(GPIO_FN_LCDD19, NULL);
753 gpio_request(GPIO_FN_LCDD18, NULL);
754 gpio_request(GPIO_FN_LCDD17, NULL);
755 gpio_request(GPIO_FN_LCDD16, NULL);
756 gpio_request(GPIO_FN_LCDD15, NULL);
757 gpio_request(GPIO_FN_LCDD14, NULL);
758 gpio_request(GPIO_FN_LCDD13, NULL);
759 gpio_request(GPIO_FN_LCDD12, NULL);
760 gpio_request(GPIO_FN_LCDD11, NULL);
761 gpio_request(GPIO_FN_LCDD10, NULL);
762 gpio_request(GPIO_FN_LCDD9, NULL);
763 gpio_request(GPIO_FN_LCDD8, NULL);
764 gpio_request(GPIO_FN_LCDD7, NULL);
765 gpio_request(GPIO_FN_LCDD6, NULL);
766 gpio_request(GPIO_FN_LCDD5, NULL);
767 gpio_request(GPIO_FN_LCDD4, NULL);
768 gpio_request(GPIO_FN_LCDD3, NULL);
769 gpio_request(GPIO_FN_LCDD2, NULL);
770 gpio_request(GPIO_FN_LCDD1, NULL);
771 gpio_request(GPIO_FN_LCDD0, NULL);
772 gpio_request(GPIO_FN_LCDDISP, NULL);
773 gpio_request(GPIO_FN_LCDHSYN, NULL);
774 gpio_request(GPIO_FN_LCDDCK, NULL);
775 gpio_request(GPIO_FN_LCDVSYN, NULL);
776 gpio_request(GPIO_FN_LCDDON, NULL);
777 gpio_request(GPIO_FN_LCDVEPWC, NULL);
778 gpio_request(GPIO_FN_LCDVCPWC, NULL);
779 gpio_request(GPIO_FN_LCDRD, NULL);
780 gpio_request(GPIO_FN_LCDLCLK, NULL);
781 __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
784 gpio_request(GPIO_FN_VIO0_D15, NULL);
785 gpio_request(GPIO_FN_VIO0_D14, NULL);
786 gpio_request(GPIO_FN_VIO0_D13, NULL);
787 gpio_request(GPIO_FN_VIO0_D12, NULL);
788 gpio_request(GPIO_FN_VIO0_D11, NULL);
789 gpio_request(GPIO_FN_VIO0_D10, NULL);
790 gpio_request(GPIO_FN_VIO0_D9, NULL);
791 gpio_request(GPIO_FN_VIO0_D8, NULL);
792 gpio_request(GPIO_FN_VIO0_D7, NULL);
793 gpio_request(GPIO_FN_VIO0_D6, NULL);
794 gpio_request(GPIO_FN_VIO0_D5, NULL);
795 gpio_request(GPIO_FN_VIO0_D4, NULL);
796 gpio_request(GPIO_FN_VIO0_D3, NULL);
797 gpio_request(GPIO_FN_VIO0_D2, NULL);
798 gpio_request(GPIO_FN_VIO0_D1, NULL);
799 gpio_request(GPIO_FN_VIO0_D0, NULL);
800 gpio_request(GPIO_FN_VIO0_VD, NULL);
801 gpio_request(GPIO_FN_VIO0_CLK, NULL);
802 gpio_request(GPIO_FN_VIO0_FLD, NULL);
803 gpio_request(GPIO_FN_VIO0_HD, NULL);
804 platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
807 gpio_request(GPIO_FN_VIO1_D7, NULL);
808 gpio_request(GPIO_FN_VIO1_D6, NULL);
809 gpio_request(GPIO_FN_VIO1_D5, NULL);
810 gpio_request(GPIO_FN_VIO1_D4, NULL);
811 gpio_request(GPIO_FN_VIO1_D3, NULL);
812 gpio_request(GPIO_FN_VIO1_D2, NULL);
813 gpio_request(GPIO_FN_VIO1_D1, NULL);
814 gpio_request(GPIO_FN_VIO1_D0, NULL);
815 gpio_request(GPIO_FN_VIO1_FLD, NULL);
816 gpio_request(GPIO_FN_VIO1_HD, NULL);
817 gpio_request(GPIO_FN_VIO1_VD, NULL);
818 gpio_request(GPIO_FN_VIO1_CLK, NULL);
819 platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
822 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
823 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
824 gpio_request(GPIO_FN_KEYIN4, NULL);
825 gpio_request(GPIO_FN_KEYIN3, NULL);
826 gpio_request(GPIO_FN_KEYIN2, NULL);
827 gpio_request(GPIO_FN_KEYIN1, NULL);
828 gpio_request(GPIO_FN_KEYIN0, NULL);
829 gpio_request(GPIO_FN_KEYOUT3, NULL);
830 gpio_request(GPIO_FN_KEYOUT2, NULL);
831 gpio_request(GPIO_FN_KEYOUT1, NULL);
832 gpio_request(GPIO_FN_KEYOUT0, NULL);
835 gpio_request(GPIO_FN_FSIMCKA, NULL);
836 gpio_request(GPIO_FN_FSIIASD, NULL);
837 gpio_request(GPIO_FN_FSIOASD, NULL);
838 gpio_request(GPIO_FN_FSIIABCK, NULL);
839 gpio_request(GPIO_FN_FSIIALRCK, NULL);
840 gpio_request(GPIO_FN_FSIOABCK, NULL);
841 gpio_request(GPIO_FN_FSIOALRCK, NULL);
842 gpio_request(GPIO_FN_CLKAUDIOAO, NULL);
844 /* set SPU2 clock to 83.4 MHz */
845 clk = clk_get(NULL, "spu_clk");
847 clk_set_rate(clk, clk_round_rate(clk, 83333333));
851 /* change parent of FSI A */
852 clk = clk_get(NULL, "fsia_clk");
854 /* 48kHz dummy clock was used to make sure 1/1 divide */
855 clk_set_rate(&sh7724_fsimcka_clk, 48000);
856 clk_set_parent(clk, &sh7724_fsimcka_clk);
857 clk_set_rate(clk, 48000);
861 /* SDHI0 connected to cn7 */
862 gpio_request(GPIO_FN_SDHI0CD, NULL);
863 gpio_request(GPIO_FN_SDHI0WP, NULL);
864 gpio_request(GPIO_FN_SDHI0D3, NULL);
865 gpio_request(GPIO_FN_SDHI0D2, NULL);
866 gpio_request(GPIO_FN_SDHI0D1, NULL);
867 gpio_request(GPIO_FN_SDHI0D0, NULL);
868 gpio_request(GPIO_FN_SDHI0CMD, NULL);
869 gpio_request(GPIO_FN_SDHI0CLK, NULL);
871 /* SDHI1 connected to cn8 */
872 gpio_request(GPIO_FN_SDHI1CD, NULL);
873 gpio_request(GPIO_FN_SDHI1WP, NULL);
874 gpio_request(GPIO_FN_SDHI1D3, NULL);
875 gpio_request(GPIO_FN_SDHI1D2, NULL);
876 gpio_request(GPIO_FN_SDHI1D1, NULL);
877 gpio_request(GPIO_FN_SDHI1D0, NULL);
878 gpio_request(GPIO_FN_SDHI1CMD, NULL);
879 gpio_request(GPIO_FN_SDHI1CLK, NULL);
882 gpio_request(GPIO_FN_IRDA_OUT, NULL);
883 gpio_request(GPIO_FN_IRDA_IN, NULL);
888 * please remove J33 pin from your board !!
890 * ms7724 board should not use GPIO_FN_LNKSTA pin
891 * So, This time PTX5 is set to input pin
893 gpio_request(GPIO_FN_RMII_RXD0, NULL);
894 gpio_request(GPIO_FN_RMII_RXD1, NULL);
895 gpio_request(GPIO_FN_RMII_TXD0, NULL);
896 gpio_request(GPIO_FN_RMII_TXD1, NULL);
897 gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
898 gpio_request(GPIO_FN_RMII_TX_EN, NULL);
899 gpio_request(GPIO_FN_RMII_RX_ER, NULL);
900 gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
901 gpio_request(GPIO_FN_MDIO, NULL);
902 gpio_request(GPIO_FN_MDC, NULL);
903 gpio_request(GPIO_PTX5, NULL);
904 gpio_direction_input(GPIO_PTX5);
909 lcdc_info.ch[0].lcd_cfg = lcdc_720p_modes;
910 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_720p_modes);
913 lcdc_info.ch[0].lcd_cfg = lcdc_vga_modes;
914 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_vga_modes);
918 /* Digital monitor */
919 lcdc_info.ch[0].interface_type = RGB18;
920 lcdc_info.ch[0].flags = 0;
923 lcdc_info.ch[0].interface_type = RGB24;
924 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
928 gpio_request(GPIO_FN_DV_D15, NULL);
929 gpio_request(GPIO_FN_DV_D14, NULL);
930 gpio_request(GPIO_FN_DV_D13, NULL);
931 gpio_request(GPIO_FN_DV_D12, NULL);
932 gpio_request(GPIO_FN_DV_D11, NULL);
933 gpio_request(GPIO_FN_DV_D10, NULL);
934 gpio_request(GPIO_FN_DV_D9, NULL);
935 gpio_request(GPIO_FN_DV_D8, NULL);
936 gpio_request(GPIO_FN_DV_CLKI, NULL);
937 gpio_request(GPIO_FN_DV_CLK, NULL);
938 gpio_request(GPIO_FN_DV_VSYNC, NULL);
939 gpio_request(GPIO_FN_DV_HSYNC, NULL);
941 return platform_add_devices(ms7724se_devices,
942 ARRAY_SIZE(ms7724se_devices));
944 device_initcall(devices_setup);
946 static struct sh_machine_vector mv_ms7724se __initmv = {
947 .mv_name = "ms7724se",
948 .mv_init_irq = init_se7724_IRQ,
949 .mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR,