2 * arch/sh/boards/se/73180/irq.c
4 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
5 * Based on arch/sh/boards/se/7300/irq.c
7 * Modified for SH-Mobile SolutionEngine 73180 Support
8 * by YOSHII Takashi <yoshii-takashi@hitachi-ul.co.jp>
12 #include <linux/init.h>
13 #include <linux/irq.h>
16 #include <asm/mach/se73180.h>
23 return 7 - (irq - 32);
27 disable_intreq_irq(unsigned int irq)
29 ctrl_outb(1 << (7 - irq2intreq(irq)), INTMSK0);
33 enable_intreq_irq(unsigned int irq)
35 ctrl_outb(1 << (7 - irq2intreq(irq)), INTMSKCLR0);
39 mask_and_ack_intreq_irq(unsigned int irq)
41 disable_intreq_irq(irq);
45 startup_intreq_irq(unsigned int irq)
47 enable_intreq_irq(irq);
52 shutdown_intreq_irq(unsigned int irq)
54 disable_intreq_irq(irq);
58 end_intreq_irq(unsigned int irq)
60 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
61 enable_intreq_irq(irq);
64 static struct hw_interrupt_type intreq_irq_type = {
66 .startup = startup_intreq_irq,
67 .shutdown = shutdown_intreq_irq,
68 .enable = enable_intreq_irq,
69 .disable = disable_intreq_irq,
70 .ack = mask_and_ack_intreq_irq,
75 make_intreq_irq(unsigned int irq)
77 disable_irq_nosync(irq);
78 irq_desc[irq].chip = &intreq_irq_type;
79 disable_intreq_irq(irq);
83 shmse_irq_demux(int irq)
90 static struct ipr_data se73180_siof0_ipr_map[] = {
91 { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
93 static struct ipr_data se73180_vpu_ipr_map[] = {
94 { VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 },
96 static struct ipr_data se73180_other_ipr_map[] = {
97 { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
98 { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
99 { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
100 { IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
101 { IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
102 { IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
103 { IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
104 { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
105 { SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY },
108 { CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
109 { BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
110 { VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
112 { LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY },
116 * Initialize IRQ setting
119 init_73180se_IRQ(void)
121 make_ipr_irq(se73180_siof0_ipr_map, ARRAY_SIZE(se73180_siof0_ipr_map));
123 ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */
124 ctrl_outw(0x2000, 0xb07fffec); /* mrshpc irq enable */
125 ctrl_outl(3 << ((7 - 5) * 4), INTC_INTPRI0); /* irq5 pri=3 */
126 ctrl_outw(2 << ((7 - 5) * 2), INTC_ICR1); /* low-level irq */
129 make_ipr_irq(se73180_vpu_ipr_map, ARRAY_SIZE(se73180_vpu_ipr_map));
131 ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */
133 make_ipr_irq(se73180_other_ipr_map, ARRAY_SIZE(se73180_other_ipr_map));
135 ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */