2 * Low-Level PCI Express Support for the SH7786
4 * Copyright (C) 2009 - 2010 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include "pcie-sh7786.h"
16 #include <asm/sizes.h>
18 struct sh7786_pcie_port {
19 struct pci_channel *hose;
25 static struct sh7786_pcie_port *sh7786_pcie_ports;
26 static unsigned int nr_ports;
28 static struct sh7786_pcie_hwops {
29 int (*core_init)(void);
30 int (*port_init_hw)(struct sh7786_pcie_port *port);
33 static struct resource sh7786_pci0_resources[] = {
37 .end = 0xfd000000 + SZ_8M - 1,
38 .flags = IORESOURCE_IO,
40 .name = "PCIe0 MEM 0",
42 .end = 0xc0000000 + SZ_512M - 1,
43 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
45 .name = "PCIe0 MEM 1",
47 .end = 0x10000000 + SZ_64M - 1,
48 .flags = IORESOURCE_MEM,
50 .name = "PCIe0 MEM 2",
52 .end = 0xfe100000 + SZ_1M - 1,
56 static struct resource sh7786_pci1_resources[] = {
60 .end = 0xfd800000 + SZ_8M - 1,
61 .flags = IORESOURCE_IO,
63 .name = "PCIe1 MEM 0",
65 .end = 0xa0000000 + SZ_512M - 1,
66 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
68 .name = "PCIe1 MEM 1",
70 .end = 0x30000000 + SZ_256M - 1,
71 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
73 .name = "PCIe1 MEM 2",
75 .end = 0xfe300000 + SZ_1M - 1,
79 static struct resource sh7786_pci2_resources[] = {
83 .end = 0xfc800000 + SZ_4M - 1,
85 .name = "PCIe2 MEM 0",
87 .end = 0x80000000 + SZ_512M - 1,
88 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
90 .name = "PCIe2 MEM 1",
92 .end = 0x20000000 + SZ_256M - 1,
93 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
95 .name = "PCIe2 MEM 2",
97 .end = 0xfcd00000 + SZ_1M - 1,
101 extern struct pci_ops sh7786_pci_ops;
103 #define DEFINE_CONTROLLER(start, idx) \
105 .pci_ops = &sh7786_pci_ops, \
106 .resources = sh7786_pci##idx##_resources, \
107 .nr_resources = ARRAY_SIZE(sh7786_pci##idx##_resources), \
113 static struct pci_channel sh7786_pci_channels[] = {
114 DEFINE_CONTROLLER(0xfe000000, 0),
115 DEFINE_CONTROLLER(0xfe200000, 1),
116 DEFINE_CONTROLLER(0xfcc00000, 2),
119 static int phy_wait_for_ack(struct pci_channel *chan)
121 unsigned int timeout = 100;
124 if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK))
133 static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
135 unsigned int timeout = 100;
138 if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask)
147 static void phy_write_reg(struct pci_channel *chan, unsigned int addr,
148 unsigned int lane, unsigned int data)
150 unsigned long phyaddr, ctrl;
152 phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) +
153 ((addr & 0xff) << BITS_ADR);
156 ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
157 ctrl |= (1 << BITS_CKE);
158 pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
161 pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
162 pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);
164 phy_wait_for_ack(chan);
167 pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);
169 phy_wait_for_ack(chan);
172 ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
173 ctrl &= ~(1 << BITS_CKE);
174 pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
177 static int phy_init(struct pci_channel *chan)
179 unsigned int timeout = 100;
181 /* Initialize the phy */
182 phy_write_reg(chan, 0x60, 0xf, 0x004b008b);
183 phy_write_reg(chan, 0x61, 0xf, 0x00007b41);
184 phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00);
185 phy_write_reg(chan, 0x65, 0xf, 0x09070907);
186 phy_write_reg(chan, 0x66, 0xf, 0x00000010);
187 phy_write_reg(chan, 0x74, 0xf, 0x0007001c);
188 phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);
190 /* Deassert Standby */
191 phy_write_reg(chan, 0x67, 0xf, 0x00000400);
194 if (pci_read_reg(chan, SH4A_PCIEPHYSR))
203 static int pcie_init(struct sh7786_pcie_port *port)
205 struct pci_channel *chan = port->hose;
211 /* Begin initialization */
212 pci_write_reg(chan, 0, SH4A_PCIETCTLR);
214 /* Initialize as type1. */
215 data = pci_read_reg(chan, SH4A_PCIEPCICONF3);
216 data &= ~(0x7f << 16);
217 data |= PCI_HEADER_TYPE_BRIDGE << 16;
218 pci_write_reg(chan, data, SH4A_PCIEPCICONF3);
220 /* Initialize default capabilities. */
221 data = pci_read_reg(chan, SH4A_PCIEEXPCAP0);
222 data &= ~(PCI_EXP_FLAGS_TYPE << 16);
225 data |= PCI_EXP_TYPE_ENDPOINT << 20;
227 data |= PCI_EXP_TYPE_ROOT_PORT << 20;
229 data |= PCI_CAP_ID_EXP;
230 pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);
232 /* Enable data link layer active state reporting */
233 pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3);
235 /* Enable extended sync and ASPM L0s support */
236 data = pci_read_reg(chan, SH4A_PCIEEXPCAP4);
237 data &= ~PCI_EXP_LNKCTL_ASPMC;
238 data |= PCI_EXP_LNKCTL_ES | 1;
239 pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);
241 /* Write out the physical slot number */
242 data = pci_read_reg(chan, SH4A_PCIEEXPCAP5);
243 data &= ~PCI_EXP_SLTCAP_PSN;
244 data |= (port->index + 1) << 19;
245 pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);
247 /* Set the completion timer timeout to the maximum 32ms. */
248 data = pci_read_reg(chan, SH4A_PCIETLCTLR);
251 pci_write_reg(chan, data, SH4A_PCIETLCTLR);
254 * Set fast training sequences to the maximum 255,
255 * and enable MAC data scrambling.
257 data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
258 data &= ~PCIEMACCTLR_SCR_DIS;
259 data |= (0xff << 16);
260 pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
262 memphys = __pa(memory_start);
263 memsize = roundup_pow_of_two(memory_end - memory_start);
266 * If there's more than 512MB of memory, we need to roll over to
269 if (memsize > SZ_512M) {
270 __raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1);
271 __raw_writel(((memsize - SZ_512M) - SZ_256) | 1,
272 chan->reg_base + SH4A_PCIELAMR1);
276 * Otherwise just zero it out and disable it.
278 __raw_writel(0, chan->reg_base + SH4A_PCIELAR1);
279 __raw_writel(0, chan->reg_base + SH4A_PCIELAMR1);
283 * LAR0/LAMR0 covers up to the first 512MB, which is enough to
284 * cover all of lowmem on most platforms.
286 __raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);
287 __raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0);
289 /* Finish initialization */
290 data = pci_read_reg(chan, SH4A_PCIETCTLR);
292 pci_write_reg(chan, data, SH4A_PCIETCTLR);
294 /* Enable DL_Active Interrupt generation */
295 data = pci_read_reg(chan, SH4A_PCIEDLINTENR);
296 data |= PCIEDLINTENR_DLL_ACT_ENABLE;
297 pci_write_reg(chan, data, SH4A_PCIEDLINTENR);
299 /* Disable MAC data scrambling. */
300 data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
301 data |= PCIEMACCTLR_SCR_DIS | (0xff << 16);
302 pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
304 ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL);
305 if (unlikely(ret != 0))
308 data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
309 data &= ~(PCI_STATUS_DEVSEL_MASK << 16);
310 data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
311 (PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST) << 16;
312 pci_write_reg(chan, data, SH4A_PCIEPCICONF1);
314 pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);
315 pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);
319 data = pci_read_reg(chan, SH4A_PCIEMACSR);
320 printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
321 port->index, (data >> 20) & 0x3f);
324 for (i = 0; i < chan->nr_resources; i++) {
325 struct resource *res = chan->resources + i;
326 resource_size_t size;
329 pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(i));
331 size = resource_size(res);
334 * The PAMR mask is calculated in units of 256kB, which
335 * keeps things pretty simple.
337 __raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
338 chan->reg_base + SH4A_PCIEPAMR(i));
340 pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(i));
341 pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL(i));
343 enable_mask = MASK_PARE;
344 if (res->flags & IORESOURCE_IO)
345 enable_mask |= MASK_SPC;
347 pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(i));
353 int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
358 static int sh7786_pcie_core_init(void)
360 /* Return the number of ports */
361 return test_mode_pin(MODE_PIN12) ? 3 : 2;
364 static int __devinit sh7786_pcie_init_hw(struct sh7786_pcie_port *port)
368 ret = phy_init(port->hose);
369 if (unlikely(ret < 0))
373 * Check if we are configured in endpoint or root complex mode,
374 * this is a fixed pin setting that applies to all PCIe ports.
376 port->endpoint = test_mode_pin(MODE_PIN11);
378 ret = pcie_init(port);
379 if (unlikely(ret < 0))
382 return register_pci_controller(port->hose);
385 static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
386 .core_init = sh7786_pcie_core_init,
387 .port_init_hw = sh7786_pcie_init_hw,
390 static int __init sh7786_pcie_init(void)
394 printk(KERN_NOTICE "PCI: Starting intialization.\n");
396 sh7786_pcie_hwops = &sh7786_65nm_pcie_hwops;
398 nr_ports = sh7786_pcie_hwops->core_init();
399 BUG_ON(nr_ports > ARRAY_SIZE(sh7786_pci_channels));
401 if (unlikely(nr_ports == 0))
404 sh7786_pcie_ports = kzalloc(nr_ports * sizeof(struct sh7786_pcie_port),
406 if (unlikely(!sh7786_pcie_ports))
409 printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports);
411 for (i = 0; i < nr_ports; i++) {
412 struct sh7786_pcie_port *port = sh7786_pcie_ports + i;
415 port->hose = sh7786_pci_channels + i;
416 port->hose->io_map_base = port->hose->resources[0].start;
418 ret |= sh7786_pcie_hwops->port_init_hw(port);
426 arch_initcall(sh7786_pcie_init);