1 #ifndef __ASM_SH_CACHE_H
2 #define __ASM_SH_CACHE_H
4 #if defined(CONFIG_SH4)
6 int cache_control(unsigned int cmd);
8 #define L1_CACHE_BYTES 32
10 struct __large_struct { unsigned long buf[100]; };
11 #define __m(x) (*(struct __large_struct *)(x))
16 * 32-bytes is the largest L1 data cache line size for SH the architecture. So
17 * it is a safe default for DMA alignment.
19 #define ARCH_DMA_MINALIGN 32
21 #endif /* CONFIG_SH4 */
24 * Use the L1 data cache line size value for the minimum DMA buffer alignment
27 #ifndef ARCH_DMA_MINALIGN
28 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
31 #endif /* __ASM_SH_CACHE_H */