2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
4 * Copyright (C) 2007, 2008 Magnus Damm
6 * Based on intc2.c and ipr.c
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
11 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
12 * Copyright (C) 2005, 2006 Paul Mundt
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/module.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
25 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
26 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
27 ((addr_e) << 16) | ((addr_d << 24)))
29 #define _INTC_SHIFT(h) (h & 0x1f)
30 #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
31 #define _INTC_FN(h) ((h >> 9) & 0xf)
32 #define _INTC_MODE(h) ((h >> 13) & 0x7)
33 #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
34 #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
36 struct intc_handle_int {
41 struct intc_desc_int {
47 struct intc_handle_int *prio;
49 struct intc_handle_int *sense;
50 unsigned int nr_sense;
55 #define IS_SMP(x) x.smp
56 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
57 #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
60 #define INTC_REG(d, x, c) (d->reg[(x)])
61 #define SMP_NR(d, x) 1
64 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
65 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
66 static unsigned long ack_handle[NR_IRQS];
69 static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
71 struct irq_chip *chip = get_irq_chip(irq);
72 return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
75 static inline unsigned int set_field(unsigned int value,
76 unsigned int field_value,
79 unsigned int width = _INTC_WIDTH(handle);
80 unsigned int shift = _INTC_SHIFT(handle);
82 value &= ~(((1 << width) - 1) << shift);
83 value |= field_value << shift;
87 static void write_8(unsigned long addr, unsigned long h, unsigned long data)
89 ctrl_outb(set_field(0, data, h), addr);
92 static void write_16(unsigned long addr, unsigned long h, unsigned long data)
94 ctrl_outw(set_field(0, data, h), addr);
97 static void write_32(unsigned long addr, unsigned long h, unsigned long data)
99 ctrl_outl(set_field(0, data, h), addr);
102 static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
105 local_irq_save(flags);
106 ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
107 local_irq_restore(flags);
110 static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
113 local_irq_save(flags);
114 ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
115 local_irq_restore(flags);
118 static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
121 local_irq_save(flags);
122 ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
123 local_irq_restore(flags);
126 enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
128 static void (*intc_reg_fns[])(unsigned long addr,
130 unsigned long data) = {
131 [REG_FN_WRITE_BASE + 0] = write_8,
132 [REG_FN_WRITE_BASE + 1] = write_16,
133 [REG_FN_WRITE_BASE + 3] = write_32,
134 [REG_FN_MODIFY_BASE + 0] = modify_8,
135 [REG_FN_MODIFY_BASE + 1] = modify_16,
136 [REG_FN_MODIFY_BASE + 3] = modify_32,
139 enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
140 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
141 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
142 MODE_PRIO_REG, /* Priority value written to enable interrupt */
143 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
146 static void intc_mode_field(unsigned long addr,
147 unsigned long handle,
148 void (*fn)(unsigned long,
153 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
156 static void intc_mode_zero(unsigned long addr,
157 unsigned long handle,
158 void (*fn)(unsigned long,
166 static void intc_mode_prio(unsigned long addr,
167 unsigned long handle,
168 void (*fn)(unsigned long,
173 fn(addr, handle, intc_prio_level[irq]);
176 static void (*intc_enable_fns[])(unsigned long addr,
177 unsigned long handle,
178 void (*fn)(unsigned long,
181 unsigned int irq) = {
182 [MODE_ENABLE_REG] = intc_mode_field,
183 [MODE_MASK_REG] = intc_mode_zero,
184 [MODE_DUAL_REG] = intc_mode_field,
185 [MODE_PRIO_REG] = intc_mode_prio,
186 [MODE_PCLR_REG] = intc_mode_prio,
189 static void (*intc_disable_fns[])(unsigned long addr,
190 unsigned long handle,
191 void (*fn)(unsigned long,
194 unsigned int irq) = {
195 [MODE_ENABLE_REG] = intc_mode_zero,
196 [MODE_MASK_REG] = intc_mode_field,
197 [MODE_DUAL_REG] = intc_mode_field,
198 [MODE_PRIO_REG] = intc_mode_zero,
199 [MODE_PCLR_REG] = intc_mode_field,
202 static inline void _intc_enable(unsigned int irq, unsigned long handle)
204 struct intc_desc_int *d = get_intc_desc(irq);
208 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
209 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
210 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
211 [_INTC_FN(handle)], irq);
215 static void intc_enable(unsigned int irq)
217 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
220 static void intc_disable(unsigned int irq)
222 struct intc_desc_int *d = get_intc_desc(irq);
223 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
227 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
228 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
229 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
230 [_INTC_FN(handle)], irq);
234 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
235 static void intc_mask_ack(unsigned int irq)
237 struct intc_desc_int *d = get_intc_desc(irq);
238 unsigned long handle = ack_handle[irq];
243 /* read register and write zero only to the assocaited bit */
246 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
247 switch (_INTC_FN(handle)) {
248 case REG_FN_MODIFY_BASE + 0: /* 8bit */
250 ctrl_outb(0xff ^ set_field(0, 1, handle), addr);
252 case REG_FN_MODIFY_BASE + 1: /* 16bit */
254 ctrl_outw(0xffff ^ set_field(0, 1, handle), addr);
256 case REG_FN_MODIFY_BASE + 3: /* 32bit */
258 ctrl_outl(0xffffffff ^ set_field(0, 1, handle), addr);
268 static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
274 /* this doesn't scale well, but...
276 * this function should only be used for cerain uncommon
277 * operations such as intc_set_priority() and intc_set_sense()
278 * and in those rare cases performance doesn't matter that much.
279 * keeping the memory footprint low is more important.
281 * one rather simple way to speed this up and still keep the
282 * memory footprint down is to make sure the array is sorted
283 * and then perform a bisect to lookup the irq.
286 for (i = 0; i < nr_hp; i++) {
287 if ((hp + i)->irq != irq)
296 int intc_set_priority(unsigned int irq, unsigned int prio)
298 struct intc_desc_int *d = get_intc_desc(irq);
299 struct intc_handle_int *ihp;
301 if (!intc_prio_level[irq] || prio <= 1)
304 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
306 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
309 intc_prio_level[irq] = prio;
312 * only set secondary masking method directly
313 * primary masking method is using intc_prio_level[irq]
314 * priority level will be set during next enable()
317 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
318 _intc_enable(irq, ihp->handle);
323 #define VALID(x) (x | 0x80)
325 static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
326 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
327 [IRQ_TYPE_EDGE_RISING] = VALID(1),
328 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
329 /* SH7706, SH7707 and SH7709 do not support high level triggered */
330 #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
331 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
332 !defined(CONFIG_CPU_SUBTYPE_SH7709)
333 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
337 static int intc_set_sense(unsigned int irq, unsigned int type)
339 struct intc_desc_int *d = get_intc_desc(irq);
340 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
341 struct intc_handle_int *ihp;
347 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
349 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
350 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
355 static unsigned int __init intc_get_reg(struct intc_desc_int *d,
356 unsigned long address)
360 for (k = 0; k < d->nr_reg; k++) {
361 if (d->reg[k] == address)
369 static intc_enum __init intc_grp_id(struct intc_desc *desc,
372 struct intc_group *g = desc->groups;
375 for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
376 g = desc->groups + i;
378 for (j = 0; g->enum_ids[j]; j++) {
379 if (g->enum_ids[j] != enum_id)
389 static unsigned int __init intc_mask_data(struct intc_desc *desc,
390 struct intc_desc_int *d,
391 intc_enum enum_id, int do_grps)
393 struct intc_mask_reg *mr = desc->mask_regs;
394 unsigned int i, j, fn, mode;
395 unsigned long reg_e, reg_d;
397 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
398 mr = desc->mask_regs + i;
400 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
401 if (mr->enum_ids[j] != enum_id)
404 if (mr->set_reg && mr->clr_reg) {
405 fn = REG_FN_WRITE_BASE;
406 mode = MODE_DUAL_REG;
410 fn = REG_FN_MODIFY_BASE;
412 mode = MODE_ENABLE_REG;
416 mode = MODE_MASK_REG;
422 fn += (mr->reg_width >> 3) - 1;
423 return _INTC_MK(fn, mode,
424 intc_get_reg(d, reg_e),
425 intc_get_reg(d, reg_d),
427 (mr->reg_width - 1) - j);
432 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
437 static unsigned int __init intc_prio_data(struct intc_desc *desc,
438 struct intc_desc_int *d,
439 intc_enum enum_id, int do_grps)
441 struct intc_prio_reg *pr = desc->prio_regs;
442 unsigned int i, j, fn, mode, bit;
443 unsigned long reg_e, reg_d;
445 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
446 pr = desc->prio_regs + i;
448 for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
449 if (pr->enum_ids[j] != enum_id)
452 if (pr->set_reg && pr->clr_reg) {
453 fn = REG_FN_WRITE_BASE;
454 mode = MODE_PCLR_REG;
458 fn = REG_FN_MODIFY_BASE;
459 mode = MODE_PRIO_REG;
466 fn += (pr->reg_width >> 3) - 1;
468 BUG_ON((j + 1) * pr->field_width > pr->reg_width);
470 bit = pr->reg_width - ((j + 1) * pr->field_width);
472 return _INTC_MK(fn, mode,
473 intc_get_reg(d, reg_e),
474 intc_get_reg(d, reg_d),
475 pr->field_width, bit);
480 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
485 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
486 static unsigned int __init intc_ack_data(struct intc_desc *desc,
487 struct intc_desc_int *d,
490 struct intc_mask_reg *mr = desc->ack_regs;
491 unsigned int i, j, fn, mode;
492 unsigned long reg_e, reg_d;
494 for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
495 mr = desc->ack_regs + i;
497 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
498 if (mr->enum_ids[j] != enum_id)
501 fn = REG_FN_MODIFY_BASE;
502 mode = MODE_ENABLE_REG;
506 fn += (mr->reg_width >> 3) - 1;
507 return _INTC_MK(fn, mode,
508 intc_get_reg(d, reg_e),
509 intc_get_reg(d, reg_d),
511 (mr->reg_width - 1) - j);
519 static unsigned int __init intc_sense_data(struct intc_desc *desc,
520 struct intc_desc_int *d,
523 struct intc_sense_reg *sr = desc->sense_regs;
524 unsigned int i, j, fn, bit;
526 for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
527 sr = desc->sense_regs + i;
529 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
530 if (sr->enum_ids[j] != enum_id)
533 fn = REG_FN_MODIFY_BASE;
534 fn += (sr->reg_width >> 3) - 1;
536 BUG_ON((j + 1) * sr->field_width > sr->reg_width);
538 bit = sr->reg_width - ((j + 1) * sr->field_width);
540 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
541 0, sr->field_width, bit);
548 static void __init intc_register_irq(struct intc_desc *desc,
549 struct intc_desc_int *d,
553 struct intc_handle_int *hp;
554 unsigned int data[2], primary;
556 /* Prefer single interrupt source bitmap over other combinations:
557 * 1. bitmap, single interrupt source
558 * 2. priority, single interrupt source
559 * 3. bitmap, multiple interrupt sources (groups)
560 * 4. priority, multiple interrupt sources (groups)
563 data[0] = intc_mask_data(desc, d, enum_id, 0);
564 data[1] = intc_prio_data(desc, d, enum_id, 0);
567 if (!data[0] && data[1])
570 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
571 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
576 BUG_ON(!data[primary]); /* must have primary masking method */
578 disable_irq_nosync(irq);
579 set_irq_chip_and_handler_name(irq, &d->chip,
580 handle_level_irq, "level");
581 set_irq_chip_data(irq, (void *)data[primary]);
583 /* set priority level
584 * - this needs to be at least 2 for 5-bit priorities on 7780
586 intc_prio_level[irq] = 2;
588 /* enable secondary masking method if present */
590 _intc_enable(irq, data[!primary]);
592 /* add irq to d->prio list if priority is available */
594 hp = d->prio + d->nr_prio;
596 hp->handle = data[1];
600 * only secondary priority should access registers, so
601 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
604 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
605 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
610 /* add irq to d->sense list if sense is available */
611 data[0] = intc_sense_data(desc, d, enum_id);
613 (d->sense + d->nr_sense)->irq = irq;
614 (d->sense + d->nr_sense)->handle = data[0];
618 /* irq should be disabled by default */
621 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
623 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
627 static unsigned int __init save_reg(struct intc_desc_int *d,
644 void __init register_intc_controller(struct intc_desc *desc)
646 unsigned int i, k, smp;
647 struct intc_desc_int *d;
649 d = alloc_bootmem(sizeof(*d));
651 d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
652 d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
653 d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
655 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
656 d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
658 d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
660 d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp));
664 if (desc->mask_regs) {
665 for (i = 0; i < desc->nr_mask_regs; i++) {
666 smp = IS_SMP(desc->mask_regs[i]);
667 k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
668 k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
672 if (desc->prio_regs) {
673 d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
675 for (i = 0; i < desc->nr_prio_regs; i++) {
676 smp = IS_SMP(desc->prio_regs[i]);
677 k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
678 k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
682 if (desc->sense_regs) {
683 d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
685 for (i = 0; i < desc->nr_sense_regs; i++) {
686 k += save_reg(d, k, desc->sense_regs[i].reg, 0);
690 d->chip.name = desc->name;
691 d->chip.mask = intc_disable;
692 d->chip.unmask = intc_enable;
693 d->chip.mask_ack = intc_disable;
694 d->chip.set_type = intc_set_sense;
696 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
697 if (desc->ack_regs) {
698 for (i = 0; i < desc->nr_ack_regs; i++)
699 k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
701 d->chip.mask_ack = intc_mask_ack;
705 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
707 for (i = 0; i < desc->nr_vectors; i++) {
708 struct intc_vect *vect = desc->vectors + i;
710 intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));