2 * arch/sh/kernel/cpu/sh2a/ubc.c
4 * On-chip UBC support for SH-2A CPUs.
6 * Copyright (C) 2009 - 2010 Paul Mundt
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/init.h>
13 #include <linux/err.h>
14 #include <linux/clk.h>
16 #include <asm/hw_breakpoint.h>
18 #define UBC_BAR(idx) (0xfffc0400 + (0x10 * idx))
19 #define UBC_BAMR(idx) (0xfffc0404 + (0x10 * idx))
20 #define UBC_BBR(idx) (0xfffc04A0 + (0x10 * idx))
21 #define UBC_BDR(idx) (0xfffc0408 + (0x10 * idx))
22 #define UBC_BDMR(idx) (0xfffc040C + (0x10 * idx))
24 #define UBC_BRCR 0xfffc04C0
27 #define UBC_BBR_UBID (1 << 13) /* User Break Interrupt Disable */
28 #define UBC_BBR_DBE (1 << 12) /* Data Break Enable */
29 #define UBC_BBR_CD_C (1 << 6) /* C Bus Cycle */
30 #define UBC_BBR_CD_I (2 << 6) /* I Bus Cycle */
31 #define UBC_BBR_ID_I (1 << 4) /* Break Condition is instruction fetch cycle */
32 #define UBC_BBR_ID_D (2 << 4) /* Break Condition is data access cycle */
33 #define UBC_BBR_ID_ID (3 << 4) /* Break Condition is instruction fetch or data access cycle */
35 #define UBC_CRR_BIE (1 << 0)
38 #define UBC_CBR_CE (1 << 0)
40 static struct sh_ubc sh2a_ubc;
42 static void sh2a_ubc_enable(struct arch_hw_breakpoint *info, int idx)
44 __raw_writel(UBC_BBR_DBE | UBC_BBR_CD_C | UBC_BBR_ID_ID |
45 info->len | info->type, UBC_BBR(idx));
46 __raw_writel(info->address, UBC_BAR(idx));
49 static void sh2a_ubc_disable(struct arch_hw_breakpoint *info, int idx)
51 __raw_writel(UBC_BBR_UBID, UBC_BBR(idx));
52 __raw_writel(0, UBC_BAR(idx));
55 static void sh2a_ubc_enable_all(unsigned long mask)
59 for (i = 0; i < sh2a_ubc.num_events; i++)
61 __raw_writel(__raw_readl(UBC_BBR(i)) & ~UBC_BBR_UBID,
65 static void sh2a_ubc_disable_all(void)
69 for (i = 0; i < sh2a_ubc.num_events; i++)
70 __raw_writel(__raw_readl(UBC_BBR(i)) | UBC_BBR_UBID,
74 static unsigned long sh2a_ubc_active_mask(void)
76 unsigned long active = 0;
79 for (i = 0; i < sh2a_ubc.num_events; i++)
80 if (!(__raw_readl(UBC_BBR(i)) & UBC_BBR_UBID))
86 static unsigned long sh2a_ubc_triggered_mask(void)
88 unsigned int ret, mask;
91 ret = __raw_readl(UBC_BRCR);
92 if ((ret & (1 << 15)) || (ret & (1 << 13))) {
93 mask |= (1 << 0); /* Match condition for channel 0 */
97 if ((ret & (1 << 14)) || (ret & (1 << 12))) {
98 mask |= (1 << 1); /* Match condition for channel 1 */
105 static void sh2a_ubc_clear_triggered_mask(unsigned long mask)
107 if (mask & (1 << 0)) /* Channel 0 statisfied break condition */
108 __raw_writel(__raw_readl(UBC_BRCR) &
109 ~((1 << 15) | (1 << 13)), UBC_BRCR);
111 if (mask & (1 << 1)) /* Channel 1 statisfied break condition */
112 __raw_writel(__raw_readl(UBC_BRCR) &
113 ~((1 << 14) | (1 << 12)), UBC_BRCR);
116 static struct sh_ubc sh2a_ubc = {
120 .enable = sh2a_ubc_enable,
121 .disable = sh2a_ubc_disable,
122 .enable_all = sh2a_ubc_enable_all,
123 .disable_all = sh2a_ubc_disable_all,
124 .active_mask = sh2a_ubc_active_mask,
125 .triggered_mask = sh2a_ubc_triggered_mask,
126 .clear_triggered_mask = sh2a_ubc_clear_triggered_mask,
129 static int __init sh2a_ubc_init(void)
131 struct clk *ubc_iclk = clk_get(NULL, "ubc0");
135 * The UBC MSTP bit is optional, as not all platforms will have
136 * it. Just ignore it if we can't find it.
138 if (IS_ERR(ubc_iclk))
141 clk_enable(ubc_iclk);
143 for (i = 0; i < sh2a_ubc.num_events; i++) {
144 __raw_writel(0, UBC_BAMR(i));
145 __raw_writel(0, UBC_BBR(i));
148 clk_disable(ubc_iclk);
150 sh2a_ubc.clk = ubc_iclk;
152 return register_sh_ubc(&sh2a_ubc);
154 arch_initcall(sh2a_ubc_init);