2 * SH3 Setup code for SH7706, SH7707, SH7708, SH7709
4 * Copyright (C) 2007 Magnus Damm
6 * Based on setup-sh7709.c
8 * Copyright (C) 2006 Paul Mundt
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/init.h>
16 #include <linux/irq.h>
17 #include <linux/platform_device.h>
18 #include <linux/serial.h>
24 /* interrupt sources */
25 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
27 DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3,
28 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
29 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
30 SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI,
33 TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
34 RTC_ATI, RTC_PRI, RTC_CUI,
38 /* interrupt groups */
39 RTC, REF, TMU2, DMAC, SCI, SCIF2, SCIF0,
42 static struct intc_vect vectors[] = {
43 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
44 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
45 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
46 INTC_VECT(RTC_CUI, 0x4c0),
47 INTC_VECT(SCI_ERI, 0x4e0), INTC_VECT(SCI_RXI, 0x500),
48 INTC_VECT(SCI_TXI, 0x520), INTC_VECT(SCI_TEI, 0x540),
49 INTC_VECT(WDT, 0x560),
50 INTC_VECT(REF_RCMI, 0x580),
51 INTC_VECT(REF_ROVI, 0x5a0),
52 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
53 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
54 defined(CONFIG_CPU_SUBTYPE_SH7709)
55 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
56 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
57 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
58 INTC_VECT(ADC_ADI, 0x980),
59 INTC_VECT(SCIF2_ERI, 0x900), INTC_VECT(SCIF2_RXI, 0x920),
60 INTC_VECT(SCIF2_BRI, 0x940), INTC_VECT(SCIF2_TXI, 0x960),
62 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
63 defined(CONFIG_CPU_SUBTYPE_SH7709)
64 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
65 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
66 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
68 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
69 INTC_VECT(LCDC, 0x9a0),
70 INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0),
74 static struct intc_group groups[] = {
75 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
76 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
77 INTC_GROUP(REF, REF_RCMI, REF_ROVI),
78 INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
79 INTC_GROUP(SCI, SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI),
80 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
81 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
84 static struct intc_prio priorities[] = {
91 static struct intc_prio_reg prio_registers[] = {
92 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
93 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
94 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
95 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
96 defined(CONFIG_CPU_SUBTYPE_SH7709)
97 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
98 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
99 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
101 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
102 defined(CONFIG_CPU_SUBTYPE_SH7709)
103 { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
104 { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
106 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
107 { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
111 static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, groups,
112 priorities, NULL, prio_registers, NULL);
114 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
115 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
116 defined(CONFIG_CPU_SUBTYPE_SH7709)
117 static struct intc_vect vectors_irq[] = {
118 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
119 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
122 static DECLARE_INTC_DESC(intc_desc_irq, "sh770x-irq", vectors_irq, NULL,
123 priorities, NULL, prio_registers, NULL);
126 static struct resource rtc_resources[] = {
129 .end = 0xfffffec0 + 0x1e,
130 .flags = IORESOURCE_IO,
134 .flags = IORESOURCE_IRQ,
138 .flags = IORESOURCE_IRQ,
142 .flags = IORESOURCE_IRQ,
146 static struct platform_device rtc_device = {
149 .num_resources = ARRAY_SIZE(rtc_resources),
150 .resource = rtc_resources,
153 static struct plat_sci_port sci_platform_data[] = {
155 .mapbase = 0xfffffe80,
156 .flags = UPF_BOOT_AUTOCONF,
158 .irqs = { 23, 24, 25, 0 },
160 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
161 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
162 defined(CONFIG_CPU_SUBTYPE_SH7709)
164 .mapbase = 0xa4000150,
165 .flags = UPF_BOOT_AUTOCONF,
167 .irqs = { 56, 57, 59, 58 },
170 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
171 defined(CONFIG_CPU_SUBTYPE_SH7709)
173 .mapbase = 0xa4000140,
174 .flags = UPF_BOOT_AUTOCONF,
176 .irqs = { 52, 53, 55, 54 },
184 static struct platform_device sci_device = {
188 .platform_data = sci_platform_data,
192 static struct platform_device *sh770x_devices[] __initdata = {
197 static int __init sh770x_devices_setup(void)
199 return platform_add_devices(sh770x_devices,
200 ARRAY_SIZE(sh770x_devices));
202 __initcall(sh770x_devices_setup);
204 #define INTC_ICR1 0xa4000010UL
205 #define INTC_ICR1_IRQLVL (1<<14)
207 void __init plat_irq_setup_pins(int mode)
209 if (mode == IRQ_MODE_IRQ) {
210 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
211 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
212 defined(CONFIG_CPU_SUBTYPE_SH7709)
213 ctrl_outw(ctrl_inw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1);
214 register_intc_controller(&intc_desc_irq);
221 void __init plat_irq_setup(void)
223 register_intc_controller(&intc_desc);