2 * arch/sh/kernel/cpu/sh4/probe.c
4 * CPU Subtype Probing for SH-4.
6 * Copyright (C) 2001 - 2006 Paul Mundt
7 * Copyright (C) 2003 Richard Curnow
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
15 #include <linux/smp.h>
16 #include <asm/processor.h>
17 #include <asm/cache.h>
19 int __init detect_cpu_and_cache_system(void)
21 unsigned long pvr, prr, cvr;
24 static unsigned long sizes[16] = {
32 pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff;
33 prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
34 cvr = (ctrl_inl(CCN_CVR));
37 * Setup some sane SH-4 defaults for the icache
39 current_cpu_data.icache.way_incr = (1 << 13);
40 current_cpu_data.icache.entry_shift = 5;
41 current_cpu_data.icache.sets = 256;
42 current_cpu_data.icache.ways = 1;
43 current_cpu_data.icache.linesz = L1_CACHE_BYTES;
46 * And again for the dcache ..
48 current_cpu_data.dcache.way_incr = (1 << 14);
49 current_cpu_data.dcache.entry_shift = 5;
50 current_cpu_data.dcache.sets = 512;
51 current_cpu_data.dcache.ways = 1;
52 current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
55 * Setup some generic flags we can probe
56 * (L2 and DSP detection only work on SH-4A)
58 if (((pvr >> 16) & 0xff) == 0x10) {
59 if ((cvr & 0x02000000) == 0)
60 current_cpu_data.flags |= CPU_HAS_L2_CACHE;
61 if ((cvr & 0x10000000) == 0)
62 current_cpu_data.flags |= CPU_HAS_DSP;
64 current_cpu_data.flags |= CPU_HAS_LLSC;
67 /* FPU detection works for everyone */
68 if ((cvr & 0x20000000) == 1)
69 current_cpu_data.flags |= CPU_HAS_FPU;
71 /* Mask off the upper chip ID */
75 * Probe the underlying processor version/revision and
76 * adjust cpu_data setup accordingly.
80 current_cpu_data.type = CPU_SH7750;
81 current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
85 current_cpu_data.type = CPU_SH7750S;
86 current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
90 current_cpu_data.type = CPU_SH7751;
91 current_cpu_data.flags |= CPU_HAS_FPU;
95 current_cpu_data.type = CPU_SH7770;
96 current_cpu_data.icache.ways = 4;
97 current_cpu_data.dcache.ways = 4;
99 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
104 current_cpu_data.type = CPU_SH7781;
106 current_cpu_data.type = CPU_SH7780;
108 current_cpu_data.icache.ways = 4;
109 current_cpu_data.dcache.ways = 4;
111 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
117 current_cpu_data.type = CPU_SH7343;
118 current_cpu_data.icache.ways = 4;
119 current_cpu_data.dcache.ways = 4;
120 current_cpu_data.flags |= CPU_HAS_LLSC;
124 current_cpu_data.type = CPU_SH7785;
125 current_cpu_data.icache.ways = 4;
126 current_cpu_data.dcache.ways = 4;
127 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
132 current_cpu_data.type = CPU_SH7722;
133 current_cpu_data.icache.ways = 4;
134 current_cpu_data.dcache.ways = 4;
135 current_cpu_data.flags |= CPU_HAS_LLSC;
138 case 0x4000: /* 1st cut */
139 case 0x4001: /* 2nd cut */
140 current_cpu_data.type = CPU_SHX3;
141 current_cpu_data.icache.ways = 4;
142 current_cpu_data.dcache.ways = 4;
143 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
147 current_cpu_data.type = CPU_ST40RA;
148 current_cpu_data.flags |= CPU_HAS_FPU;
151 current_cpu_data.type = CPU_ST40GX1;
152 current_cpu_data.flags |= CPU_HAS_FPU;
155 current_cpu_data.type = CPU_SH4_501;
156 current_cpu_data.icache.ways = 2;
157 current_cpu_data.dcache.ways = 2;
160 current_cpu_data.type = CPU_SH4_202;
161 current_cpu_data.icache.ways = 2;
162 current_cpu_data.dcache.ways = 2;
163 current_cpu_data.flags |= CPU_HAS_FPU;
165 case 0x500 ... 0x501:
168 current_cpu_data.type = CPU_SH7750R;
171 current_cpu_data.type = CPU_SH7751R;
174 current_cpu_data.type = CPU_SH7760;
178 current_cpu_data.icache.ways = 2;
179 current_cpu_data.dcache.ways = 2;
181 current_cpu_data.flags |= CPU_HAS_FPU;
185 current_cpu_data.type = CPU_SH_NONE;
189 #ifdef CONFIG_SH_DIRECT_MAPPED
190 current_cpu_data.icache.ways = 1;
191 current_cpu_data.dcache.ways = 1;
194 #ifdef CONFIG_CPU_HAS_PTEA
195 current_cpu_data.flags |= CPU_HAS_PTEA;
199 * On anything that's not a direct-mapped cache, look to the CVR
200 * for I/D-cache specifics.
202 if (current_cpu_data.icache.ways > 1) {
203 size = sizes[(cvr >> 20) & 0xf];
204 current_cpu_data.icache.way_incr = (size >> 1);
205 current_cpu_data.icache.sets = (size >> 6);
209 /* And the rest of the D-cache */
210 if (current_cpu_data.dcache.ways > 1) {
211 size = sizes[(cvr >> 16) & 0xf];
212 current_cpu_data.dcache.way_incr = (size >> 1);
213 current_cpu_data.dcache.sets = (size >> 6);
217 * Setup the L2 cache desc
219 * SH-4A's have an optional PIPT L2.
221 if (current_cpu_data.flags & CPU_HAS_L2_CACHE) {
223 * Size calculation is much more sensible
224 * than it is for the L1.
226 * Sizes are 128KB, 258KB, 512KB, and 1MB.
228 size = (cvr & 0xf) << 17;
232 current_cpu_data.scache.way_incr = (1 << 16);
233 current_cpu_data.scache.entry_shift = 5;
234 current_cpu_data.scache.ways = 4;
235 current_cpu_data.scache.linesz = L1_CACHE_BYTES;
237 current_cpu_data.scache.entry_mask =
238 (current_cpu_data.scache.way_incr -
239 current_cpu_data.scache.linesz);
241 current_cpu_data.scache.sets = size /
242 (current_cpu_data.scache.linesz *
243 current_cpu_data.scache.ways);
245 current_cpu_data.scache.way_size =
246 (current_cpu_data.scache.sets *
247 current_cpu_data.scache.linesz);