2 * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
4 * SH7343, SH7722, SH7723 & SH7366 support for the clock framework
6 * Copyright (c) 2006-2007 Nomad Global Solutions Inc
7 * Based on code for sh7343 by Paul Mundt
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
14 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/stringify.h>
18 #include <asm/clock.h>
23 #define ROUND_NEAREST 0
27 static int adjust_algos[][3] = {
29 { NM, N, 1 }, /* N:1, N:1 */
30 { 3, 2, 2 }, /* 3:2:2 */
31 { 5, 2, 2 }, /* 5:2:2 */
32 { N, 1, 1 }, /* N:1:1 */
44 static unsigned long adjust_pair_of_clocks(unsigned long r1, unsigned long r2,
45 int m1, int m2, int round_flag)
47 unsigned long rem, div;
50 pr_debug( "Actual values: r1 = %ld\n", r1);
51 pr_debug( "...............r2 = %ld\n", r2);
55 pr_debug( "setting equal rates: r2 now %ld\n", r2);
56 } else if ((m2 == N && m1 == 1) ||
57 (m2 == NM && m1 == N)) { /* N:1 or NM:N */
58 pr_debug( "Setting rates as 1:N (N:N*M)\n");
60 pr_debug( "...remainder = %ld\n", rem);
63 pr_debug( "...div = %ld\n", div);
66 the_one = rem >= r1/2 ? 1 : 0; break;
73 r2 = r1 * (div + the_one);
74 pr_debug( "...setting r2 to %ld\n", r2);
76 } else if ((m2 == 1 && m1 == N) ||
77 (m2 == N && m1 == NM)) { /* 1:N or N:NM */
78 pr_debug( "Setting rates as N:1 (N*M:N)\n");
80 pr_debug( "...remainder = %ld\n", rem);
83 pr_debug( "...div = %ld\n", div);
86 the_one = rem > r2/2 ? 1 : 0; break;
93 r2 = r1 / (div + the_one);
94 pr_debug( "...setting r2 to %ld\n", r2);
96 } else { /* value:value */
97 pr_debug( "Setting rates as %d:%d\n", m1, m2);
100 pr_debug( "...div = %ld\n", div);
101 pr_debug( "...setting r2 to %ld\n", r2);
107 static void adjust_clocks(int originate, int *l, unsigned long v[],
112 pr_debug( "Go down from %d...\n", originate);
113 /* go up recalculation clocks */
114 for (x = originate; x>0; x -- )
115 v[x-1] = adjust_pair_of_clocks(v[x], v[x-1],
119 pr_debug( "Go up from %d...\n", originate);
120 /* go down recalculation clocks */
121 for (x = originate; x<n_in_line - 1; x ++ )
122 v[x+1] = adjust_pair_of_clocks(v[x], v[x+1],
129 * SH7722 uses a common set of multipliers and divisors, so this
134 * Instead of having two separate multipliers/divisors set, like this:
136 * static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
137 * static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
139 * I created the divisors2 array, which is used to calculate rate like
140 * rate = parent * 2 / divisors2[ divisor ];
142 static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
144 static void master_clk_recalc(struct clk *clk)
146 unsigned frqcr = ctrl_inl(FRQCR);
148 clk->rate = CONFIG_SH_PCLK_FREQ * (((frqcr >> 24) & 0x1f) + 1);
151 static void master_clk_init(struct clk *clk)
154 clk->flags |= CLK_RATE_PROPAGATES;
155 clk->rate = CONFIG_SH_PCLK_FREQ;
156 master_clk_recalc(clk);
160 static void module_clk_recalc(struct clk *clk)
162 unsigned long frqcr = ctrl_inl(FRQCR);
164 clk->rate = clk->parent->rate / (((frqcr >> 24) & 0x1f) + 1);
167 static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
169 int div = rate / clk->rate;
170 int master_divs[] = { 2, 3, 4, 6, 8, 16 };
174 for (index = 1; index < ARRAY_SIZE(master_divs); index++)
175 if (div >= master_divs[index - 1] && div < master_divs[index])
178 if (index >= ARRAY_SIZE(master_divs))
179 index = ARRAY_SIZE(master_divs);
180 div = master_divs[index - 1];
182 frqcr = ctrl_inl(FRQCR);
183 frqcr &= ~(0xF << 24);
184 frqcr |= ( (div-1) << 24);
185 ctrl_outl(frqcr, FRQCR);
190 static struct clk_ops sh7722_master_clk_ops = {
191 .init = master_clk_init,
192 .recalc = master_clk_recalc,
193 .set_rate = master_clk_setrate,
196 static struct clk_ops sh7722_module_clk_ops = {
197 .recalc = module_clk_recalc,
200 struct frqcr_context {
205 struct frqcr_context sh7722_get_clk_context(const char *name)
207 struct frqcr_context ctx = { 0, };
209 if (!strcmp(name, "peripheral_clk")) {
212 } else if (!strcmp(name, "sdram_clk")) {
215 } else if (!strcmp(name, "bus_clk")) {
218 } else if (!strcmp(name, "sh_clk")) {
221 } else if (!strcmp(name, "umem_clk")) {
224 } else if (!strcmp(name, "cpu_clk")) {
232 * sh7722_find_div_index - find divisor for setting rate
234 * All sh7722 clocks use the same set of multipliers/divisors. This function
235 * chooses correct divisor to set the rate of clock with parent clock that
236 * generates frequency of 'parent_rate'
238 * @parent_rate: rate of parent clock
239 * @rate: requested rate to be set
241 static int sh7722_find_div_index(unsigned long parent_rate, unsigned rate)
243 unsigned div2 = parent_rate * 2 / rate;
246 if (rate > parent_rate)
249 for (index = 1; index < ARRAY_SIZE(divisors2); index++) {
250 if (div2 > divisors2[index - 1] && div2 <= divisors2[index])
253 if (index >= ARRAY_SIZE(divisors2))
254 index = ARRAY_SIZE(divisors2) - 1;
258 static void sh7722_frqcr_recalc(struct clk *clk)
260 struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
261 unsigned long frqcr = ctrl_inl(FRQCR);
264 index = (frqcr >> ctx.shift) & ctx.mask;
265 clk->rate = clk->parent->rate * 2 / divisors2[index];
268 static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate,
271 struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
272 unsigned long parent_rate = clk->parent->rate;
278 if (parent_rate < rate)
281 /* look for multiplier/divisor pair */
282 div = sh7722_find_div_index(parent_rate, rate);
286 /* calculate new value of clock rate */
287 clk->rate = parent_rate * 2 / divisors2[div];
288 frqcr = ctrl_inl(FRQCR);
290 /* FIXME: adjust as algo_id specifies */
291 if (algo_id != NO_CHANGE) {
293 char *algo_group_1[] = { "cpu_clk", "umem_clk", "sh_clk" };
294 char *algo_group_2[] = { "sh_clk", "bus_clk" };
295 char *algo_group_3[] = { "sh_clk", "sdram_clk" };
296 char *algo_group_4[] = { "bus_clk", "peripheral_clk" };
297 char *algo_group_5[] = { "cpu_clk", "peripheral_clk" };
298 char **algo_current = NULL;
299 /* 3 is the maximum number of clocks in relation */
301 unsigned long values[3]; /* the same comment as above */
302 int part_length = -1;
306 * all the steps below only required if adjustion was
309 if (algo_id == IUS_N1_N1 ||
310 algo_id == IUS_322 ||
311 algo_id == IUS_522 ||
312 algo_id == IUS_N11) {
313 algo_current = algo_group_1;
316 if (algo_id == SB_N1) {
317 algo_current = algo_group_2;
320 if (algo_id == SB3_N1 ||
324 algo_current = algo_group_3;
327 if (algo_id == BP_N1) {
328 algo_current = algo_group_4;
331 if (algo_id == IP_N1) {
332 algo_current = algo_group_5;
336 goto incorrect_algo_id;
339 for (i = 0; i < part_length; i ++ ) {
340 if (originator >= 0 && !strcmp(clk->name,
343 ck[i] = clk_get(NULL, algo_current[i]);
344 values[i] = clk_get_rate(ck[i]);
348 adjust_clocks(originator, adjust_algos[algo_id],
349 values, part_length);
351 for (i = 0; i < part_length; i ++ ) {
352 struct frqcr_context part_ctx;
356 part_div = sh7722_find_div_index(parent_rate,
359 part_ctx = sh7722_get_clk_context(
361 frqcr &= ~(part_ctx.mask <<
363 frqcr |= part_div << part_ctx.shift;
368 ck[i]->ops->recalc(ck[i]);
373 /* was there any error during recalculation ? If so, bail out.. */
374 if (unlikely(err!=0))
377 /* clear FRQCR bits */
378 frqcr &= ~(ctx.mask << ctx.shift);
379 frqcr |= div << ctx.shift;
381 /* ...and perform actual change */
382 ctrl_outl(frqcr, FRQCR);
391 static long sh7722_frqcr_round_rate(struct clk *clk, unsigned long rate)
393 unsigned long parent_rate = clk->parent->rate;
396 /* look for multiplier/divisor pair */
397 div = sh7722_find_div_index(parent_rate, rate);
401 /* calculate new value of clock rate */
402 return parent_rate * 2 / divisors2[div];
405 static struct clk_ops sh7722_frqcr_clk_ops = {
406 .recalc = sh7722_frqcr_recalc,
407 .set_rate = sh7722_frqcr_set_rate,
408 .round_rate = sh7722_frqcr_round_rate,
412 * clock ops methods for SIU A/B and IrDA clock
416 #ifndef CONFIG_CPU_SUBTYPE_SH7343
418 static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id)
423 r = ctrl_inl(clk->arch_flags);
424 div = sh7722_find_div_index(clk->parent->rate, rate);
427 r = (r & ~0xF) | div;
428 ctrl_outl(r, clk->arch_flags);
432 static void sh7722_siu_recalc(struct clk *clk)
436 r = ctrl_inl(clk->arch_flags);
437 clk->rate = clk->parent->rate * 2 / divisors2[r & 0xF];
440 static int sh7722_siu_start_stop(struct clk *clk, int enable)
444 r = ctrl_inl(clk->arch_flags);
446 ctrl_outl(r & ~(1 << 8), clk->arch_flags);
448 ctrl_outl(r | (1 << 8), clk->arch_flags);
452 static void sh7722_siu_enable(struct clk *clk)
454 sh7722_siu_start_stop(clk, 1);
457 static void sh7722_siu_disable(struct clk *clk)
459 sh7722_siu_start_stop(clk, 0);
462 static struct clk_ops sh7722_siu_clk_ops = {
463 .recalc = sh7722_siu_recalc,
464 .set_rate = sh7722_siu_set_rate,
465 .enable = sh7722_siu_enable,
466 .disable = sh7722_siu_disable,
469 #endif /* CONFIG_CPU_SUBTYPE_SH7343 */
471 static void sh7722_video_enable(struct clk *clk)
475 r = ctrl_inl(VCLKCR);
476 ctrl_outl( r & ~(1<<8), VCLKCR);
479 static void sh7722_video_disable(struct clk *clk)
483 r = ctrl_inl(VCLKCR);
484 ctrl_outl( r | (1<<8), VCLKCR);
487 static int sh7722_video_set_rate(struct clk *clk, unsigned long rate,
492 r = ctrl_inl(VCLKCR);
494 r |= ((clk->parent->rate / rate - 1) & 0x3F);
495 ctrl_outl(r, VCLKCR);
499 static void sh7722_video_recalc(struct clk *clk)
503 r = ctrl_inl(VCLKCR);
504 clk->rate = clk->parent->rate / ((r & 0x3F) + 1);
507 static struct clk_ops sh7722_video_clk_ops = {
508 .recalc = sh7722_video_recalc,
509 .set_rate = sh7722_video_set_rate,
510 .enable = sh7722_video_enable,
511 .disable = sh7722_video_disable,
514 * and at last, clock definitions themselves
516 static struct clk sh7722_umem_clock = {
518 .ops = &sh7722_frqcr_clk_ops,
519 .flags = CLK_RATE_PROPAGATES,
522 static struct clk sh7722_sh_clock = {
524 .ops = &sh7722_frqcr_clk_ops,
525 .flags = CLK_RATE_PROPAGATES,
528 static struct clk sh7722_peripheral_clock = {
529 .name = "peripheral_clk",
530 .ops = &sh7722_frqcr_clk_ops,
531 .flags = CLK_RATE_PROPAGATES,
534 static struct clk sh7722_sdram_clock = {
536 .ops = &sh7722_frqcr_clk_ops,
539 static struct clk sh7722_r_clock = {
542 .flags = CLK_RATE_PROPAGATES,
545 #ifndef CONFIG_CPU_SUBTYPE_SH7343
548 * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops
549 * methods of clk_ops determine which register they should access by
550 * examining clk->name field
552 static struct clk sh7722_siu_a_clock = {
554 .arch_flags = SCLKACR,
555 .ops = &sh7722_siu_clk_ops,
558 static struct clk sh7722_siu_b_clock = {
560 .arch_flags = SCLKBCR,
561 .ops = &sh7722_siu_clk_ops,
564 #if defined(CONFIG_CPU_SUBTYPE_SH7722)
565 static struct clk sh7722_irda_clock = {
567 .arch_flags = IrDACLKCR,
568 .ops = &sh7722_siu_clk_ops,
571 #endif /* CONFIG_CPU_SUBTYPE_SH7343 */
573 static struct clk sh7722_video_clock = {
575 .ops = &sh7722_video_clk_ops,
578 #define MSTPCR_ARCH_FLAGS(reg, bit) (((reg) << 8) | (bit))
579 #define MSTPCR_ARCH_FLAGS_REG(value) ((value) >> 8)
580 #define MSTPCR_ARCH_FLAGS_BIT(value) ((value) & 0xff)
582 static int sh7722_mstpcr_start_stop(struct clk *clk, int enable)
584 unsigned long bit = MSTPCR_ARCH_FLAGS_BIT(clk->arch_flags);
588 switch(MSTPCR_ARCH_FLAGS_REG(clk->arch_flags)) {
613 static void sh7722_mstpcr_enable(struct clk *clk)
615 sh7722_mstpcr_start_stop(clk, 1);
618 static void sh7722_mstpcr_disable(struct clk *clk)
620 sh7722_mstpcr_start_stop(clk, 0);
623 static void sh7722_mstpcr_recalc(struct clk *clk)
626 clk->rate = clk->parent->rate;
629 static struct clk_ops sh7722_mstpcr_clk_ops = {
630 .enable = sh7722_mstpcr_enable,
631 .disable = sh7722_mstpcr_disable,
632 .recalc = sh7722_mstpcr_recalc,
635 #define DECLARE_MSTPCRN(regnr, bitnr, bitstr) \
637 .name = "mstp" __stringify(regnr) bitstr, \
638 .arch_flags = MSTPCR_ARCH_FLAGS(regnr, bitnr), \
639 .ops = &sh7722_mstpcr_clk_ops, \
642 #define DECLARE_MSTPCR(regnr) \
643 DECLARE_MSTPCRN(regnr, 31, "31"), \
644 DECLARE_MSTPCRN(regnr, 30, "30"), \
645 DECLARE_MSTPCRN(regnr, 29, "29"), \
646 DECLARE_MSTPCRN(regnr, 28, "28"), \
647 DECLARE_MSTPCRN(regnr, 27, "27"), \
648 DECLARE_MSTPCRN(regnr, 26, "26"), \
649 DECLARE_MSTPCRN(regnr, 25, "25"), \
650 DECLARE_MSTPCRN(regnr, 24, "24"), \
651 DECLARE_MSTPCRN(regnr, 23, "23"), \
652 DECLARE_MSTPCRN(regnr, 22, "22"), \
653 DECLARE_MSTPCRN(regnr, 21, "21"), \
654 DECLARE_MSTPCRN(regnr, 20, "20"), \
655 DECLARE_MSTPCRN(regnr, 19, "19"), \
656 DECLARE_MSTPCRN(regnr, 18, "18"), \
657 DECLARE_MSTPCRN(regnr, 17, "17"), \
658 DECLARE_MSTPCRN(regnr, 16, "16"), \
659 DECLARE_MSTPCRN(regnr, 15, "15"), \
660 DECLARE_MSTPCRN(regnr, 14, "14"), \
661 DECLARE_MSTPCRN(regnr, 13, "13"), \
662 DECLARE_MSTPCRN(regnr, 12, "12"), \
663 DECLARE_MSTPCRN(regnr, 11, "11"), \
664 DECLARE_MSTPCRN(regnr, 10, "10"), \
665 DECLARE_MSTPCRN(regnr, 9, "09"), \
666 DECLARE_MSTPCRN(regnr, 8, "08"), \
667 DECLARE_MSTPCRN(regnr, 7, "07"), \
668 DECLARE_MSTPCRN(regnr, 6, "06"), \
669 DECLARE_MSTPCRN(regnr, 5, "05"), \
670 DECLARE_MSTPCRN(regnr, 4, "04"), \
671 DECLARE_MSTPCRN(regnr, 3, "03"), \
672 DECLARE_MSTPCRN(regnr, 2, "02"), \
673 DECLARE_MSTPCRN(regnr, 1, "01"), \
674 DECLARE_MSTPCRN(regnr, 0, "00")
676 static struct clk sh7722_mstpcr[] = {
682 #define MSTPCR(_name, _parent, regnr, bitnr) \
685 .arch_flags = MSTPCR_ARCH_FLAGS(regnr, bitnr), \
686 .ops = (void *)_parent, \
689 static struct clk sh7722_mstpcr_clocks[] = {
690 #if defined(CONFIG_CPU_SUBTYPE_SH7722)
691 MSTPCR("uram0", "umem_clk", 0, 28),
692 MSTPCR("xymem0", "bus_clk", 0, 26),
693 MSTPCR("tmu0", "peripheral_clk", 0, 15),
694 MSTPCR("cmt0", "r_clk", 0, 14),
695 MSTPCR("rwdt0", "r_clk", 0, 13),
696 MSTPCR("flctl0", "peripheral_clk", 0, 10),
697 MSTPCR("scif0", "peripheral_clk", 0, 7),
698 MSTPCR("scif1", "peripheral_clk", 0, 6),
699 MSTPCR("scif2", "peripheral_clk", 0, 5),
700 MSTPCR("i2c0", "peripheral_clk", 1, 9),
701 MSTPCR("rtc0", "r_clk", 1, 8),
702 MSTPCR("sdhi0", "peripheral_clk", 2, 18),
703 MSTPCR("keysc0", "r_clk", 2, 14),
704 MSTPCR("usbf0", "peripheral_clk", 2, 11),
705 MSTPCR("2dg0", "bus_clk", 2, 9),
706 MSTPCR("siu0", "bus_clk", 2, 8),
707 MSTPCR("vou0", "bus_clk", 2, 5),
708 MSTPCR("jpu0", "bus_clk", 2, 6),
709 MSTPCR("beu0", "bus_clk", 2, 4),
710 MSTPCR("ceu0", "bus_clk", 2, 3),
711 MSTPCR("veu0", "bus_clk", 2, 2),
712 MSTPCR("vpu0", "bus_clk", 2, 1),
713 MSTPCR("lcdc0", "bus_clk", 2, 0),
715 #if defined(CONFIG_CPU_SUBTYPE_SH7723)
716 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
717 MSTPCR("tlb0", "cpu_clk", 0, 31),
718 MSTPCR("ic0", "cpu_clk", 0, 30),
719 MSTPCR("oc0", "cpu_clk", 0, 29),
720 MSTPCR("l2c0", "sh_clk", 0, 28),
721 MSTPCR("ilmem0", "cpu_clk", 0, 27),
722 MSTPCR("fpu0", "cpu_clk", 0, 24),
723 MSTPCR("intc0", "cpu_clk", 0, 22),
724 MSTPCR("dmac0", "bus_clk", 0, 21),
725 MSTPCR("sh0", "sh_clk", 0, 20),
726 MSTPCR("hudi0", "peripheral_clk", 0, 19),
727 MSTPCR("ubc0", "cpu_clk", 0, 17),
728 MSTPCR("tmu0", "peripheral_clk", 0, 15),
729 MSTPCR("cmt0", "r_clk", 0, 14),
730 MSTPCR("rwdt0", "r_clk", 0, 13),
731 MSTPCR("dmac1", "bus_clk", 0, 12),
732 MSTPCR("tmu1", "peripheral_clk", 0, 11),
733 MSTPCR("flctl0", "peripheral_clk", 0, 10),
734 MSTPCR("scif0", "peripheral_clk", 0, 9),
735 MSTPCR("scif1", "peripheral_clk", 0, 8),
736 MSTPCR("scif2", "peripheral_clk", 0, 7),
737 MSTPCR("scif3", "bus_clk", 0, 6),
738 MSTPCR("scif4", "bus_clk", 0, 5),
739 MSTPCR("scif5", "bus_clk", 0, 4),
740 MSTPCR("msiof0", "bus_clk", 0, 2),
741 MSTPCR("msiof1", "bus_clk", 0, 1),
742 MSTPCR("meram0", "sh_clk", 0, 0),
743 MSTPCR("i2c0", "peripheral_clk", 1, 9),
744 MSTPCR("rtc0", "r_clk", 1, 8),
745 MSTPCR("atapi0", "sh_clk", 2, 28),
746 MSTPCR("adc0", "peripheral_clk", 2, 28),
747 MSTPCR("tpu0", "bus_clk", 2, 25),
748 MSTPCR("irda0", "peripheral_clk", 2, 24),
749 MSTPCR("tsif0", "bus_clk", 2, 22),
750 MSTPCR("icb0", "bus_clk", 2, 21),
751 MSTPCR("sdhi0", "bus_clk", 2, 18),
752 MSTPCR("sdhi1", "bus_clk", 2, 17),
753 MSTPCR("keysc0", "r_clk", 2, 14),
754 MSTPCR("usb0", "bus_clk", 2, 11),
755 MSTPCR("2dg0", "bus_clk", 2, 10),
756 MSTPCR("siu0", "bus_clk", 2, 8),
757 MSTPCR("veu1", "bus_clk", 2, 6),
758 MSTPCR("vou0", "bus_clk", 2, 5),
759 MSTPCR("beu0", "bus_clk", 2, 4),
760 MSTPCR("ceu0", "bus_clk", 2, 3),
761 MSTPCR("veu0", "bus_clk", 2, 2),
762 MSTPCR("vpu0", "bus_clk", 2, 1),
763 MSTPCR("lcdc0", "bus_clk", 2, 0),
765 #if defined(CONFIG_CPU_SUBTYPE_SH7343)
766 MSTPCR("uram0", "umem_clk", 0, 28),
767 MSTPCR("xymem0", "bus_clk", 0, 26),
768 MSTPCR("tmu0", "peripheral_clk", 0, 15),
769 MSTPCR("cmt0", "r_clk", 0, 14),
770 MSTPCR("rwdt0", "r_clk", 0, 13),
771 MSTPCR("scif0", "peripheral_clk", 0, 7),
772 MSTPCR("scif1", "peripheral_clk", 0, 6),
773 MSTPCR("scif2", "peripheral_clk", 0, 5),
774 MSTPCR("scif3", "peripheral_clk", 0, 4),
775 MSTPCR("i2c0", "peripheral_clk", 1, 9),
776 MSTPCR("i2c1", "peripheral_clk", 1, 8),
777 MSTPCR("sdhi0", "peripheral_clk", 2, 18),
778 MSTPCR("keysc0", "r_clk", 2, 14),
779 MSTPCR("usbf0", "peripheral_clk", 2, 11),
780 MSTPCR("siu0", "bus_clk", 2, 8),
781 MSTPCR("jpu0", "bus_clk", 2, 6),
782 MSTPCR("vou0", "bus_clk", 2, 5),
783 MSTPCR("beu0", "bus_clk", 2, 4),
784 MSTPCR("ceu0", "bus_clk", 2, 3),
785 MSTPCR("veu0", "bus_clk", 2, 2),
786 MSTPCR("vpu0", "bus_clk", 2, 1),
787 MSTPCR("lcdc0", "bus_clk", 2, 0),
789 #if defined(CONFIG_CPU_SUBTYPE_SH7366)
790 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
791 MSTPCR("tlb0", "cpu_clk", 0, 31),
792 MSTPCR("ic0", "cpu_clk", 0, 30),
793 MSTPCR("oc0", "cpu_clk", 0, 29),
794 MSTPCR("rsmem0", "sh_clk", 0, 28),
795 MSTPCR("xymem0", "cpu_clk", 0, 26),
796 MSTPCR("intc30", "peripheral_clk", 0, 23),
797 MSTPCR("intc0", "peripheral_clk", 0, 22),
798 MSTPCR("dmac0", "bus_clk", 0, 21),
799 MSTPCR("sh0", "sh_clk", 0, 20),
800 MSTPCR("hudi0", "peripheral_clk", 0, 19),
801 MSTPCR("ubc0", "cpu_clk", 0, 17),
802 MSTPCR("tmu0", "peripheral_clk", 0, 15),
803 MSTPCR("cmt0", "r_clk", 0, 14),
804 MSTPCR("rwdt0", "r_clk", 0, 13),
805 MSTPCR("flctl0", "peripheral_clk", 0, 10),
806 MSTPCR("scif0", "peripheral_clk", 0, 7),
807 MSTPCR("scif1", "bus_clk", 0, 6),
808 MSTPCR("scif2", "bus_clk", 0, 5),
809 MSTPCR("msiof0", "peripheral_clk", 0, 2),
810 MSTPCR("sbr0", "peripheral_clk", 0, 1),
811 MSTPCR("i2c0", "peripheral_clk", 1, 9),
812 MSTPCR("icb0", "bus_clk", 2, 27),
813 MSTPCR("meram0", "sh_clk", 2, 26),
814 MSTPCR("dacc0", "peripheral_clk", 2, 24),
815 MSTPCR("dacy0", "peripheral_clk", 2, 23),
816 MSTPCR("tsif0", "bus_clk", 2, 22),
817 MSTPCR("sdhi0", "bus_clk", 2, 18),
818 MSTPCR("mmcif0", "bus_clk", 2, 17),
819 MSTPCR("usb0", "bus_clk", 2, 11),
820 MSTPCR("siu0", "bus_clk", 2, 8),
821 MSTPCR("veu1", "bus_clk", 2, 7),
822 MSTPCR("vou0", "bus_clk", 2, 5),
823 MSTPCR("beu0", "bus_clk", 2, 4),
824 MSTPCR("ceu0", "bus_clk", 2, 3),
825 MSTPCR("veu0", "bus_clk", 2, 2),
826 MSTPCR("vpu0", "bus_clk", 2, 1),
827 MSTPCR("lcdc0", "bus_clk", 2, 0),
831 static struct clk *sh7722_clocks[] = {
834 &sh7722_peripheral_clock,
836 #ifndef CONFIG_CPU_SUBTYPE_SH7343
839 #if defined(CONFIG_CPU_SUBTYPE_SH7722)
847 * init in order: master, module, bus, cpu
849 struct clk_ops *onchip_ops[] = {
850 &sh7722_master_clk_ops,
851 &sh7722_module_clk_ops,
852 &sh7722_frqcr_clk_ops,
853 &sh7722_frqcr_clk_ops,
857 arch_init_clk_ops(struct clk_ops **ops, int type)
859 BUG_ON(type < 0 || type > ARRAY_SIZE(onchip_ops));
860 *ops = onchip_ops[type];
863 int __init arch_clk_init(void)
868 clk = clk_get(NULL, "master_clk");
869 for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) {
870 pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name);
871 sh7722_clocks[i]->parent = clk;
872 clk_register(sh7722_clocks[i]);
876 clk_register(&sh7722_r_clock);
878 for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr_clocks); i++) {
879 pr_debug( "Registering mstpcr clock '%s'\n",
880 sh7722_mstpcr_clocks[i].name);
881 clk = clk_get(NULL, (void *) sh7722_mstpcr_clocks[i].ops);
882 sh7722_mstpcr_clocks[i].parent = clk;
883 sh7722_mstpcr_clocks[i].ops = &sh7722_mstpcr_clk_ops;
884 clk_register(&sh7722_mstpcr_clocks[i]);
888 for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr); i++) {
889 pr_debug( "Registering mstpcr '%s'\n", sh7722_mstpcr[i].name);
890 clk_register(&sh7722_mstpcr[i]);