2 * arch/sh/kernel/cpu/sh4a/clock-sh7785.c
4 * SH7785 support for the clock framework
6 * Copyright (C) 2007 - 2010 Paul Mundt
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/clk.h>
16 #include <linux/cpufreq.h>
17 #include <asm/clkdev.h>
18 #include <asm/clock.h>
20 #include <cpu/sh7785.h>
23 * Default rate for the root input clock, reset this with clk_set_rate()
24 * from the platform code.
26 static struct clk extal_clk = {
32 static unsigned long pll_recalc(struct clk *clk)
36 multiplier = test_mode_pin(MODE_PIN4) ? 36 : 72;
38 return clk->parent->rate * multiplier;
41 static struct clk_ops pll_clk_ops = {
45 static struct clk pll_clk = {
50 .flags = CLK_ENABLE_ON_INIT,
53 static struct clk *clks[] = {
58 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
61 static struct clk_div_mult_table div4_div_mult_table = {
63 .nr_divisors = ARRAY_SIZE(div2),
66 static struct clk_div4_table div4_table = {
67 .div_mult_table = &div4_div_mult_table,
70 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
71 DIV4_DU, DIV4_P, DIV4_NR };
73 #define DIV4(_str, _bit, _mask, _flags) \
74 SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
76 struct clk div4_clks[DIV4_NR] = {
77 [DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0),
78 [DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0),
79 [DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0),
80 [DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT),
81 [DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT),
82 [DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT),
83 [DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT),
84 [DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT),
87 #define MSTPCR0 0xffc80030
88 #define MSTPCR1 0xffc80034
90 enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
91 MSTP021, MSTP020, MSTP017, MSTP016,
92 MSTP013, MSTP012, MSTP009, MSTP008, MSTP003, MSTP002,
93 MSTP119, MSTP117, MSTP105, MSTP104, MSTP100,
96 static struct clk mstp_clks[MSTP_NR] = {
98 [MSTP029] = SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
99 [MSTP028] = SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
100 [MSTP027] = SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
101 [MSTP026] = SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
102 [MSTP025] = SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
103 [MSTP024] = SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
104 [MSTP021] = SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
105 [MSTP020] = SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
106 [MSTP017] = SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
107 [MSTP016] = SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
108 [MSTP013] = SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0),
109 [MSTP012] = SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0),
110 [MSTP009] = SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
111 [MSTP008] = SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
112 [MSTP003] = SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0),
113 [MSTP002] = SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
116 [MSTP119] = SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0),
117 [MSTP117] = SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0),
118 [MSTP105] = SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
119 [MSTP104] = SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
120 [MSTP100] = SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0),
123 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
125 static struct clk_lookup lookups[] = {
129 .dev_id = "sh-sci.5",
131 .clk = &mstp_clks[MSTP029],
134 .dev_id = "sh-sci.4",
136 .clk = &mstp_clks[MSTP028],
139 .dev_id = "sh-sci.3",
141 .clk = &mstp_clks[MSTP027],
144 .dev_id = "sh-sci.2",
146 .clk = &mstp_clks[MSTP026],
149 .dev_id = "sh-sci.1",
151 .clk = &mstp_clks[MSTP025],
154 .dev_id = "sh-sci.0",
156 .clk = &mstp_clks[MSTP024],
158 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
159 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
160 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
161 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
162 CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]),
163 CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]),
166 .dev_id = "sh_tmu.0",
168 .clk = &mstp_clks[MSTP008],
171 .dev_id = "sh_tmu.1",
173 .clk = &mstp_clks[MSTP008],
176 .dev_id = "sh_tmu.2",
178 .clk = &mstp_clks[MSTP008],
181 .dev_id = "sh_tmu.3",
183 .clk = &mstp_clks[MSTP009],
186 .dev_id = "sh_tmu.4",
188 .clk = &mstp_clks[MSTP009],
191 .dev_id = "sh_tmu.5",
193 .clk = &mstp_clks[MSTP009],
195 CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]),
196 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
197 CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
198 CLKDEV_CON_ID("ubc_fck", &mstp_clks[MSTP117]),
199 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
200 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
201 CLKDEV_CON_ID("gdta_fck", &mstp_clks[MSTP100]),
204 int __init arch_clk_init(void)
208 for (i = 0; i < ARRAY_SIZE(clks); i++)
209 ret |= clk_register(clks[i]);
210 for (i = 0; i < ARRAY_SIZE(lookups); i++)
211 clkdev_add(&lookups[i]);
214 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
217 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);