2 * arch/sh/kernel/cpu/sh4a/clock-sh7786.c
4 * SH7786 support for the clock framework
6 * Copyright (C) 2010 Paul Mundt
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/clk.h>
16 #include <linux/clk.h>
17 #include <asm/clkdev.h>
18 #include <asm/clock.h>
22 * Default rate for the root input clock, reset this with clk_set_rate()
23 * from the platform code.
25 static struct clk extal_clk = {
29 static unsigned long pll_recalc(struct clk *clk)
34 * Clock modes 0, 1, and 2 use an x64 multiplier against PLL1,
35 * while modes 3, 4, and 5 use an x32.
37 multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32;
39 return clk->parent->rate * multiplier;
42 static struct clk_ops pll_clk_ops = {
46 static struct clk pll_clk = {
49 .flags = CLK_ENABLE_ON_INIT,
52 static struct clk *clks[] = {
57 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
60 static struct clk_div_mult_table div4_div_mult_table = {
62 .nr_divisors = ARRAY_SIZE(div2),
65 static struct clk_div4_table div4_table = {
66 .div_mult_table = &div4_div_mult_table,
69 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
71 #define DIV4(_bit, _mask, _flags) \
72 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
74 struct clk div4_clks[DIV4_NR] = {
75 [DIV4_P] = DIV4(0, 0x0b40, 0),
76 [DIV4_DU] = DIV4(4, 0x0010, 0),
77 [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
78 [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
79 [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
80 [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
83 #define MSTPCR0 0xffc40030
84 #define MSTPCR1 0xffc40034
86 enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
87 MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016,
88 MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008,
89 MSTP005, MSTP004, MSTP002,
90 MSTP112, MSTP110, MSTP109, MSTP108,
91 MSTP105, MSTP104, MSTP103, MSTP102,
94 static struct clk mstp_clks[MSTP_NR] = {
96 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
97 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
98 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
99 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
100 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
101 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
102 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
103 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
104 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
105 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
106 [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
107 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
108 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
109 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
110 [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
111 [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
112 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
113 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
114 [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
115 [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
116 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
119 [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
120 [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
121 [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
122 [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
123 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
124 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
125 [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
126 [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
129 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
131 static struct clk_lookup lookups[] = {
133 CLKDEV_CON_ID("extal", &extal_clk),
134 CLKDEV_CON_ID("pll_clk", &pll_clk),
137 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
138 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
139 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
140 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
141 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
142 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
147 .dev_id = "sh-sci.5",
149 .clk = &mstp_clks[MSTP029],
152 .dev_id = "sh-sci.4",
154 .clk = &mstp_clks[MSTP028],
157 .dev_id = "sh-sci.3",
159 .clk = &mstp_clks[MSTP027],
162 .dev_id = "sh-sci.2",
164 .clk = &mstp_clks[MSTP026],
167 .dev_id = "sh-sci.1",
169 .clk = &mstp_clks[MSTP025],
172 .dev_id = "sh-sci.0",
174 .clk = &mstp_clks[MSTP024],
176 CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
177 CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
178 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
179 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
180 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
181 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
182 CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
183 CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
186 .dev_id = "sh_tmu.0",
188 .clk = &mstp_clks[MSTP008],
191 .dev_id = "sh_tmu.1",
193 .clk = &mstp_clks[MSTP008],
196 .dev_id = "sh_tmu.2",
198 .clk = &mstp_clks[MSTP008],
201 .dev_id = "sh_tmu.3",
203 .clk = &mstp_clks[MSTP009],
206 .dev_id = "sh_tmu.4",
208 .clk = &mstp_clks[MSTP009],
211 .dev_id = "sh_tmu.5",
213 .clk = &mstp_clks[MSTP009],
216 .dev_id = "sh_tmu.6",
218 .clk = &mstp_clks[MSTP010],
221 .dev_id = "sh_tmu.7",
223 .clk = &mstp_clks[MSTP010],
226 .dev_id = "sh_tmu.8",
228 .clk = &mstp_clks[MSTP010],
231 .dev_id = "sh_tmu.9",
233 .clk = &mstp_clks[MSTP011],
236 .dev_id = "sh_tmu.10",
238 .clk = &mstp_clks[MSTP011],
241 .dev_id = "sh_tmu.11",
243 .clk = &mstp_clks[MSTP011],
245 CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
246 CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
247 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
248 CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
249 CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
250 CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
251 CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
252 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
253 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
254 CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
255 CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),
258 int __init arch_clk_init(void)
262 for (i = 0; i < ARRAY_SIZE(clks); i++)
263 ret |= clk_register(clks[i]);
264 for (i = 0; i < ARRAY_SIZE(lookups); i++)
265 clkdev_add(&lookups[i]);
268 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
271 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);