4 * Copyright (C) 2009 Renesas Solutions Corp.
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Based on SH7723 Setup
9 * Copyright (C) 2008 Paul Mundt
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
15 #include <linux/platform_device.h>
16 #include <linux/init.h>
17 #include <linux/serial.h>
19 #include <linux/serial_sci.h>
20 #include <linux/uio_driver.h>
21 #include <linux/sh_dma.h>
22 #include <linux/sh_timer.h>
24 #include <linux/notifier.h>
26 #include <asm/suspend.h>
27 #include <asm/clock.h>
28 #include <asm/mmzone.h>
30 #include <cpu/dma-register.h>
31 #include <cpu/sh7724.h>
34 static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = {
36 .slave_id = SHDMA_SLAVE_SCIF0_TX,
38 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
41 .slave_id = SHDMA_SLAVE_SCIF0_RX,
43 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
46 .slave_id = SHDMA_SLAVE_SCIF1_TX,
48 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
51 .slave_id = SHDMA_SLAVE_SCIF1_RX,
53 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
56 .slave_id = SHDMA_SLAVE_SCIF2_TX,
58 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
61 .slave_id = SHDMA_SLAVE_SCIF2_RX,
63 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
66 .slave_id = SHDMA_SLAVE_SCIF3_TX,
68 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
71 .slave_id = SHDMA_SLAVE_SCIF3_RX,
73 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
76 .slave_id = SHDMA_SLAVE_SCIF4_TX,
78 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
81 .slave_id = SHDMA_SLAVE_SCIF4_RX,
83 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
86 .slave_id = SHDMA_SLAVE_SCIF5_TX,
88 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
91 .slave_id = SHDMA_SLAVE_SCIF5_RX,
93 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
96 .slave_id = SHDMA_SLAVE_SDHI0_TX,
98 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
101 .slave_id = SHDMA_SLAVE_SDHI0_RX,
103 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
106 .slave_id = SHDMA_SLAVE_SDHI1_TX,
108 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
111 .slave_id = SHDMA_SLAVE_SDHI1_RX,
113 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
118 static const struct sh_dmae_channel sh7724_dmae_channels[] = {
146 static const unsigned int ts_shift[] = TS_SHIFT;
148 static struct sh_dmae_pdata dma_platform_data = {
149 .slave = sh7724_dmae_slaves,
150 .slave_num = ARRAY_SIZE(sh7724_dmae_slaves),
151 .channel = sh7724_dmae_channels,
152 .channel_num = ARRAY_SIZE(sh7724_dmae_channels),
153 .ts_low_shift = CHCR_TS_LOW_SHIFT,
154 .ts_low_mask = CHCR_TS_LOW_MASK,
155 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
156 .ts_high_mask = CHCR_TS_HIGH_MASK,
157 .ts_shift = ts_shift,
158 .ts_shift_num = ARRAY_SIZE(ts_shift),
159 .dmaor_init = DMAOR_INIT,
162 /* Resource order important! */
163 static struct resource sh7724_dmae0_resources[] = {
165 /* Channel registers and DMAOR */
168 .flags = IORESOURCE_MEM,
174 .flags = IORESOURCE_MEM,
180 .flags = IORESOURCE_IRQ,
183 /* IRQ for channels 0-3 */
186 .flags = IORESOURCE_IRQ,
189 /* IRQ for channels 4-5 */
192 .flags = IORESOURCE_IRQ,
196 /* Resource order important! */
197 static struct resource sh7724_dmae1_resources[] = {
199 /* Channel registers and DMAOR */
202 .flags = IORESOURCE_MEM,
208 .flags = IORESOURCE_MEM,
214 .flags = IORESOURCE_IRQ,
217 /* IRQ for channels 0-3 */
220 .flags = IORESOURCE_IRQ,
223 /* IRQ for channels 4-5 */
226 .flags = IORESOURCE_IRQ,
230 static struct platform_device dma0_device = {
231 .name = "sh-dma-engine",
233 .resource = sh7724_dmae0_resources,
234 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources),
236 .platform_data = &dma_platform_data,
239 .hwblk_id = HWBLK_DMAC0,
243 static struct platform_device dma1_device = {
244 .name = "sh-dma-engine",
246 .resource = sh7724_dmae1_resources,
247 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources),
249 .platform_data = &dma_platform_data,
252 .hwblk_id = HWBLK_DMAC1,
257 static struct plat_sci_port scif0_platform_data = {
258 .mapbase = 0xffe00000,
259 .flags = UPF_BOOT_AUTOCONF,
261 .irqs = { 80, 80, 80, 80 },
264 static struct platform_device scif0_device = {
268 .platform_data = &scif0_platform_data,
272 static struct plat_sci_port scif1_platform_data = {
273 .mapbase = 0xffe10000,
274 .flags = UPF_BOOT_AUTOCONF,
276 .irqs = { 81, 81, 81, 81 },
279 static struct platform_device scif1_device = {
283 .platform_data = &scif1_platform_data,
287 static struct plat_sci_port scif2_platform_data = {
288 .mapbase = 0xffe20000,
289 .flags = UPF_BOOT_AUTOCONF,
291 .irqs = { 82, 82, 82, 82 },
294 static struct platform_device scif2_device = {
298 .platform_data = &scif2_platform_data,
302 static struct plat_sci_port scif3_platform_data = {
303 .mapbase = 0xa4e30000,
304 .flags = UPF_BOOT_AUTOCONF,
306 .irqs = { 56, 56, 56, 56 },
309 static struct platform_device scif3_device = {
313 .platform_data = &scif3_platform_data,
317 static struct plat_sci_port scif4_platform_data = {
318 .mapbase = 0xa4e40000,
319 .flags = UPF_BOOT_AUTOCONF,
321 .irqs = { 88, 88, 88, 88 },
324 static struct platform_device scif4_device = {
328 .platform_data = &scif4_platform_data,
332 static struct plat_sci_port scif5_platform_data = {
333 .mapbase = 0xa4e50000,
334 .flags = UPF_BOOT_AUTOCONF,
336 .irqs = { 109, 109, 109, 109 },
339 static struct platform_device scif5_device = {
343 .platform_data = &scif5_platform_data,
348 static struct resource rtc_resources[] = {
351 .end = 0xa465fec0 + 0x58 - 1,
352 .flags = IORESOURCE_IO,
357 .flags = IORESOURCE_IRQ,
362 .flags = IORESOURCE_IRQ,
367 .flags = IORESOURCE_IRQ,
371 static struct platform_device rtc_device = {
374 .num_resources = ARRAY_SIZE(rtc_resources),
375 .resource = rtc_resources,
377 .hwblk_id = HWBLK_RTC,
382 static struct resource iic0_resources[] = {
386 .end = 0x04470018 - 1,
387 .flags = IORESOURCE_MEM,
392 .flags = IORESOURCE_IRQ,
396 static struct platform_device iic0_device = {
397 .name = "i2c-sh_mobile",
398 .id = 0, /* "i2c0" clock */
399 .num_resources = ARRAY_SIZE(iic0_resources),
400 .resource = iic0_resources,
402 .hwblk_id = HWBLK_IIC0,
407 static struct resource iic1_resources[] = {
411 .end = 0x04750018 - 1,
412 .flags = IORESOURCE_MEM,
417 .flags = IORESOURCE_IRQ,
421 static struct platform_device iic1_device = {
422 .name = "i2c-sh_mobile",
423 .id = 1, /* "i2c1" clock */
424 .num_resources = ARRAY_SIZE(iic1_resources),
425 .resource = iic1_resources,
427 .hwblk_id = HWBLK_IIC1,
432 static struct uio_info vpu_platform_data = {
438 static struct resource vpu_resources[] = {
443 .flags = IORESOURCE_MEM,
446 /* place holder for contiguous memory */
450 static struct platform_device vpu_device = {
451 .name = "uio_pdrv_genirq",
454 .platform_data = &vpu_platform_data,
456 .resource = vpu_resources,
457 .num_resources = ARRAY_SIZE(vpu_resources),
459 .hwblk_id = HWBLK_VPU,
464 static struct uio_info veu0_platform_data = {
470 static struct resource veu0_resources[] = {
475 .flags = IORESOURCE_MEM,
478 /* place holder for contiguous memory */
482 static struct platform_device veu0_device = {
483 .name = "uio_pdrv_genirq",
486 .platform_data = &veu0_platform_data,
488 .resource = veu0_resources,
489 .num_resources = ARRAY_SIZE(veu0_resources),
491 .hwblk_id = HWBLK_VEU0,
496 static struct uio_info veu1_platform_data = {
502 static struct resource veu1_resources[] = {
507 .flags = IORESOURCE_MEM,
510 /* place holder for contiguous memory */
514 static struct platform_device veu1_device = {
515 .name = "uio_pdrv_genirq",
518 .platform_data = &veu1_platform_data,
520 .resource = veu1_resources,
521 .num_resources = ARRAY_SIZE(veu1_resources),
523 .hwblk_id = HWBLK_VEU1,
527 static struct sh_timer_config cmt_platform_data = {
528 .channel_offset = 0x60,
530 .clockevent_rating = 125,
531 .clocksource_rating = 200,
534 static struct resource cmt_resources[] = {
538 .flags = IORESOURCE_MEM,
542 .flags = IORESOURCE_IRQ,
546 static struct platform_device cmt_device = {
550 .platform_data = &cmt_platform_data,
552 .resource = cmt_resources,
553 .num_resources = ARRAY_SIZE(cmt_resources),
555 .hwblk_id = HWBLK_CMT,
559 static struct sh_timer_config tmu0_platform_data = {
560 .channel_offset = 0x04,
562 .clockevent_rating = 200,
565 static struct resource tmu0_resources[] = {
569 .flags = IORESOURCE_MEM,
573 .flags = IORESOURCE_IRQ,
577 static struct platform_device tmu0_device = {
581 .platform_data = &tmu0_platform_data,
583 .resource = tmu0_resources,
584 .num_resources = ARRAY_SIZE(tmu0_resources),
586 .hwblk_id = HWBLK_TMU0,
590 static struct sh_timer_config tmu1_platform_data = {
591 .channel_offset = 0x10,
593 .clocksource_rating = 200,
596 static struct resource tmu1_resources[] = {
600 .flags = IORESOURCE_MEM,
604 .flags = IORESOURCE_IRQ,
608 static struct platform_device tmu1_device = {
612 .platform_data = &tmu1_platform_data,
614 .resource = tmu1_resources,
615 .num_resources = ARRAY_SIZE(tmu1_resources),
617 .hwblk_id = HWBLK_TMU0,
621 static struct sh_timer_config tmu2_platform_data = {
622 .channel_offset = 0x1c,
626 static struct resource tmu2_resources[] = {
630 .flags = IORESOURCE_MEM,
634 .flags = IORESOURCE_IRQ,
638 static struct platform_device tmu2_device = {
642 .platform_data = &tmu2_platform_data,
644 .resource = tmu2_resources,
645 .num_resources = ARRAY_SIZE(tmu2_resources),
647 .hwblk_id = HWBLK_TMU0,
652 static struct sh_timer_config tmu3_platform_data = {
653 .channel_offset = 0x04,
657 static struct resource tmu3_resources[] = {
661 .flags = IORESOURCE_MEM,
665 .flags = IORESOURCE_IRQ,
669 static struct platform_device tmu3_device = {
673 .platform_data = &tmu3_platform_data,
675 .resource = tmu3_resources,
676 .num_resources = ARRAY_SIZE(tmu3_resources),
678 .hwblk_id = HWBLK_TMU1,
682 static struct sh_timer_config tmu4_platform_data = {
683 .channel_offset = 0x10,
687 static struct resource tmu4_resources[] = {
691 .flags = IORESOURCE_MEM,
695 .flags = IORESOURCE_IRQ,
699 static struct platform_device tmu4_device = {
703 .platform_data = &tmu4_platform_data,
705 .resource = tmu4_resources,
706 .num_resources = ARRAY_SIZE(tmu4_resources),
708 .hwblk_id = HWBLK_TMU1,
712 static struct sh_timer_config tmu5_platform_data = {
713 .channel_offset = 0x1c,
717 static struct resource tmu5_resources[] = {
721 .flags = IORESOURCE_MEM,
725 .flags = IORESOURCE_IRQ,
729 static struct platform_device tmu5_device = {
733 .platform_data = &tmu5_platform_data,
735 .resource = tmu5_resources,
736 .num_resources = ARRAY_SIZE(tmu5_resources),
738 .hwblk_id = HWBLK_TMU1,
743 static struct uio_info jpu_platform_data = {
749 static struct resource jpu_resources[] = {
754 .flags = IORESOURCE_MEM,
757 /* place holder for contiguous memory */
761 static struct platform_device jpu_device = {
762 .name = "uio_pdrv_genirq",
765 .platform_data = &jpu_platform_data,
767 .resource = jpu_resources,
768 .num_resources = ARRAY_SIZE(jpu_resources),
770 .hwblk_id = HWBLK_JPU,
775 static struct uio_info spu0_platform_data = {
781 static struct resource spu0_resources[] = {
786 .flags = IORESOURCE_MEM,
789 /* place holder for contiguous memory */
793 static struct platform_device spu0_device = {
794 .name = "uio_pdrv_genirq",
797 .platform_data = &spu0_platform_data,
799 .resource = spu0_resources,
800 .num_resources = ARRAY_SIZE(spu0_resources),
802 .hwblk_id = HWBLK_SPU,
807 static struct uio_info spu1_platform_data = {
813 static struct resource spu1_resources[] = {
818 .flags = IORESOURCE_MEM,
821 /* place holder for contiguous memory */
825 static struct platform_device spu1_device = {
826 .name = "uio_pdrv_genirq",
829 .platform_data = &spu1_platform_data,
831 .resource = spu1_resources,
832 .num_resources = ARRAY_SIZE(spu1_resources),
834 .hwblk_id = HWBLK_SPU,
838 static struct platform_device *sh7724_devices[] __initdata = {
865 static int __init sh7724_devices_setup(void)
867 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
868 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
869 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
870 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
871 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20);
872 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20);
874 return platform_add_devices(sh7724_devices,
875 ARRAY_SIZE(sh7724_devices));
877 arch_initcall(sh7724_devices_setup);
879 static struct platform_device *sh7724_early_devices[] __initdata = {
895 void __init plat_early_device_setup(void)
897 early_platform_add_devices(sh7724_early_devices,
898 ARRAY_SIZE(sh7724_early_devices));
901 #define RAMCR_CACHE_L2FC 0x0002
902 #define RAMCR_CACHE_L2E 0x0001
903 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
905 void l2_cache_init(void)
907 /* Enable L2 cache */
908 __raw_writel(L2_CACHE_ENABLE, RAMCR);
916 /* interrupt sources */
917 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
919 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
920 _2DG_TRI, _2DG_INI, _2DG_CEI,
921 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
922 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
930 RTC_ATI, RTC_PRI, RTC_CUI,
931 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
932 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
934 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
936 MSIOF_MSIOFI0, MSIOF_MSIOFI1,
937 SPU_SPUI0, SPU_SPUI1,
941 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
942 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
947 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
951 MMC_MMC2I, MMC_MMC3I,
953 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
955 /* interrupt groups */
956 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
957 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
960 static struct intc_vect vectors[] __initdata = {
961 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
962 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
963 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
964 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
966 INTC_VECT(DMAC1A_DEI0, 0x700),
967 INTC_VECT(DMAC1A_DEI1, 0x720),
968 INTC_VECT(DMAC1A_DEI2, 0x740),
969 INTC_VECT(DMAC1A_DEI3, 0x760),
971 INTC_VECT(_2DG_TRI, 0x780),
972 INTC_VECT(_2DG_INI, 0x7A0),
973 INTC_VECT(_2DG_CEI, 0x7C0),
975 INTC_VECT(DMAC0A_DEI0, 0x800),
976 INTC_VECT(DMAC0A_DEI1, 0x820),
977 INTC_VECT(DMAC0A_DEI2, 0x840),
978 INTC_VECT(DMAC0A_DEI3, 0x860),
980 INTC_VECT(VIO_CEU0, 0x880),
981 INTC_VECT(VIO_BEU0, 0x8A0),
982 INTC_VECT(VIO_VEU1, 0x8C0),
983 INTC_VECT(VIO_VOU, 0x8E0),
985 INTC_VECT(SCIFA3, 0x900),
986 INTC_VECT(VPU, 0x980),
987 INTC_VECT(TPU, 0x9A0),
988 INTC_VECT(CEU1, 0x9E0),
989 INTC_VECT(BEU1, 0xA00),
990 INTC_VECT(USB0, 0xA20),
991 INTC_VECT(USB1, 0xA40),
992 INTC_VECT(ATAPI, 0xA60),
994 INTC_VECT(RTC_ATI, 0xA80),
995 INTC_VECT(RTC_PRI, 0xAA0),
996 INTC_VECT(RTC_CUI, 0xAC0),
998 INTC_VECT(DMAC1B_DEI4, 0xB00),
999 INTC_VECT(DMAC1B_DEI5, 0xB20),
1000 INTC_VECT(DMAC1B_DADERR, 0xB40),
1002 INTC_VECT(DMAC0B_DEI4, 0xB80),
1003 INTC_VECT(DMAC0B_DEI5, 0xBA0),
1004 INTC_VECT(DMAC0B_DADERR, 0xBC0),
1006 INTC_VECT(KEYSC, 0xBE0),
1007 INTC_VECT(SCIF_SCIF0, 0xC00),
1008 INTC_VECT(SCIF_SCIF1, 0xC20),
1009 INTC_VECT(SCIF_SCIF2, 0xC40),
1010 INTC_VECT(VEU0, 0xC60),
1011 INTC_VECT(MSIOF_MSIOFI0, 0xC80),
1012 INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
1013 INTC_VECT(SPU_SPUI0, 0xCC0),
1014 INTC_VECT(SPU_SPUI1, 0xCE0),
1015 INTC_VECT(SCIFA4, 0xD00),
1017 INTC_VECT(ICB, 0xD20),
1018 INTC_VECT(ETHI, 0xD60),
1020 INTC_VECT(I2C1_ALI, 0xD80),
1021 INTC_VECT(I2C1_TACKI, 0xDA0),
1022 INTC_VECT(I2C1_WAITI, 0xDC0),
1023 INTC_VECT(I2C1_DTEI, 0xDE0),
1025 INTC_VECT(I2C0_ALI, 0xE00),
1026 INTC_VECT(I2C0_TACKI, 0xE20),
1027 INTC_VECT(I2C0_WAITI, 0xE40),
1028 INTC_VECT(I2C0_DTEI, 0xE60),
1030 INTC_VECT(SDHI0, 0xE80),
1031 INTC_VECT(SDHI0, 0xEA0),
1032 INTC_VECT(SDHI0, 0xEC0),
1033 INTC_VECT(SDHI0, 0xEE0),
1035 INTC_VECT(CMT, 0xF00),
1036 INTC_VECT(TSIF, 0xF20),
1037 INTC_VECT(FSI, 0xF80),
1038 INTC_VECT(SCIFA5, 0xFA0),
1040 INTC_VECT(TMU0_TUNI0, 0x400),
1041 INTC_VECT(TMU0_TUNI1, 0x420),
1042 INTC_VECT(TMU0_TUNI2, 0x440),
1044 INTC_VECT(IRDA, 0x480),
1046 INTC_VECT(SDHI1, 0x4E0),
1047 INTC_VECT(SDHI1, 0x500),
1048 INTC_VECT(SDHI1, 0x520),
1050 INTC_VECT(JPU, 0x560),
1051 INTC_VECT(_2DDMAC, 0x4A0),
1053 INTC_VECT(MMC_MMC2I, 0x5A0),
1054 INTC_VECT(MMC_MMC3I, 0x5C0),
1056 INTC_VECT(LCDC, 0xF40),
1058 INTC_VECT(TMU1_TUNI0, 0x920),
1059 INTC_VECT(TMU1_TUNI1, 0x940),
1060 INTC_VECT(TMU1_TUNI2, 0x960),
1063 static struct intc_group groups[] __initdata = {
1064 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
1065 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
1066 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
1067 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
1068 INTC_GROUP(USB, USB0, USB1),
1069 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
1070 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
1071 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
1072 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
1073 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
1074 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
1075 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
1078 static struct intc_mask_reg mask_registers[] __initdata = {
1079 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
1080 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
1081 0, DISABLED, ENABLED, ENABLED } },
1082 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
1083 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
1084 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
1085 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
1086 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
1087 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
1088 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
1089 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
1090 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
1091 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
1092 JPU, 0, 0, LCDC } },
1093 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
1094 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
1095 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
1096 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
1097 { 0, 0, ICB, SCIFA4,
1098 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
1099 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
1100 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
1101 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
1102 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
1103 { DISABLED, DISABLED, ENABLED, ENABLED,
1104 0, 0, SCIFA5, FSI } },
1105 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
1106 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
1107 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
1108 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
1109 0, RTC_CUI, RTC_PRI, RTC_ATI } },
1110 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
1111 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
1112 0, TPU, 0, TSIF } },
1113 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
1114 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
1115 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
1116 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1119 static struct intc_prio_reg prio_registers[] __initdata = {
1120 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
1121 TMU0_TUNI2, IRDA } },
1122 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
1123 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
1124 TMU1_TUNI2, SPU } },
1125 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } },
1126 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
1127 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } },
1128 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
1129 SCIF_SCIF2, VEU0 } },
1130 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1132 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } },
1133 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } },
1134 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } },
1135 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
1136 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
1137 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1140 static struct intc_sense_reg sense_registers[] __initdata = {
1141 { 0xa414001c, 16, 2, /* ICR1 */
1142 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1145 static struct intc_mask_reg ack_registers[] __initdata = {
1146 { 0xa4140024, 0, 8, /* INTREQ00 */
1147 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1150 static struct intc_desc intc_desc __initdata = {
1152 .force_enable = ENABLED,
1153 .force_disable = DISABLED,
1154 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
1155 prio_registers, sense_registers, ack_registers),
1158 void __init plat_irq_setup(void)
1160 register_intc_controller(&intc_desc);
1165 unsigned long mmselr;
1166 unsigned long cs0bcr;
1167 unsigned long cs4bcr;
1168 unsigned long cs5abcr;
1169 unsigned long cs5bbcr;
1170 unsigned long cs6abcr;
1171 unsigned long cs6bbcr;
1172 unsigned long cs4wcr;
1173 unsigned long cs5awcr;
1174 unsigned long cs5bwcr;
1175 unsigned long cs6awcr;
1176 unsigned long cs6bwcr;
1178 unsigned short ipra;
1179 unsigned short iprb;
1180 unsigned short iprc;
1181 unsigned short iprd;
1182 unsigned short ipre;
1183 unsigned short iprf;
1184 unsigned short iprg;
1185 unsigned short iprh;
1186 unsigned short ipri;
1187 unsigned short iprj;
1188 unsigned short iprk;
1189 unsigned short iprl;
1200 unsigned char imr10;
1201 unsigned char imr11;
1202 unsigned char imr12;
1204 unsigned short rwtcnt;
1205 unsigned short rwtcsr;
1207 unsigned long irdaclk;
1208 unsigned long spuclk;
1209 } sh7724_rstandby_state;
1211 static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb,
1212 unsigned long flags, void *unused)
1214 if (!(flags & SUSP_SH_RSTANDBY))
1218 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */
1219 sh7724_rstandby_state.mmselr |= 0xa5a50000;
1220 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */
1221 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */
1222 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */
1223 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */
1224 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */
1225 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */
1226 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */
1227 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */
1228 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */
1229 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */
1230 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */
1233 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */
1234 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */
1235 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */
1236 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */
1237 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */
1238 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */
1239 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */
1240 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */
1241 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */
1242 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */
1243 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */
1244 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */
1245 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */
1246 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */
1247 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */
1248 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */
1249 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */
1250 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */
1251 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */
1252 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */
1253 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */
1254 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */
1255 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */
1256 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */
1257 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */
1260 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */
1261 sh7724_rstandby_state.rwtcnt |= 0x5a00;
1262 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */
1263 sh7724_rstandby_state.rwtcsr |= 0xa500;
1264 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
1267 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */
1268 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */
1273 static int sh7724_post_sleep_notifier_call(struct notifier_block *nb,
1274 unsigned long flags, void *unused)
1276 if (!(flags & SUSP_SH_RSTANDBY))
1280 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */
1281 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */
1282 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */
1283 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */
1284 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */
1285 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */
1286 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */
1287 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */
1288 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */
1289 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */
1290 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */
1291 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */
1294 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */
1295 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */
1296 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */
1297 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */
1298 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */
1299 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */
1300 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */
1301 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */
1302 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */
1303 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */
1304 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */
1305 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */
1306 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */
1307 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */
1308 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */
1309 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */
1310 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */
1311 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */
1312 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */
1313 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */
1314 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */
1315 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */
1316 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */
1317 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */
1318 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */
1321 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */
1322 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */
1325 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */
1326 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */
1331 static struct notifier_block sh7724_pre_sleep_notifier = {
1332 .notifier_call = sh7724_pre_sleep_notifier_call,
1333 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU),
1336 static struct notifier_block sh7724_post_sleep_notifier = {
1337 .notifier_call = sh7724_post_sleep_notifier_call,
1338 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU),
1341 static int __init sh7724_sleep_setup(void)
1343 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list,
1344 &sh7724_pre_sleep_notifier);
1346 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list,
1347 &sh7724_post_sleep_notifier);
1350 arch_initcall(sh7724_sleep_setup);