4 * Copyright (C) 2009 Renesas Solutions Corp.
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Based on SH7723 Setup
9 * Copyright (C) 2008 Paul Mundt
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
15 #include <linux/platform_device.h>
16 #include <linux/init.h>
17 #include <linux/serial.h>
19 #include <linux/serial_sci.h>
20 #include <linux/uio_driver.h>
21 #include <linux/sh_timer.h>
23 #include <linux/notifier.h>
25 #include <asm/suspend.h>
26 #include <asm/clock.h>
27 #include <asm/dmaengine.h>
28 #include <asm/mmzone.h>
30 #include <cpu/dma-register.h>
31 #include <cpu/sh7724.h>
34 static const struct sh_dmae_channel sh7724_dmae_channels[] = {
62 static const unsigned int ts_shift[] = TS_SHIFT;
64 static struct sh_dmae_pdata dma_platform_data = {
65 .channel = sh7724_dmae_channels,
66 .channel_num = ARRAY_SIZE(sh7724_dmae_channels),
67 .ts_low_shift = CHCR_TS_LOW_SHIFT,
68 .ts_low_mask = CHCR_TS_LOW_MASK,
69 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
70 .ts_high_mask = CHCR_TS_HIGH_MASK,
72 .ts_shift_num = ARRAY_SIZE(ts_shift),
73 .dmaor_init = DMAOR_INIT,
76 /* Resource order important! */
77 static struct resource sh7724_dmae0_resources[] = {
79 /* Channel registers and DMAOR */
82 .flags = IORESOURCE_MEM,
88 .flags = IORESOURCE_MEM,
94 .flags = IORESOURCE_IRQ,
97 /* IRQ for channels 0-3 */
100 .flags = IORESOURCE_IRQ,
103 /* IRQ for channels 4-5 */
106 .flags = IORESOURCE_IRQ,
110 /* Resource order important! */
111 static struct resource sh7724_dmae1_resources[] = {
113 /* Channel registers and DMAOR */
116 .flags = IORESOURCE_MEM,
122 .flags = IORESOURCE_MEM,
128 .flags = IORESOURCE_IRQ,
131 /* IRQ for channels 0-3 */
134 .flags = IORESOURCE_IRQ,
137 /* IRQ for channels 4-5 */
140 .flags = IORESOURCE_IRQ,
144 static struct platform_device dma0_device = {
145 .name = "sh-dma-engine",
147 .resource = sh7724_dmae0_resources,
148 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources),
150 .platform_data = &dma_platform_data,
153 .hwblk_id = HWBLK_DMAC0,
157 static struct platform_device dma1_device = {
158 .name = "sh-dma-engine",
160 .resource = sh7724_dmae1_resources,
161 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources),
163 .platform_data = &dma_platform_data,
166 .hwblk_id = HWBLK_DMAC1,
171 static struct plat_sci_port scif0_platform_data = {
172 .mapbase = 0xffe00000,
173 .flags = UPF_BOOT_AUTOCONF,
175 .irqs = { 80, 80, 80, 80 },
178 static struct platform_device scif0_device = {
182 .platform_data = &scif0_platform_data,
186 static struct plat_sci_port scif1_platform_data = {
187 .mapbase = 0xffe10000,
188 .flags = UPF_BOOT_AUTOCONF,
190 .irqs = { 81, 81, 81, 81 },
193 static struct platform_device scif1_device = {
197 .platform_data = &scif1_platform_data,
201 static struct plat_sci_port scif2_platform_data = {
202 .mapbase = 0xffe20000,
203 .flags = UPF_BOOT_AUTOCONF,
205 .irqs = { 82, 82, 82, 82 },
208 static struct platform_device scif2_device = {
212 .platform_data = &scif2_platform_data,
216 static struct plat_sci_port scif3_platform_data = {
217 .mapbase = 0xa4e30000,
218 .flags = UPF_BOOT_AUTOCONF,
220 .irqs = { 56, 56, 56, 56 },
223 static struct platform_device scif3_device = {
227 .platform_data = &scif3_platform_data,
231 static struct plat_sci_port scif4_platform_data = {
232 .mapbase = 0xa4e40000,
233 .flags = UPF_BOOT_AUTOCONF,
235 .irqs = { 88, 88, 88, 88 },
238 static struct platform_device scif4_device = {
242 .platform_data = &scif4_platform_data,
246 static struct plat_sci_port scif5_platform_data = {
247 .mapbase = 0xa4e50000,
248 .flags = UPF_BOOT_AUTOCONF,
250 .irqs = { 109, 109, 109, 109 },
253 static struct platform_device scif5_device = {
257 .platform_data = &scif5_platform_data,
262 static struct resource rtc_resources[] = {
265 .end = 0xa465fec0 + 0x58 - 1,
266 .flags = IORESOURCE_IO,
271 .flags = IORESOURCE_IRQ,
276 .flags = IORESOURCE_IRQ,
281 .flags = IORESOURCE_IRQ,
285 static struct platform_device rtc_device = {
288 .num_resources = ARRAY_SIZE(rtc_resources),
289 .resource = rtc_resources,
291 .hwblk_id = HWBLK_RTC,
296 static struct resource iic0_resources[] = {
300 .end = 0x04470018 - 1,
301 .flags = IORESOURCE_MEM,
306 .flags = IORESOURCE_IRQ,
310 static struct platform_device iic0_device = {
311 .name = "i2c-sh_mobile",
312 .id = 0, /* "i2c0" clock */
313 .num_resources = ARRAY_SIZE(iic0_resources),
314 .resource = iic0_resources,
316 .hwblk_id = HWBLK_IIC0,
321 static struct resource iic1_resources[] = {
325 .end = 0x04750018 - 1,
326 .flags = IORESOURCE_MEM,
331 .flags = IORESOURCE_IRQ,
335 static struct platform_device iic1_device = {
336 .name = "i2c-sh_mobile",
337 .id = 1, /* "i2c1" clock */
338 .num_resources = ARRAY_SIZE(iic1_resources),
339 .resource = iic1_resources,
341 .hwblk_id = HWBLK_IIC1,
346 static struct uio_info vpu_platform_data = {
352 static struct resource vpu_resources[] = {
357 .flags = IORESOURCE_MEM,
360 /* place holder for contiguous memory */
364 static struct platform_device vpu_device = {
365 .name = "uio_pdrv_genirq",
368 .platform_data = &vpu_platform_data,
370 .resource = vpu_resources,
371 .num_resources = ARRAY_SIZE(vpu_resources),
373 .hwblk_id = HWBLK_VPU,
378 static struct uio_info veu0_platform_data = {
384 static struct resource veu0_resources[] = {
389 .flags = IORESOURCE_MEM,
392 /* place holder for contiguous memory */
396 static struct platform_device veu0_device = {
397 .name = "uio_pdrv_genirq",
400 .platform_data = &veu0_platform_data,
402 .resource = veu0_resources,
403 .num_resources = ARRAY_SIZE(veu0_resources),
405 .hwblk_id = HWBLK_VEU0,
410 static struct uio_info veu1_platform_data = {
416 static struct resource veu1_resources[] = {
421 .flags = IORESOURCE_MEM,
424 /* place holder for contiguous memory */
428 static struct platform_device veu1_device = {
429 .name = "uio_pdrv_genirq",
432 .platform_data = &veu1_platform_data,
434 .resource = veu1_resources,
435 .num_resources = ARRAY_SIZE(veu1_resources),
437 .hwblk_id = HWBLK_VEU1,
441 static struct sh_timer_config cmt_platform_data = {
442 .channel_offset = 0x60,
444 .clockevent_rating = 125,
445 .clocksource_rating = 200,
448 static struct resource cmt_resources[] = {
452 .flags = IORESOURCE_MEM,
456 .flags = IORESOURCE_IRQ,
460 static struct platform_device cmt_device = {
464 .platform_data = &cmt_platform_data,
466 .resource = cmt_resources,
467 .num_resources = ARRAY_SIZE(cmt_resources),
469 .hwblk_id = HWBLK_CMT,
473 static struct sh_timer_config tmu0_platform_data = {
474 .channel_offset = 0x04,
476 .clockevent_rating = 200,
479 static struct resource tmu0_resources[] = {
483 .flags = IORESOURCE_MEM,
487 .flags = IORESOURCE_IRQ,
491 static struct platform_device tmu0_device = {
495 .platform_data = &tmu0_platform_data,
497 .resource = tmu0_resources,
498 .num_resources = ARRAY_SIZE(tmu0_resources),
500 .hwblk_id = HWBLK_TMU0,
504 static struct sh_timer_config tmu1_platform_data = {
505 .channel_offset = 0x10,
507 .clocksource_rating = 200,
510 static struct resource tmu1_resources[] = {
514 .flags = IORESOURCE_MEM,
518 .flags = IORESOURCE_IRQ,
522 static struct platform_device tmu1_device = {
526 .platform_data = &tmu1_platform_data,
528 .resource = tmu1_resources,
529 .num_resources = ARRAY_SIZE(tmu1_resources),
531 .hwblk_id = HWBLK_TMU0,
535 static struct sh_timer_config tmu2_platform_data = {
536 .channel_offset = 0x1c,
540 static struct resource tmu2_resources[] = {
544 .flags = IORESOURCE_MEM,
548 .flags = IORESOURCE_IRQ,
552 static struct platform_device tmu2_device = {
556 .platform_data = &tmu2_platform_data,
558 .resource = tmu2_resources,
559 .num_resources = ARRAY_SIZE(tmu2_resources),
561 .hwblk_id = HWBLK_TMU0,
566 static struct sh_timer_config tmu3_platform_data = {
567 .channel_offset = 0x04,
571 static struct resource tmu3_resources[] = {
575 .flags = IORESOURCE_MEM,
579 .flags = IORESOURCE_IRQ,
583 static struct platform_device tmu3_device = {
587 .platform_data = &tmu3_platform_data,
589 .resource = tmu3_resources,
590 .num_resources = ARRAY_SIZE(tmu3_resources),
592 .hwblk_id = HWBLK_TMU1,
596 static struct sh_timer_config tmu4_platform_data = {
597 .channel_offset = 0x10,
601 static struct resource tmu4_resources[] = {
605 .flags = IORESOURCE_MEM,
609 .flags = IORESOURCE_IRQ,
613 static struct platform_device tmu4_device = {
617 .platform_data = &tmu4_platform_data,
619 .resource = tmu4_resources,
620 .num_resources = ARRAY_SIZE(tmu4_resources),
622 .hwblk_id = HWBLK_TMU1,
626 static struct sh_timer_config tmu5_platform_data = {
627 .channel_offset = 0x1c,
631 static struct resource tmu5_resources[] = {
635 .flags = IORESOURCE_MEM,
639 .flags = IORESOURCE_IRQ,
643 static struct platform_device tmu5_device = {
647 .platform_data = &tmu5_platform_data,
649 .resource = tmu5_resources,
650 .num_resources = ARRAY_SIZE(tmu5_resources),
652 .hwblk_id = HWBLK_TMU1,
657 static struct uio_info jpu_platform_data = {
663 static struct resource jpu_resources[] = {
668 .flags = IORESOURCE_MEM,
671 /* place holder for contiguous memory */
675 static struct platform_device jpu_device = {
676 .name = "uio_pdrv_genirq",
679 .platform_data = &jpu_platform_data,
681 .resource = jpu_resources,
682 .num_resources = ARRAY_SIZE(jpu_resources),
684 .hwblk_id = HWBLK_JPU,
689 static struct uio_info spu0_platform_data = {
695 static struct resource spu0_resources[] = {
700 .flags = IORESOURCE_MEM,
703 /* place holder for contiguous memory */
707 static struct platform_device spu0_device = {
708 .name = "uio_pdrv_genirq",
711 .platform_data = &spu0_platform_data,
713 .resource = spu0_resources,
714 .num_resources = ARRAY_SIZE(spu0_resources),
716 .hwblk_id = HWBLK_SPU,
721 static struct uio_info spu1_platform_data = {
727 static struct resource spu1_resources[] = {
732 .flags = IORESOURCE_MEM,
735 /* place holder for contiguous memory */
739 static struct platform_device spu1_device = {
740 .name = "uio_pdrv_genirq",
743 .platform_data = &spu1_platform_data,
745 .resource = spu1_resources,
746 .num_resources = ARRAY_SIZE(spu1_resources),
748 .hwblk_id = HWBLK_SPU,
752 static struct platform_device *sh7724_devices[] __initdata = {
779 static int __init sh7724_devices_setup(void)
781 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
782 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
783 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
784 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
785 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20);
786 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20);
788 return platform_add_devices(sh7724_devices,
789 ARRAY_SIZE(sh7724_devices));
791 arch_initcall(sh7724_devices_setup);
793 static struct platform_device *sh7724_early_devices[] __initdata = {
809 void __init plat_early_device_setup(void)
811 early_platform_add_devices(sh7724_early_devices,
812 ARRAY_SIZE(sh7724_early_devices));
815 #define RAMCR_CACHE_L2FC 0x0002
816 #define RAMCR_CACHE_L2E 0x0001
817 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
819 void l2_cache_init(void)
821 /* Enable L2 cache */
822 __raw_writel(L2_CACHE_ENABLE, RAMCR);
830 /* interrupt sources */
831 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
833 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
834 _2DG_TRI, _2DG_INI, _2DG_CEI,
835 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
836 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
844 RTC_ATI, RTC_PRI, RTC_CUI,
845 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
846 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
848 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
850 MSIOF_MSIOFI0, MSIOF_MSIOFI1,
851 SPU_SPUI0, SPU_SPUI1,
855 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
856 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
861 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
865 MMC_MMC2I, MMC_MMC3I,
867 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
869 /* interrupt groups */
870 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
871 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
874 static struct intc_vect vectors[] __initdata = {
875 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
876 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
877 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
878 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
880 INTC_VECT(DMAC1A_DEI0, 0x700),
881 INTC_VECT(DMAC1A_DEI1, 0x720),
882 INTC_VECT(DMAC1A_DEI2, 0x740),
883 INTC_VECT(DMAC1A_DEI3, 0x760),
885 INTC_VECT(_2DG_TRI, 0x780),
886 INTC_VECT(_2DG_INI, 0x7A0),
887 INTC_VECT(_2DG_CEI, 0x7C0),
889 INTC_VECT(DMAC0A_DEI0, 0x800),
890 INTC_VECT(DMAC0A_DEI1, 0x820),
891 INTC_VECT(DMAC0A_DEI2, 0x840),
892 INTC_VECT(DMAC0A_DEI3, 0x860),
894 INTC_VECT(VIO_CEU0, 0x880),
895 INTC_VECT(VIO_BEU0, 0x8A0),
896 INTC_VECT(VIO_VEU1, 0x8C0),
897 INTC_VECT(VIO_VOU, 0x8E0),
899 INTC_VECT(SCIFA3, 0x900),
900 INTC_VECT(VPU, 0x980),
901 INTC_VECT(TPU, 0x9A0),
902 INTC_VECT(CEU1, 0x9E0),
903 INTC_VECT(BEU1, 0xA00),
904 INTC_VECT(USB0, 0xA20),
905 INTC_VECT(USB1, 0xA40),
906 INTC_VECT(ATAPI, 0xA60),
908 INTC_VECT(RTC_ATI, 0xA80),
909 INTC_VECT(RTC_PRI, 0xAA0),
910 INTC_VECT(RTC_CUI, 0xAC0),
912 INTC_VECT(DMAC1B_DEI4, 0xB00),
913 INTC_VECT(DMAC1B_DEI5, 0xB20),
914 INTC_VECT(DMAC1B_DADERR, 0xB40),
916 INTC_VECT(DMAC0B_DEI4, 0xB80),
917 INTC_VECT(DMAC0B_DEI5, 0xBA0),
918 INTC_VECT(DMAC0B_DADERR, 0xBC0),
920 INTC_VECT(KEYSC, 0xBE0),
921 INTC_VECT(SCIF_SCIF0, 0xC00),
922 INTC_VECT(SCIF_SCIF1, 0xC20),
923 INTC_VECT(SCIF_SCIF2, 0xC40),
924 INTC_VECT(VEU0, 0xC60),
925 INTC_VECT(MSIOF_MSIOFI0, 0xC80),
926 INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
927 INTC_VECT(SPU_SPUI0, 0xCC0),
928 INTC_VECT(SPU_SPUI1, 0xCE0),
929 INTC_VECT(SCIFA4, 0xD00),
931 INTC_VECT(ICB, 0xD20),
932 INTC_VECT(ETHI, 0xD60),
934 INTC_VECT(I2C1_ALI, 0xD80),
935 INTC_VECT(I2C1_TACKI, 0xDA0),
936 INTC_VECT(I2C1_WAITI, 0xDC0),
937 INTC_VECT(I2C1_DTEI, 0xDE0),
939 INTC_VECT(I2C0_ALI, 0xE00),
940 INTC_VECT(I2C0_TACKI, 0xE20),
941 INTC_VECT(I2C0_WAITI, 0xE40),
942 INTC_VECT(I2C0_DTEI, 0xE60),
944 INTC_VECT(SDHI0, 0xE80),
945 INTC_VECT(SDHI0, 0xEA0),
946 INTC_VECT(SDHI0, 0xEC0),
947 INTC_VECT(SDHI0, 0xEE0),
949 INTC_VECT(CMT, 0xF00),
950 INTC_VECT(TSIF, 0xF20),
951 INTC_VECT(FSI, 0xF80),
952 INTC_VECT(SCIFA5, 0xFA0),
954 INTC_VECT(TMU0_TUNI0, 0x400),
955 INTC_VECT(TMU0_TUNI1, 0x420),
956 INTC_VECT(TMU0_TUNI2, 0x440),
958 INTC_VECT(IRDA, 0x480),
960 INTC_VECT(SDHI1, 0x4E0),
961 INTC_VECT(SDHI1, 0x500),
962 INTC_VECT(SDHI1, 0x520),
964 INTC_VECT(JPU, 0x560),
965 INTC_VECT(_2DDMAC, 0x4A0),
967 INTC_VECT(MMC_MMC2I, 0x5A0),
968 INTC_VECT(MMC_MMC3I, 0x5C0),
970 INTC_VECT(LCDC, 0xF40),
972 INTC_VECT(TMU1_TUNI0, 0x920),
973 INTC_VECT(TMU1_TUNI1, 0x940),
974 INTC_VECT(TMU1_TUNI2, 0x960),
977 static struct intc_group groups[] __initdata = {
978 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
979 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
980 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
981 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
982 INTC_GROUP(USB, USB0, USB1),
983 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
984 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
985 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
986 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
987 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
988 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
989 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
992 static struct intc_mask_reg mask_registers[] __initdata = {
993 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
994 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
995 0, DISABLED, ENABLED, ENABLED } },
996 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
997 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
998 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
999 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
1000 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
1001 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
1002 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
1003 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
1004 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
1005 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
1006 JPU, 0, 0, LCDC } },
1007 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
1008 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
1009 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
1010 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
1011 { 0, 0, ICB, SCIFA4,
1012 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
1013 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
1014 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
1015 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
1016 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
1017 { DISABLED, DISABLED, ENABLED, ENABLED,
1018 0, 0, SCIFA5, FSI } },
1019 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
1020 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
1021 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
1022 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
1023 0, RTC_CUI, RTC_PRI, RTC_ATI } },
1024 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
1025 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
1026 0, TPU, 0, TSIF } },
1027 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
1028 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
1029 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
1030 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1033 static struct intc_prio_reg prio_registers[] __initdata = {
1034 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
1035 TMU0_TUNI2, IRDA } },
1036 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
1037 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
1038 TMU1_TUNI2, SPU } },
1039 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } },
1040 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
1041 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } },
1042 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
1043 SCIF_SCIF2, VEU0 } },
1044 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1046 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } },
1047 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } },
1048 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } },
1049 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
1050 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
1051 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1054 static struct intc_sense_reg sense_registers[] __initdata = {
1055 { 0xa414001c, 16, 2, /* ICR1 */
1056 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1059 static struct intc_mask_reg ack_registers[] __initdata = {
1060 { 0xa4140024, 0, 8, /* INTREQ00 */
1061 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1064 static struct intc_desc intc_desc __initdata = {
1066 .force_enable = ENABLED,
1067 .force_disable = DISABLED,
1068 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
1069 prio_registers, sense_registers, ack_registers),
1072 void __init plat_irq_setup(void)
1074 register_intc_controller(&intc_desc);
1079 unsigned long mmselr;
1080 unsigned long cs0bcr;
1081 unsigned long cs4bcr;
1082 unsigned long cs5abcr;
1083 unsigned long cs5bbcr;
1084 unsigned long cs6abcr;
1085 unsigned long cs6bbcr;
1086 unsigned long cs4wcr;
1087 unsigned long cs5awcr;
1088 unsigned long cs5bwcr;
1089 unsigned long cs6awcr;
1090 unsigned long cs6bwcr;
1092 unsigned short ipra;
1093 unsigned short iprb;
1094 unsigned short iprc;
1095 unsigned short iprd;
1096 unsigned short ipre;
1097 unsigned short iprf;
1098 unsigned short iprg;
1099 unsigned short iprh;
1100 unsigned short ipri;
1101 unsigned short iprj;
1102 unsigned short iprk;
1103 unsigned short iprl;
1114 unsigned char imr10;
1115 unsigned char imr11;
1116 unsigned char imr12;
1118 unsigned short rwtcnt;
1119 unsigned short rwtcsr;
1121 unsigned long irdaclk;
1122 unsigned long spuclk;
1123 } sh7724_rstandby_state;
1125 static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb,
1126 unsigned long flags, void *unused)
1128 if (!(flags & SUSP_SH_RSTANDBY))
1132 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */
1133 sh7724_rstandby_state.mmselr |= 0xa5a50000;
1134 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */
1135 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */
1136 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */
1137 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */
1138 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */
1139 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */
1140 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */
1141 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */
1142 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */
1143 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */
1144 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */
1147 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */
1148 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */
1149 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */
1150 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */
1151 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */
1152 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */
1153 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */
1154 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */
1155 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */
1156 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */
1157 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */
1158 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */
1159 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */
1160 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */
1161 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */
1162 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */
1163 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */
1164 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */
1165 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */
1166 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */
1167 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */
1168 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */
1169 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */
1170 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */
1171 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */
1174 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */
1175 sh7724_rstandby_state.rwtcnt |= 0x5a00;
1176 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */
1177 sh7724_rstandby_state.rwtcsr |= 0xa500;
1178 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
1181 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */
1182 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */
1187 static int sh7724_post_sleep_notifier_call(struct notifier_block *nb,
1188 unsigned long flags, void *unused)
1190 if (!(flags & SUSP_SH_RSTANDBY))
1194 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */
1195 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */
1196 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */
1197 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */
1198 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */
1199 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */
1200 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */
1201 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */
1202 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */
1203 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */
1204 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */
1205 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */
1208 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */
1209 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */
1210 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */
1211 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */
1212 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */
1213 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */
1214 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */
1215 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */
1216 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */
1217 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */
1218 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */
1219 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */
1220 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */
1221 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */
1222 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */
1223 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */
1224 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */
1225 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */
1226 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */
1227 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */
1228 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */
1229 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */
1230 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */
1231 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */
1232 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */
1235 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */
1236 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */
1239 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */
1240 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */
1245 static struct notifier_block sh7724_pre_sleep_notifier = {
1246 .notifier_call = sh7724_pre_sleep_notifier_call,
1247 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU),
1250 static struct notifier_block sh7724_post_sleep_notifier = {
1251 .notifier_call = sh7724_post_sleep_notifier_call,
1252 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU),
1255 static int __init sh7724_sleep_setup(void)
1257 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list,
1258 &sh7724_pre_sleep_notifier);
1260 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list,
1261 &sh7724_post_sleep_notifier);
1264 arch_initcall(sh7724_sleep_setup);