4 * Copyright (C) 2007 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
16 static struct plat_sci_port sci_platform_data[] = {
18 .mapbase = 0xffc30000,
19 .flags = UPF_BOOT_AUTOCONF,
21 .irqs = { 40, 41, 43, 42 },
23 .mapbase = 0xffc40000,
24 .flags = UPF_BOOT_AUTOCONF,
26 .irqs = { 44, 45, 47, 46 },
28 .mapbase = 0xffc50000,
29 .flags = UPF_BOOT_AUTOCONF,
31 .irqs = { 48, 49, 51, 50 },
33 .mapbase = 0xffc60000,
34 .flags = UPF_BOOT_AUTOCONF,
36 .irqs = { 52, 53, 55, 54 },
42 static struct platform_device sci_device = {
46 .platform_data = sci_platform_data,
50 static struct platform_device *shx3_devices[] __initdata = {
54 static int __init shx3_devices_setup(void)
56 return platform_add_devices(shx3_devices,
57 ARRAY_SIZE(shx3_devices));
59 __initcall(shx3_devices_setup);
64 /* interrupt sources */
65 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
66 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
67 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
68 IRL_HHLL, IRL_HHLH, IRL_HHHL,
69 IRQ0, IRQ1, IRQ2, IRQ3,
71 TMU0, TMU1, TMU2, TMU3, TMU4, TMU5,
72 PCII0, PCII1, PCII2, PCII3, PCII4,
73 PCII5, PCII6, PCII7, PCII8, PCII9,
74 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
75 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
76 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
77 SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI,
78 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
79 DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
81 DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
82 DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
83 IIC, VIN0, VIN1, VCORE0, ATAPI,
84 DTU0_TEND, DTU0_AE, DTU0_TMISS,
85 DTU1_TEND, DTU1_AE, DTU1_TMISS,
86 DTU2_TEND, DTU2_AE, DTU2_TMISS,
87 DTU3_TEND, DTU3_AE, DTU3_TMISS,
89 GPIO0, GPIO1, GPIO2, GPIO3,
92 /* interrupt groups */
93 IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
94 DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3,
97 static struct intc_vect vectors[] = {
98 INTC_VECT(HUDII, 0x3e0),
99 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
100 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460),
101 INTC_VECT(TMU4, 0x480), INTC_VECT(TMU5, 0x4a0),
102 INTC_VECT(PCII0, 0x500), INTC_VECT(PCII1, 0x520),
103 INTC_VECT(PCII2, 0x540), INTC_VECT(PCII3, 0x560),
104 INTC_VECT(PCII4, 0x580), INTC_VECT(PCII5, 0x5a0),
105 INTC_VECT(PCII6, 0x5c0), INTC_VECT(PCII7, 0x5e0),
106 INTC_VECT(PCII8, 0x600), INTC_VECT(PCII9, 0x620),
107 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
108 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
109 INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
110 INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
111 INTC_VECT(SCIF2_ERI, 0x800), INTC_VECT(SCIF2_RXI, 0x820),
112 INTC_VECT(SCIF2_BRI, 0x840), INTC_VECT(SCIF2_TXI, 0x860),
113 INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0),
114 INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0),
115 INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920),
116 INTC_VECT(DMAC0_DMINT2, 0x940), INTC_VECT(DMAC0_DMINT3, 0x960),
117 INTC_VECT(DMAC0_DMINT4, 0x980), INTC_VECT(DMAC0_DMINT5, 0x9a0),
118 INTC_VECT(DMAC0_DMAE, 0x9c0),
119 INTC_VECT(DU, 0x9e0),
120 INTC_VECT(DMAC1_DMINT6, 0xa00), INTC_VECT(DMAC1_DMINT7, 0xa20),
121 INTC_VECT(DMAC1_DMINT8, 0xa40), INTC_VECT(DMAC1_DMINT9, 0xa60),
122 INTC_VECT(DMAC1_DMINT10, 0xa80), INTC_VECT(DMAC1_DMINT11, 0xaa0),
123 INTC_VECT(DMAC1_DMAE, 0xac0),
124 INTC_VECT(IIC, 0xae0),
125 INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20),
126 INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60),
127 INTC_VECT(DTU0_TEND, 0xc00), INTC_VECT(DTU0_AE, 0xc20),
128 INTC_VECT(DTU0_TMISS, 0xc40),
129 INTC_VECT(DTU1_TEND, 0xc60), INTC_VECT(DTU1_AE, 0xc80),
130 INTC_VECT(DTU1_TMISS, 0xca0),
131 INTC_VECT(DTU2_TEND, 0xcc0), INTC_VECT(DTU2_AE, 0xce0),
132 INTC_VECT(DTU2_TMISS, 0xd00),
133 INTC_VECT(DTU3_TEND, 0xd20), INTC_VECT(DTU3_AE, 0xd40),
134 INTC_VECT(DTU3_TMISS, 0xd60),
135 INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20),
136 INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60),
137 INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0),
138 INTC_VECT(PAM, 0xec0), INTC_VECT(IRM, 0xee0),
141 static struct intc_group groups[] = {
142 INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
143 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
144 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
145 IRL_HHLL, IRL_HHLH, IRL_HHHL),
146 INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9),
147 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
148 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
149 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
150 INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI),
151 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
152 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
153 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
154 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
155 INTC_GROUP(DTU0, DTU0_TEND, DTU0_AE, DTU0_TMISS),
156 INTC_GROUP(DTU1, DTU1_TEND, DTU1_AE, DTU1_TMISS),
157 INTC_GROUP(DTU2, DTU2_TEND, DTU2_AE, DTU2_TMISS),
158 INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS),
161 static struct intc_prio priorities[] = {
168 static struct intc_mask_reg mask_registers[] = {
169 { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
170 { IRQ0, IRQ1, IRQ2, IRQ3 } },
171 { 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */
173 { 0xfe410820, 0xfe410850, 32, /* CnINT2MSK0 / CnINT2MSKCLR0 */
174 { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
175 DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
176 0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
177 0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } },
178 { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
179 { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
180 PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2,
181 PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11,
182 DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7,
183 DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4,
184 DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } },
185 { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
186 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
187 SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI,
188 SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI,
189 SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI,
190 SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } },
193 static struct intc_prio_reg prio_registers[] = {
194 { 0xfe410010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
196 { 0xfe410800, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
197 TMU3, TMU2, TMU1, TMU0 } },
198 { 0xfe410804, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0,
199 SCIF3, SCIF2, SCIF1, SCIF0 } },
200 { 0xfe410808, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0, PCII56789, PCII4,
201 PCII3, PCII2, PCII1, PCII0 } },
202 { 0xfe41080c, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0,
203 VIN1, VIN0, IIC, DU} },
204 { 0xfe410810, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3,
205 GPIO2, GPIO1, GPIO0, IRM } },
208 static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups, priorities,
209 mask_registers, prio_registers, NULL);
211 /* Support for external interrupt pins in IRQ mode */
212 static struct intc_vect vectors_irq[] = {
213 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
214 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
217 static struct intc_sense_reg sense_registers[] = {
218 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
221 static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups,
222 priorities, mask_registers, prio_registers,
225 /* External interrupt pins in IRL mode */
226 static struct intc_vect vectors_irl[] = {
227 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
228 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
229 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
230 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
231 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
232 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
233 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
234 INTC_VECT(IRL_HHHL, 0x3c0),
237 static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
238 priorities, mask_registers, prio_registers, NULL);
240 void __init plat_irq_setup_pins(int mode)
244 register_intc_controller(&intc_desc_irq);
246 case IRQ_MODE_IRL3210:
247 register_intc_controller(&intc_desc_irl);
254 void __init plat_irq_setup(void)
256 register_intc_controller(&intc_desc);
259 void __init plat_mem_setup(void)
261 unsigned int nid = 1;
263 /* Register CPU#0 URAM space as Node 1 */
264 setup_bootmem_node(nid++, 0x145f0000, 0x14610000); /* CPU0 */
268 setup_bootmem_node(nid++, 0x14df0000, 0x14e10000); /* CPU1 */
269 setup_bootmem_node(nid++, 0x155f0000, 0x15610000); /* CPU2 */
270 setup_bootmem_node(nid++, 0x15df0000, 0x15e10000); /* CPU3 */
273 setup_bootmem_node(nid++, 0x16000000, 0x16020000); /* CSM */