4 * Copyright (C) 2007 - 2010 Paul Mundt
5 * Copyright (C) 2007 Magnus Damm
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/init.h>
12 #include <linux/cpumask.h>
13 #include <linux/smp.h>
14 #include <linux/interrupt.h>
17 #define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
18 #define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
20 #define STBCR_MSTP 0x00000001
21 #define STBCR_RESET 0x00000002
22 #define STBCR_LTSLP 0x80000000
24 static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
26 unsigned int message = (unsigned int)(long)arg;
27 unsigned int cpu = hard_smp_processor_id();
28 unsigned int offs = 4 * cpu;
31 x = __raw_readl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
32 x &= (1 << (message << 2));
33 __raw_writel(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
35 smp_message_recv(message);
40 static void shx3_smp_setup(void)
45 init_cpu_possible(cpumask_of(cpu));
47 /* Enable light sleep for the boot CPU */
48 __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu));
50 __cpu_number_map[0] = 0;
51 __cpu_logical_map[0] = 0;
54 * Do this stupidly for now.. we don't have an easy way to probe
55 * for the total number of cores.
57 for (i = 1, num = 0; i < NR_CPUS; i++) {
58 set_cpu_possible(i, true);
59 __cpu_number_map[i] = ++num;
60 __cpu_logical_map[num] = i;
63 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
66 static void shx3_prepare_cpus(unsigned int max_cpus)
72 BUILD_BUG_ON(SMP_MSG_NR >= 8);
74 for (i = 0; i < SMP_MSG_NR; i++)
75 request_irq(104 + i, ipi_interrupt_handler,
76 IRQF_DISABLED | IRQF_PERCPU, "IPI", (void *)(long)i);
78 for (i = 0; i < max_cpus; i++)
79 set_cpu_present(i, true);
82 static void shx3_start_cpu(unsigned int cpu, unsigned long entry_point)
84 if (__in_29bit_mode())
85 __raw_writel(entry_point, RESET_REG(cpu));
87 __raw_writel(virt_to_phys(entry_point), RESET_REG(cpu));
89 if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
90 __raw_writel(STBCR_MSTP, STBCR_REG(cpu));
92 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
95 /* Start up secondary processor by sending a reset */
96 __raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu));
99 static unsigned int shx3_smp_processor_id(void)
101 return __raw_readl(0xff000048); /* CPIDR */
104 static void shx3_send_ipi(unsigned int cpu, unsigned int message)
106 unsigned long addr = 0xfe410070 + (cpu * 4);
110 __raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
113 struct plat_smp_ops shx3_smp_ops = {
114 .smp_setup = shx3_smp_setup,
115 .prepare_cpus = shx3_prepare_cpus,
116 .start_cpu = shx3_start_cpu,
117 .smp_processor_id = shx3_smp_processor_id,
118 .send_ipi = shx3_send_ipi,