arch/sh/kernel/traps_32.c

   1 /*
   2  * 'traps.c' handles hardware traps and faults after we have saved some
   3  * state in 'entry.S'.
   4  *
   5  *  SuperH version: Copyright (C) 1999 Niibe Yutaka
   6  *                  Copyright (C) 2000 Philipp Rumpf
   7  *                  Copyright (C) 2000 David Howells
   8  *                  Copyright (C) 2002 - 2010 Paul Mundt
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/hardirq.h>
  17 #include <linux/init.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/module.h>
  20 #include <linux/kallsyms.h>
  21 #include <linux/io.h>
  22 #include <linux/bug.h>
  23 #include <linux/debug_locks.h>
  24 #include <linux/kdebug.h>
  25 #include <linux/kexec.h>
  26 #include <linux/limits.h>
  27 #include <linux/sysfs.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/perf_event.h>
  30 #include <asm/alignment.h>
  31 #include <asm/fpu.h>
  32 #include <asm/kprobes.h>
  33 #include <asm/traps.h>
  34 #include <asm/bl_bit.h>
  35
  36 #ifdef CONFIG_CPU_SH2
  37 # define TRAP_RESERVED_INST     4
  38 # define TRAP_ILLEGAL_SLOT_INST 6
  39 # define TRAP_ADDRESS_ERROR     9
  40 # ifdef CONFIG_CPU_SH2A
  41 #  define TRAP_UBC              12
  42 #  define TRAP_FPU_ERROR        13
  43 #  define TRAP_DIVZERO_ERROR    17
  44 #  define TRAP_DIVOVF_ERROR     18
  45 # endif
  46 #else
  47 #define TRAP_RESERVED_INST      12
  48 #define TRAP_ILLEGAL_SLOT_INST  13
  49 #endif
  50
  51 static DEFINE_SPINLOCK(die_lock);
  52
  53 void die(const char * str, struct pt_regs * regs, long err)
  54 {
  55         static int die_counter;
  56
  57         oops_enter();
  58
  59         spin_lock_irq(&die_lock);
  60         console_verbose();
  61         bust_spinlocks(1);
  62
  63         printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
  64         print_modules();
  65         show_regs(regs);
  66
  67         printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
  68                         task_pid_nr(current), task_stack_page(current) + 1);
  69
  70         if (!user_mode(regs) || in_interrupt())
  71                 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
  72                          (unsigned long)task_stack_page(current));
  73
  74         notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
  75
  76         bust_spinlocks(0);
  77         add_taint(TAINT_DIE);
  78         spin_unlock_irq(&die_lock);
  79         oops_exit();
  80
  81         if (kexec_should_crash(current))
  82                 crash_kexec(regs);
  83
  84         if (in_interrupt())
  85                 panic("Fatal exception in interrupt");
  86
  87         if (panic_on_oops)
  88                 panic("Fatal exception");
  89
  90         do_exit(SIGSEGV);
  91 }
  92
  93 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
  94                                  long err)
  95 {
  96         if (!user_mode(regs))
  97                 die(str, regs, err);
  98 }
  99
 100 /*
 101  * try and fix up kernelspace address errors
 102  * - userspace errors just cause EFAULT to be returned, resulting in SEGV
 103  * - kernel/userspace interfaces cause a jump to an appropriate handler
 104  * - other kernel errors are bad
 105  */
 106 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
 107 {
 108         if (!user_mode(regs)) {
 109                 const struct exception_table_entry *fixup;
 110                 fixup = search_exception_tables(regs->pc);
 111                 if (fixup) {
 112                         regs->pc = fixup->fixup;
 113                         return;
 114                 }
 115
 116                 die(str, regs, err);
 117         }
 118 }
 119
 120 static inline void sign_extend(unsigned int count, unsigned char *dst)
 121 {
 122 #ifdef __LITTLE_ENDIAN__
 123         if ((count == 1) && dst[0] & 0x80) {
 124                 dst[1] = 0xff;
 125                 dst[2] = 0xff;
 126                 dst[3] = 0xff;
 127         }
 128         if ((count == 2) && dst[1] & 0x80) {
 129                 dst[2] = 0xff;
 130                 dst[3] = 0xff;
 131         }
 132 #else
 133         if ((count == 1) && dst[3] & 0x80) {
 134                 dst[2] = 0xff;
 135                 dst[1] = 0xff;
 136                 dst[0] = 0xff;
 137         }
 138         if ((count == 2) && dst[2] & 0x80) {
 139                 dst[1] = 0xff;
 140                 dst[0] = 0xff;
 141         }
 142 #endif
 143 }
 144
 145 static struct mem_access user_mem_access = {
 146         copy_from_user,
 147         copy_to_user,
 148 };
 149
 150 /*
 151  * handle an instruction that does an unaligned memory access by emulating the
 152  * desired behaviour
 153  * - note that PC _may not_ point to the faulting instruction
 154  *   (if that instruction is in a branch delay slot)
 155  * - return 0 if emulation okay, -EFAULT on existential error
 156  */
 157 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
 158                                 struct mem_access *ma)
 159 {
 160         int ret, index, count;
 161         unsigned long *rm, *rn;
 162         unsigned char *src, *dst;
 163         unsigned char __user *srcu, *dstu;
 164
 165         index = (instruction>>8)&15;    /* 0x0F00 */
 166         rn = &regs->regs[index];
 167
 168         index = (instruction>>4)&15;    /* 0x00F0 */
 169         rm = &regs->regs[index];
 170
 171         count = 1<<(instruction&3);
 172
 173         switch (count) {
 174         case 1: inc_unaligned_byte_access(); break;
 175         case 2: inc_unaligned_word_access(); break;
 176         case 4: inc_unaligned_dword_access(); break;
 177         case 8: inc_unaligned_multi_access(); break;
 178         }
 179
 180         ret = -EFAULT;
 181         switch (instruction>>12) {
 182         case 0: /* mov.[bwl] to/from memory via r0+rn */
 183                 if (instruction & 8) {
 184                         /* from memory */
 185                         srcu = (unsigned char __user *)*rm;
 186                         srcu += regs->regs[0];
 187                         dst = (unsigned char *)rn;
 188                         *(unsigned long *)dst = 0;
 189
 190 #if !defined(__LITTLE_ENDIAN__)
 191                         dst += 4-count;
 192 #endif
 193                         if (ma->from(dst, srcu, count))
 194                                 goto fetch_fault;
 195
 196                         sign_extend(count, dst);
 197                 } else {
 198                         /* to memory */
 199                         src = (unsigned char *)rm;
 200 #if !defined(__LITTLE_ENDIAN__)
 201                         src += 4-count;
 202 #endif
 203                         dstu = (unsigned char __user *)*rn;
 204                         dstu += regs->regs[0];
 205
 206                         if (ma->to(dstu, src, count))
 207                                 goto fetch_fault;
 208                 }
 209                 ret = 0;
 210                 break;
 211
 212         case 1: /* mov.l Rm,@(disp,Rn) */
 213                 src = (unsigned char*) rm;
 214                 dstu = (unsigned char __user *)*rn;
 215                 dstu += (instruction&0x000F)<<2;
 216
 217                 if (ma->to(dstu, src, 4))
 218                         goto fetch_fault;
 219                 ret = 0;
 220                 break;
 221
 222         case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
 223                 if (instruction & 4)
 224                         *rn -= count;
 225                 src = (unsigned char*) rm;
 226                 dstu = (unsigned char __user *)*rn;
 227 #if !defined(__LITTLE_ENDIAN__)
 228                 src += 4-count;
 229 #endif
 230                 if (ma->to(dstu, src, count))
 231                         goto fetch_fault;
 232                 ret = 0;
 233                 break;
 234
 235         case 5: /* mov.l @(disp,Rm),Rn */
 236                 srcu = (unsigned char __user *)*rm;
 237                 srcu += (instruction & 0x000F) << 2;
 238                 dst = (unsigned char *)rn;
 239                 *(unsigned long *)dst = 0;
 240
 241                 if (ma->from(dst, srcu, 4))
 242                         goto fetch_fault;
 243                 ret = 0;
 244                 break;
 245
 246         case 6: /* mov.[bwl] from memory, possibly with post-increment */
 247                 srcu = (unsigned char __user *)*rm;
 248                 if (instruction & 4)
 249                         *rm += count;
 250                 dst = (unsigned char*) rn;
 251                 *(unsigned long*)dst = 0;
 252
 253 #if !defined(__LITTLE_ENDIAN__)
 254                 dst += 4-count;
 255 #endif
 256                 if (ma->from(dst, srcu, count))
 257                         goto fetch_fault;
 258                 sign_extend(count, dst);
 259                 ret = 0;
 260                 break;
 261
 262         case 8:
 263                 switch ((instruction&0xFF00)>>8) {
 264                 case 0x81: /* mov.w R0,@(disp,Rn) */
 265                         src = (unsigned char *) &regs->regs[0];
 266 #if !defined(__LITTLE_ENDIAN__)
 267                         src += 2;
 268 #endif
 269                         dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
 270                         dstu += (instruction & 0x000F) << 1;
 271
 272                         if (ma->to(dstu, src, 2))
 273                                 goto fetch_fault;
 274                         ret = 0;
 275                         break;
 276
 277                 case 0x85: /* mov.w @(disp,Rm),R0 */
 278                         srcu = (unsigned char __user *)*rm;
 279                         srcu += (instruction & 0x000F) << 1;
 280                         dst = (unsigned char *) &regs->regs[0];
 281                         *(unsigned long *)dst = 0;
 282
 283 #if !defined(__LITTLE_ENDIAN__)
 284                         dst += 2;
 285 #endif
 286                         if (ma->from(dst, srcu, 2))
 287                                 goto fetch_fault;
 288                         sign_extend(2, dst);
 289                         ret = 0;
 290                         break;
 291                 }
 292                 break;
 293
 294         case 9: /* mov.w @(disp,PC),Rn */
 295                 srcu = (unsigned char __user *)regs->pc;
 296                 srcu += 4;
 297                 srcu += (instruction & 0x00FF) << 1;
 298                 dst = (unsigned char *)rn;
 299                 *(unsigned long *)dst = 0;
 300
 301 #if !defined(__LITTLE_ENDIAN__)
 302                 dst += 2;
 303 #endif
 304
 305                 if (ma->from(dst, srcu, 2))
 306                         goto fetch_fault;
 307                 sign_extend(2, dst);
 308                 ret = 0;
 309                 break;
 310
 311         case 0xd: /* mov.l @(disp,PC),Rn */
 312                 srcu = (unsigned char __user *)(regs->pc & ~0x3);
 313                 srcu += 4;
 314                 srcu += (instruction & 0x00FF) << 2;
 315                 dst = (unsigned char *)rn;
 316                 *(unsigned long *)dst = 0;
 317
 318                 if (ma->from(dst, srcu, 4))
 319                         goto fetch_fault;
 320                 ret = 0;
 321                 break;
 322         }
 323         return ret;
 324
 325  fetch_fault:
 326         /* Argh. Address not only misaligned but also non-existent.
 327          * Raise an EFAULT and see if it's trapped
 328          */
 329         die_if_no_fixup("Fault in unaligned fixup", regs, 0);
 330         return -EFAULT;
 331 }
 332
 333 /*
 334  * emulate the instruction in the delay slot
 335  * - fetches the instruction from PC+2
 336  */
 337 static inline int handle_delayslot(struct pt_regs *regs,
 338                                    insn_size_t old_instruction,
 339                                    struct mem_access *ma)
 340 {
 341         insn_size_t instruction;
 342         void __user *addr = (void __user *)(regs->pc +
 343                 instruction_size(old_instruction));
 344
 345         if (copy_from_user(&instruction, addr, sizeof(instruction))) {
 346                 /* the instruction-fetch faulted */
 347                 if (user_mode(regs))
 348                         return -EFAULT;
 349
 350                 /* kernel */
 351                 die("delay-slot-insn faulting in handle_unaligned_delayslot",
 352                     regs, 0);
 353         }
 354
 355         return handle_unaligned_ins(instruction, regs, ma);
 356 }
 357
 358 /*
 359  * handle an instruction that does an unaligned memory access
 360  * - have to be careful of branch delay-slot instructions that fault
 361  *  SH3:
 362  *   - if the branch would be taken PC points to the branch
 363  *   - if the branch would not be taken, PC points to delay-slot
 364  *  SH4:
 365  *   - PC always points to delayed branch
 366  * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
 367  */
 368
 369 /* Macros to determine offset from current PC for branch instructions */
 370 /* Explicit type coercion is used to force sign extension where needed */
 371 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
 372 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
 373
 374 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
 375                             struct mem_access *ma, int expected,
 376                             unsigned long address)
 377 {
 378         u_int rm;
 379         int ret, index;
 380
 381         /*
 382          * XXX: We can't handle mixed 16/32-bit instructions yet
 383          */
 384         if (instruction_size(instruction) != 2)
 385                 return -EINVAL;
 386
 387         index = (instruction>>8)&15;    /* 0x0F00 */
 388         rm = regs->regs[index];
 389
 390         /*
 391          * Log the unexpected fixups, and then pass them on to perf.
 392          *
 393          * We intentionally don't report the expected cases to perf as
 394          * otherwise the trapped I/O case will skew the results too much
 395          * to be useful.
 396          */
 397         if (!expected) {
 398                 unaligned_fixups_notify(current, instruction, regs);
 399                 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1,
 400                               regs, address);
 401         }
 402
 403         ret = -EFAULT;
 404         switch (instruction&0xF000) {
 405         case 0x0000:
 406                 if (instruction==0x000B) {
 407                         /* rts */
 408                         ret = handle_delayslot(regs, instruction, ma);
 409                         if (ret==0)
 410                                 regs->pc = regs->pr;
 411                 }
 412                 else if ((instruction&0x00FF)==0x0023) {
 413                         /* braf @Rm */
 414                         ret = handle_delayslot(regs, instruction, ma);
 415                         if (ret==0)
 416                                 regs->pc += rm + 4;
 417                 }
 418                 else if ((instruction&0x00FF)==0x0003) {
 419                         /* bsrf @Rm */
 420                         ret = handle_delayslot(regs, instruction, ma);
 421                         if (ret==0) {
 422                                 regs->pr = regs->pc + 4;
 423                                 regs->pc += rm + 4;
 424                         }
 425                 }
 426                 else {
 427                         /* mov.[bwl] to/from memory via r0+rn */
 428                         goto simple;
 429                 }
 430                 break;
 431
 432         case 0x1000: /* mov.l Rm,@(disp,Rn) */
 433                 goto simple;
 434
 435         case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
 436                 goto simple;
 437
 438         case 0x4000:
 439                 if ((instruction&0x00FF)==0x002B) {
 440                         /* jmp @Rm */
 441                         ret = handle_delayslot(regs, instruction, ma);
 442                         if (ret==0)
 443                                 regs->pc = rm;
 444                 }
 445                 else if ((instruction&0x00FF)==0x000B) {
 446                         /* jsr @Rm */
 447                         ret = handle_delayslot(regs, instruction, ma);
 448                         if (ret==0) {
 449                                 regs->pr = regs->pc + 4;
 450                                 regs->pc = rm;
 451                         }
 452                 }
 453                 else {
 454                         /* mov.[bwl] to/from memory via r0+rn */
 455                         goto simple;
 456                 }
 457                 break;
 458
 459         case 0x5000: /* mov.l @(disp,Rm),Rn */
 460                 goto simple;
 461
 462         case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
 463                 goto simple;
 464
 465         case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
 466                 switch (instruction&0x0F00) {
 467                 case 0x0100: /* mov.w R0,@(disp,Rm) */
 468                         goto simple;
 469                 case 0x0500: /* mov.w @(disp,Rm),R0 */
 470                         goto simple;
 471                 case 0x0B00: /* bf   lab - no delayslot*/
 472                         ret = 0;
 473                         break;
 474                 case 0x0F00: /* bf/s lab */
 475                         ret = handle_delayslot(regs, instruction, ma);
 476                         if (ret==0) {
 477 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 478                                 if ((regs->sr & 0x00000001) != 0)
 479                                         regs->pc += 4; /* next after slot */
 480                                 else
 481 #endif
 482                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 483                         }
 484                         break;
 485                 case 0x0900: /* bt   lab - no delayslot */
 486                         ret = 0;
 487                         break;
 488                 case 0x0D00: /* bt/s lab */
 489                         ret = handle_delayslot(regs, instruction, ma);
 490                         if (ret==0) {
 491 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 492                                 if ((regs->sr & 0x00000001) == 0)
 493                                         regs->pc += 4; /* next after slot */
 494                                 else
 495 #endif
 496                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 497                         }
 498                         break;
 499                 }
 500                 break;
 501
 502         case 0x9000: /* mov.w @(disp,Rm),Rn */
 503                 goto simple;
 504
 505         case 0xA000: /* bra label */
 506                 ret = handle_delayslot(regs, instruction, ma);
 507                 if (ret==0)
 508                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 509                 break;
 510
 511         case 0xB000: /* bsr label */
 512                 ret = handle_delayslot(regs, instruction, ma);
 513                 if (ret==0) {
 514                         regs->pr = regs->pc + 4;
 515                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 516                 }
 517                 break;
 518
 519         case 0xD000: /* mov.l @(disp,Rm),Rn */
 520                 goto simple;
 521         }
 522         return ret;
 523
 524         /* handle non-delay-slot instruction */
 525  simple:
 526         ret = handle_unaligned_ins(instruction, regs, ma);
 527         if (ret==0)
 528                 regs->pc += instruction_size(instruction);
 529         return ret;
 530 }
 531
 532 /*
 533  * Handle various address error exceptions:
 534  *  - instruction address error:
 535  *       misaligned PC
 536  *       PC >= 0x80000000 in user mode
 537  *  - data address error (read and write)
 538  *       misaligned data access
 539  *       access to >= 0x80000000 is user mode
 540  * Unfortuntaly we can't distinguish between instruction address error
 541  * and data address errors caused by read accesses.
 542  */
 543 asmlinkage void do_address_error(struct pt_regs *regs,
 544                                  unsigned long writeaccess,
 545                                  unsigned long address)
 546 {
 547         unsigned long error_code = 0;
 548         mm_segment_t oldfs;
 549         siginfo_t info;
 550         insn_size_t instruction;
 551         int tmp;
 552
 553         /* Intentional ifdef */
 554 #ifdef CONFIG_CPU_HAS_SR_RB
 555         error_code = lookup_exception_vector();
 556 #endif
 557
 558         oldfs = get_fs();
 559
 560         if (user_mode(regs)) {
 561                 int si_code = BUS_ADRERR;
 562                 unsigned int user_action;
 563
 564                 local_irq_enable();
 565                 inc_unaligned_user_access();
 566
 567                 set_fs(USER_DS);
 568                 if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
 569                                    sizeof(instruction))) {
 570                         set_fs(oldfs);
 571                         goto uspace_segv;
 572                 }
 573                 set_fs(oldfs);
 574
 575                 /* shout about userspace fixups */
 576                 unaligned_fixups_notify(current, instruction, regs);
 577
 578                 user_action = unaligned_user_action();
 579                 if (user_action & UM_FIXUP)
 580                         goto fixup;
 581                 if (user_action & UM_SIGNAL)
 582                         goto uspace_segv;
 583                 else {
 584                         /* ignore */
 585                         regs->pc += instruction_size(instruction);
 586                         return;
 587                 }
 588
 589 fixup:
 590                 /* bad PC is not something we can fix */
 591                 if (regs->pc & 1) {
 592                         si_code = BUS_ADRALN;
 593                         goto uspace_segv;
 594                 }
 595
 596                 set_fs(USER_DS);
 597                 tmp = handle_unaligned_access(instruction, regs,
 598                                               &user_mem_access, 0,
 599                                               address);
 600                 set_fs(oldfs);
 601
 602                 if (tmp == 0)
 603                         return; /* sorted */
 604 uspace_segv:
 605                 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
 606                        "access (PC %lx PR %lx)\n", current->comm, regs->pc,
 607                        regs->pr);
 608
 609                 info.si_signo = SIGBUS;
 610                 info.si_errno = 0;
 611                 info.si_code = si_code;
 612                 info.si_addr = (void __user *)address;
 613                 force_sig_info(SIGBUS, &info, current);
 614         } else {
 615                 inc_unaligned_kernel_access();
 616
 617                 if (regs->pc & 1)
 618                         die("unaligned program counter", regs, error_code);
 619
 620                 set_fs(KERNEL_DS);
 621                 if (copy_from_user(&instruction, (void __user *)(regs->pc),
 622                                    sizeof(instruction))) {
 623                         /* Argh. Fault on the instruction itself.
 624                            This should never happen non-SMP
 625                         */
 626                         set_fs(oldfs);
 627                         die("insn faulting in do_address_error", regs, 0);
 628                 }
 629
 630                 unaligned_fixups_notify(current, instruction, regs);
 631
 632                 handle_unaligned_access(instruction, regs, &user_mem_access,
 633                                         0, address);
 634                 set_fs(oldfs);
 635         }
 636 }
 637
 638 #ifdef CONFIG_SH_DSP
 639 /*
 640  *      SH-DSP support gerg@snapgear.com.
 641  */
 642 int is_dsp_inst(struct pt_regs *regs)
 643 {
 644         unsigned short inst = 0;
 645
 646         /*
 647          * Safe guard if DSP mode is already enabled or we're lacking
 648          * the DSP altogether.
 649          */
 650         if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
 651                 return 0;
 652
 653         get_user(inst, ((unsigned short *) regs->pc));
 654
 655         inst &= 0xf000;
 656
 657         /* Check for any type of DSP or support instruction */
 658         if ((inst == 0xf000) || (inst == 0x4000))
 659                 return 1;
 660
 661         return 0;
 662 }
 663 #else
 664 #define is_dsp_inst(regs)       (0)
 665 #endif /* CONFIG_SH_DSP */
 666
 667 #ifdef CONFIG_CPU_SH2A
 668 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
 669                                 unsigned long r6, unsigned long r7,
 670                                 struct pt_regs __regs)
 671 {
 672         siginfo_t info;
 673
 674         switch (r4) {
 675         case TRAP_DIVZERO_ERROR:
 676                 info.si_code = FPE_INTDIV;
 677                 break;
 678         case TRAP_DIVOVF_ERROR:
 679                 info.si_code = FPE_INTOVF;
 680                 break;
 681         }
 682
 683         force_sig_info(SIGFPE, &info, current);
 684 }
 685 #endif
 686
 687 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
 688                                 unsigned long r6, unsigned long r7,
 689                                 struct pt_regs __regs)
 690 {
 691         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 692         unsigned long error_code;
 693         struct task_struct *tsk = current;
 694
 695 #ifdef CONFIG_SH_FPU_EMU
 696         unsigned short inst = 0;
 697         int err;
 698
 699         get_user(inst, (unsigned short*)regs->pc);
 700
 701         err = do_fpu_inst(inst, regs);
 702         if (!err) {
 703                 regs->pc += instruction_size(inst);
 704                 return;
 705         }
 706         /* not a FPU inst. */
 707 #endif
 708
 709 #ifdef CONFIG_SH_DSP
 710         /* Check if it's a DSP instruction */
 711         if (is_dsp_inst(regs)) {
 712                 /* Enable DSP mode, and restart instruction. */
 713                 regs->sr |= SR_DSP;
 714                 /* Save DSP mode */
 715                 tsk->thread.dsp_status.status |= SR_DSP;
 716                 return;
 717         }
 718 #endif
 719
 720         error_code = lookup_exception_vector();
 721
 722         local_irq_enable();
 723         force_sig(SIGILL, tsk);
 724         die_if_no_fixup("reserved instruction", regs, error_code);
 725 }
 726
 727 #ifdef CONFIG_SH_FPU_EMU
 728 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
 729 {
 730         /*
 731          * bfs: 8fxx: PC+=d*2+4;
 732          * bts: 8dxx: PC+=d*2+4;
 733          * bra: axxx: PC+=D*2+4;
 734          * bsr: bxxx: PC+=D*2+4  after PR=PC+4;
 735          * braf:0x23: PC+=Rn*2+4;
 736          * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
 737          * jmp: 4x2b: PC=Rn;
 738          * jsr: 4x0b: PC=Rn      after PR=PC+4;
 739          * rts: 000b: PC=PR;
 740          */
 741         if (((inst & 0xf000) == 0xb000)  ||     /* bsr */
 742             ((inst & 0xf0ff) == 0x0003)  ||     /* bsrf */
 743             ((inst & 0xf0ff) == 0x400b))        /* jsr */
 744                 regs->pr = regs->pc + 4;
 745
 746         if ((inst & 0xfd00) == 0x8d00) {        /* bfs, bts */
 747                 regs->pc += SH_PC_8BIT_OFFSET(inst);
 748                 return 0;
 749         }
 750
 751         if ((inst & 0xe000) == 0xa000) {        /* bra, bsr */
 752                 regs->pc += SH_PC_12BIT_OFFSET(inst);
 753                 return 0;
 754         }
 755
 756         if ((inst & 0xf0df) == 0x0003) {        /* braf, bsrf */
 757                 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
 758                 return 0;
 759         }
 760
 761         if ((inst & 0xf0df) == 0x400b) {        /* jmp, jsr */
 762                 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
 763                 return 0;
 764         }
 765
 766         if ((inst & 0xffff) == 0x000b) {        /* rts */
 767                 regs->pc = regs->pr;
 768                 return 0;
 769         }
 770
 771         return 1;
 772 }
 773 #endif
 774
 775 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
 776                                 unsigned long r6, unsigned long r7,
 777                                 struct pt_regs __regs)
 778 {
 779         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 780         unsigned long inst;
 781         struct task_struct *tsk = current;
 782
 783         if (kprobe_handle_illslot(regs->pc) == 0)
 784                 return;
 785
 786 #ifdef CONFIG_SH_FPU_EMU
 787         get_user(inst, (unsigned short *)regs->pc + 1);
 788         if (!do_fpu_inst(inst, regs)) {
 789                 get_user(inst, (unsigned short *)regs->pc);
 790                 if (!emulate_branch(inst, regs))
 791                         return;
 792                 /* fault in branch.*/
 793         }
 794         /* not a FPU inst. */
 795 #endif
 796
 797         inst = lookup_exception_vector();
 798
 799         local_irq_enable();
 800         force_sig(SIGILL, tsk);
 801         die_if_no_fixup("illegal slot instruction", regs, inst);
 802 }
 803
 804 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
 805                                    unsigned long r6, unsigned long r7,
 806                                    struct pt_regs __regs)
 807 {
 808         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 809         long ex;
 810
 811         ex = lookup_exception_vector();
 812         die_if_kernel("exception", regs, ex);
 813 }
 814
 815 void __cpuinit per_cpu_trap_init(void)
 816 {
 817         extern void *vbr_base;
 818
 819         /* NOTE: The VBR value should be at P1
 820            (or P2, virtural "fixed" address space).
 821            It's definitely should not in physical address.  */
 822
 823         asm volatile("ldc       %0, vbr"
 824                      : /* no output */
 825                      : "r" (&vbr_base)
 826                      : "memory");
 827
 828         /* disable exception blocking now when the vbr has been setup */
 829         clear_bl_bit();
 830 }
 831
 832 void *set_exception_table_vec(unsigned int vec, void *handler)
 833 {
 834         extern void *exception_handling_table[];
 835         void *old_handler;
 836
 837         old_handler = exception_handling_table[vec];
 838         exception_handling_table[vec] = handler;
 839         return old_handler;
 840 }
 841
 842 void __init trap_init(void)
 843 {
 844         set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
 845         set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
 846
 847 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
 848     defined(CONFIG_SH_FPU_EMU)
 849         /*
 850          * For SH-4 lacking an FPU, treat floating point instructions as
 851          * reserved. They'll be handled in the math-emu case, or faulted on
 852          * otherwise.
 853          */
 854         set_exception_table_evt(0x800, do_reserved_inst);
 855         set_exception_table_evt(0x820, do_illegal_slot_inst);
 856 #elif defined(CONFIG_SH_FPU)
 857         set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
 858         set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
 859 #endif
 860
 861 #ifdef CONFIG_CPU_SH2
 862         set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
 863 #endif
 864 #ifdef CONFIG_CPU_SH2A
 865         set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
 866         set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
 867 #ifdef CONFIG_SH_FPU
 868         set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
 869 #endif
 870 #endif
 871
 872 #ifdef TRAP_UBC
 873         set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
 874 #endif
 875 }