2 * 'traps.c' handles hardware traps and faults after we have saved some
5 * SuperH version: Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf
7 * Copyright (C) 2000 David Howells
8 * Copyright (C) 2002 - 2010 Paul Mundt
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/hardirq.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/module.h>
20 #include <linux/kallsyms.h>
22 #include <linux/bug.h>
23 #include <linux/debug_locks.h>
24 #include <linux/kdebug.h>
25 #include <linux/kexec.h>
26 #include <linux/limits.h>
27 #include <linux/sysfs.h>
28 #include <linux/uaccess.h>
29 #include <linux/perf_event.h>
30 #include <asm/alignment.h>
32 #include <asm/kprobes.h>
33 #include <asm/traps.h>
34 #include <asm/bl_bit.h>
37 # define TRAP_RESERVED_INST 4
38 # define TRAP_ILLEGAL_SLOT_INST 6
39 # define TRAP_ADDRESS_ERROR 9
40 # ifdef CONFIG_CPU_SH2A
42 # define TRAP_FPU_ERROR 13
43 # define TRAP_DIVZERO_ERROR 17
44 # define TRAP_DIVOVF_ERROR 18
47 #define TRAP_RESERVED_INST 12
48 #define TRAP_ILLEGAL_SLOT_INST 13
51 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
56 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
58 for (p = bottom & ~31; p < top; ) {
59 printk("%04lx: ", p & 0xffff);
61 for (i = 0; i < 8; i++, p += 4) {
64 if (p < bottom || p >= top)
67 if (__get_user(val, (unsigned int __user *)p)) {
78 static DEFINE_SPINLOCK(die_lock);
80 void die(const char * str, struct pt_regs * regs, long err)
82 static int die_counter;
86 spin_lock_irq(&die_lock);
90 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
94 printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
95 task_pid_nr(current), task_stack_page(current) + 1);
97 if (!user_mode(regs) || in_interrupt())
98 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
99 (unsigned long)task_stack_page(current));
101 notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
104 add_taint(TAINT_DIE);
105 spin_unlock_irq(&die_lock);
108 if (kexec_should_crash(current))
112 panic("Fatal exception in interrupt");
115 panic("Fatal exception");
120 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
123 if (!user_mode(regs))
128 * try and fix up kernelspace address errors
129 * - userspace errors just cause EFAULT to be returned, resulting in SEGV
130 * - kernel/userspace interfaces cause a jump to an appropriate handler
131 * - other kernel errors are bad
133 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
135 if (!user_mode(regs)) {
136 const struct exception_table_entry *fixup;
137 fixup = search_exception_tables(regs->pc);
139 regs->pc = fixup->fixup;
147 static inline void sign_extend(unsigned int count, unsigned char *dst)
149 #ifdef __LITTLE_ENDIAN__
150 if ((count == 1) && dst[0] & 0x80) {
155 if ((count == 2) && dst[1] & 0x80) {
160 if ((count == 1) && dst[3] & 0x80) {
165 if ((count == 2) && dst[2] & 0x80) {
172 static struct mem_access user_mem_access = {
178 * handle an instruction that does an unaligned memory access by emulating the
180 * - note that PC _may not_ point to the faulting instruction
181 * (if that instruction is in a branch delay slot)
182 * - return 0 if emulation okay, -EFAULT on existential error
184 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
185 struct mem_access *ma)
187 int ret, index, count;
188 unsigned long *rm, *rn;
189 unsigned char *src, *dst;
190 unsigned char __user *srcu, *dstu;
192 index = (instruction>>8)&15; /* 0x0F00 */
193 rn = ®s->regs[index];
195 index = (instruction>>4)&15; /* 0x00F0 */
196 rm = ®s->regs[index];
198 count = 1<<(instruction&3);
201 case 1: inc_unaligned_byte_access(); break;
202 case 2: inc_unaligned_word_access(); break;
203 case 4: inc_unaligned_dword_access(); break;
204 case 8: inc_unaligned_multi_access(); break;
208 switch (instruction>>12) {
209 case 0: /* mov.[bwl] to/from memory via r0+rn */
210 if (instruction & 8) {
212 srcu = (unsigned char __user *)*rm;
213 srcu += regs->regs[0];
214 dst = (unsigned char *)rn;
215 *(unsigned long *)dst = 0;
217 #if !defined(__LITTLE_ENDIAN__)
220 if (ma->from(dst, srcu, count))
223 sign_extend(count, dst);
226 src = (unsigned char *)rm;
227 #if !defined(__LITTLE_ENDIAN__)
230 dstu = (unsigned char __user *)*rn;
231 dstu += regs->regs[0];
233 if (ma->to(dstu, src, count))
239 case 1: /* mov.l Rm,@(disp,Rn) */
240 src = (unsigned char*) rm;
241 dstu = (unsigned char __user *)*rn;
242 dstu += (instruction&0x000F)<<2;
244 if (ma->to(dstu, src, 4))
249 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
252 src = (unsigned char*) rm;
253 dstu = (unsigned char __user *)*rn;
254 #if !defined(__LITTLE_ENDIAN__)
257 if (ma->to(dstu, src, count))
262 case 5: /* mov.l @(disp,Rm),Rn */
263 srcu = (unsigned char __user *)*rm;
264 srcu += (instruction & 0x000F) << 2;
265 dst = (unsigned char *)rn;
266 *(unsigned long *)dst = 0;
268 if (ma->from(dst, srcu, 4))
273 case 6: /* mov.[bwl] from memory, possibly with post-increment */
274 srcu = (unsigned char __user *)*rm;
277 dst = (unsigned char*) rn;
278 *(unsigned long*)dst = 0;
280 #if !defined(__LITTLE_ENDIAN__)
283 if (ma->from(dst, srcu, count))
285 sign_extend(count, dst);
290 switch ((instruction&0xFF00)>>8) {
291 case 0x81: /* mov.w R0,@(disp,Rn) */
292 src = (unsigned char *) ®s->regs[0];
293 #if !defined(__LITTLE_ENDIAN__)
296 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
297 dstu += (instruction & 0x000F) << 1;
299 if (ma->to(dstu, src, 2))
304 case 0x85: /* mov.w @(disp,Rm),R0 */
305 srcu = (unsigned char __user *)*rm;
306 srcu += (instruction & 0x000F) << 1;
307 dst = (unsigned char *) ®s->regs[0];
308 *(unsigned long *)dst = 0;
310 #if !defined(__LITTLE_ENDIAN__)
313 if (ma->from(dst, srcu, 2))
321 case 9: /* mov.w @(disp,PC),Rn */
322 srcu = (unsigned char __user *)regs->pc;
324 srcu += (instruction & 0x00FF) << 1;
325 dst = (unsigned char *)rn;
326 *(unsigned long *)dst = 0;
328 #if !defined(__LITTLE_ENDIAN__)
332 if (ma->from(dst, srcu, 2))
338 case 0xd: /* mov.l @(disp,PC),Rn */
339 srcu = (unsigned char __user *)(regs->pc & ~0x3);
341 srcu += (instruction & 0x00FF) << 2;
342 dst = (unsigned char *)rn;
343 *(unsigned long *)dst = 0;
345 if (ma->from(dst, srcu, 4))
353 /* Argh. Address not only misaligned but also non-existent.
354 * Raise an EFAULT and see if it's trapped
356 die_if_no_fixup("Fault in unaligned fixup", regs, 0);
361 * emulate the instruction in the delay slot
362 * - fetches the instruction from PC+2
364 static inline int handle_delayslot(struct pt_regs *regs,
365 insn_size_t old_instruction,
366 struct mem_access *ma)
368 insn_size_t instruction;
369 void __user *addr = (void __user *)(regs->pc +
370 instruction_size(old_instruction));
372 if (copy_from_user(&instruction, addr, sizeof(instruction))) {
373 /* the instruction-fetch faulted */
378 die("delay-slot-insn faulting in handle_unaligned_delayslot",
382 return handle_unaligned_ins(instruction, regs, ma);
386 * handle an instruction that does an unaligned memory access
387 * - have to be careful of branch delay-slot instructions that fault
389 * - if the branch would be taken PC points to the branch
390 * - if the branch would not be taken, PC points to delay-slot
392 * - PC always points to delayed branch
393 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
396 /* Macros to determine offset from current PC for branch instructions */
397 /* Explicit type coercion is used to force sign extension where needed */
398 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
399 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
401 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
402 struct mem_access *ma, int expected,
403 unsigned long address)
409 * XXX: We can't handle mixed 16/32-bit instructions yet
411 if (instruction_size(instruction) != 2)
414 index = (instruction>>8)&15; /* 0x0F00 */
415 rm = regs->regs[index];
418 * Log the unexpected fixups, and then pass them on to perf.
420 * We intentionally don't report the expected cases to perf as
421 * otherwise the trapped I/O case will skew the results too much
425 unaligned_fixups_notify(current, instruction, regs);
426 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1,
431 switch (instruction&0xF000) {
433 if (instruction==0x000B) {
435 ret = handle_delayslot(regs, instruction, ma);
439 else if ((instruction&0x00FF)==0x0023) {
441 ret = handle_delayslot(regs, instruction, ma);
445 else if ((instruction&0x00FF)==0x0003) {
447 ret = handle_delayslot(regs, instruction, ma);
449 regs->pr = regs->pc + 4;
454 /* mov.[bwl] to/from memory via r0+rn */
459 case 0x1000: /* mov.l Rm,@(disp,Rn) */
462 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
466 if ((instruction&0x00FF)==0x002B) {
468 ret = handle_delayslot(regs, instruction, ma);
472 else if ((instruction&0x00FF)==0x000B) {
474 ret = handle_delayslot(regs, instruction, ma);
476 regs->pr = regs->pc + 4;
481 /* mov.[bwl] to/from memory via r0+rn */
486 case 0x5000: /* mov.l @(disp,Rm),Rn */
489 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
492 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
493 switch (instruction&0x0F00) {
494 case 0x0100: /* mov.w R0,@(disp,Rm) */
496 case 0x0500: /* mov.w @(disp,Rm),R0 */
498 case 0x0B00: /* bf lab - no delayslot*/
501 case 0x0F00: /* bf/s lab */
502 ret = handle_delayslot(regs, instruction, ma);
504 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
505 if ((regs->sr & 0x00000001) != 0)
506 regs->pc += 4; /* next after slot */
509 regs->pc += SH_PC_8BIT_OFFSET(instruction);
512 case 0x0900: /* bt lab - no delayslot */
515 case 0x0D00: /* bt/s lab */
516 ret = handle_delayslot(regs, instruction, ma);
518 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
519 if ((regs->sr & 0x00000001) == 0)
520 regs->pc += 4; /* next after slot */
523 regs->pc += SH_PC_8BIT_OFFSET(instruction);
529 case 0x9000: /* mov.w @(disp,Rm),Rn */
532 case 0xA000: /* bra label */
533 ret = handle_delayslot(regs, instruction, ma);
535 regs->pc += SH_PC_12BIT_OFFSET(instruction);
538 case 0xB000: /* bsr label */
539 ret = handle_delayslot(regs, instruction, ma);
541 regs->pr = regs->pc + 4;
542 regs->pc += SH_PC_12BIT_OFFSET(instruction);
546 case 0xD000: /* mov.l @(disp,Rm),Rn */
551 /* handle non-delay-slot instruction */
553 ret = handle_unaligned_ins(instruction, regs, ma);
555 regs->pc += instruction_size(instruction);
560 * Handle various address error exceptions:
561 * - instruction address error:
563 * PC >= 0x80000000 in user mode
564 * - data address error (read and write)
565 * misaligned data access
566 * access to >= 0x80000000 is user mode
567 * Unfortuntaly we can't distinguish between instruction address error
568 * and data address errors caused by read accesses.
570 asmlinkage void do_address_error(struct pt_regs *regs,
571 unsigned long writeaccess,
572 unsigned long address)
574 unsigned long error_code = 0;
577 insn_size_t instruction;
580 /* Intentional ifdef */
581 #ifdef CONFIG_CPU_HAS_SR_RB
582 error_code = lookup_exception_vector();
587 if (user_mode(regs)) {
588 int si_code = BUS_ADRERR;
589 unsigned int user_action;
592 inc_unaligned_user_access();
595 if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
596 sizeof(instruction))) {
602 /* shout about userspace fixups */
603 unaligned_fixups_notify(current, instruction, regs);
605 user_action = unaligned_user_action();
606 if (user_action & UM_FIXUP)
608 if (user_action & UM_SIGNAL)
612 regs->pc += instruction_size(instruction);
617 /* bad PC is not something we can fix */
619 si_code = BUS_ADRALN;
624 tmp = handle_unaligned_access(instruction, regs,
632 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
633 "access (PC %lx PR %lx)\n", current->comm, regs->pc,
636 info.si_signo = SIGBUS;
638 info.si_code = si_code;
639 info.si_addr = (void __user *)address;
640 force_sig_info(SIGBUS, &info, current);
642 inc_unaligned_kernel_access();
645 die("unaligned program counter", regs, error_code);
648 if (copy_from_user(&instruction, (void __user *)(regs->pc),
649 sizeof(instruction))) {
650 /* Argh. Fault on the instruction itself.
651 This should never happen non-SMP
654 die("insn faulting in do_address_error", regs, 0);
657 unaligned_fixups_notify(current, instruction, regs);
659 handle_unaligned_access(instruction, regs, &user_mem_access,
667 * SH-DSP support gerg@snapgear.com.
669 int is_dsp_inst(struct pt_regs *regs)
671 unsigned short inst = 0;
674 * Safe guard if DSP mode is already enabled or we're lacking
675 * the DSP altogether.
677 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
680 get_user(inst, ((unsigned short *) regs->pc));
684 /* Check for any type of DSP or support instruction */
685 if ((inst == 0xf000) || (inst == 0x4000))
691 #define is_dsp_inst(regs) (0)
692 #endif /* CONFIG_SH_DSP */
694 #ifdef CONFIG_CPU_SH2A
695 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
696 unsigned long r6, unsigned long r7,
697 struct pt_regs __regs)
702 case TRAP_DIVZERO_ERROR:
703 info.si_code = FPE_INTDIV;
705 case TRAP_DIVOVF_ERROR:
706 info.si_code = FPE_INTOVF;
710 force_sig_info(SIGFPE, &info, current);
714 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
715 unsigned long r6, unsigned long r7,
716 struct pt_regs __regs)
718 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
719 unsigned long error_code;
720 struct task_struct *tsk = current;
722 #ifdef CONFIG_SH_FPU_EMU
723 unsigned short inst = 0;
726 get_user(inst, (unsigned short*)regs->pc);
728 err = do_fpu_inst(inst, regs);
730 regs->pc += instruction_size(inst);
733 /* not a FPU inst. */
737 /* Check if it's a DSP instruction */
738 if (is_dsp_inst(regs)) {
739 /* Enable DSP mode, and restart instruction. */
742 tsk->thread.dsp_status.status |= SR_DSP;
747 error_code = lookup_exception_vector();
750 force_sig(SIGILL, tsk);
751 die_if_no_fixup("reserved instruction", regs, error_code);
754 #ifdef CONFIG_SH_FPU_EMU
755 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
758 * bfs: 8fxx: PC+=d*2+4;
759 * bts: 8dxx: PC+=d*2+4;
760 * bra: axxx: PC+=D*2+4;
761 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
762 * braf:0x23: PC+=Rn*2+4;
763 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
765 * jsr: 4x0b: PC=Rn after PR=PC+4;
768 if (((inst & 0xf000) == 0xb000) || /* bsr */
769 ((inst & 0xf0ff) == 0x0003) || /* bsrf */
770 ((inst & 0xf0ff) == 0x400b)) /* jsr */
771 regs->pr = regs->pc + 4;
773 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */
774 regs->pc += SH_PC_8BIT_OFFSET(inst);
778 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */
779 regs->pc += SH_PC_12BIT_OFFSET(inst);
783 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */
784 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
788 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */
789 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
793 if ((inst & 0xffff) == 0x000b) { /* rts */
802 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
803 unsigned long r6, unsigned long r7,
804 struct pt_regs __regs)
806 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
808 struct task_struct *tsk = current;
810 if (kprobe_handle_illslot(regs->pc) == 0)
813 #ifdef CONFIG_SH_FPU_EMU
814 get_user(inst, (unsigned short *)regs->pc + 1);
815 if (!do_fpu_inst(inst, regs)) {
816 get_user(inst, (unsigned short *)regs->pc);
817 if (!emulate_branch(inst, regs))
819 /* fault in branch.*/
821 /* not a FPU inst. */
824 inst = lookup_exception_vector();
827 force_sig(SIGILL, tsk);
828 die_if_no_fixup("illegal slot instruction", regs, inst);
831 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
832 unsigned long r6, unsigned long r7,
833 struct pt_regs __regs)
835 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
838 ex = lookup_exception_vector();
839 die_if_kernel("exception", regs, ex);
842 void __cpuinit per_cpu_trap_init(void)
844 extern void *vbr_base;
846 /* NOTE: The VBR value should be at P1
847 (or P2, virtural "fixed" address space).
848 It's definitely should not in physical address. */
850 asm volatile("ldc %0, vbr"
855 /* disable exception blocking now when the vbr has been setup */
859 void *set_exception_table_vec(unsigned int vec, void *handler)
861 extern void *exception_handling_table[];
864 old_handler = exception_handling_table[vec];
865 exception_handling_table[vec] = handler;
869 void __init trap_init(void)
871 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
872 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
874 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
875 defined(CONFIG_SH_FPU_EMU)
877 * For SH-4 lacking an FPU, treat floating point instructions as
878 * reserved. They'll be handled in the math-emu case, or faulted on
881 set_exception_table_evt(0x800, do_reserved_inst);
882 set_exception_table_evt(0x820, do_illegal_slot_inst);
883 #elif defined(CONFIG_SH_FPU)
884 set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
885 set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
888 #ifdef CONFIG_CPU_SH2
889 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
891 #ifdef CONFIG_CPU_SH2A
892 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
893 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
895 set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
900 set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
904 void show_stack(struct task_struct *tsk, unsigned long *sp)
911 sp = (unsigned long *)current_stack_pointer;
913 sp = (unsigned long *)tsk->thread.sp;
915 stack = (unsigned long)sp;
916 dump_mem("Stack: ", stack, THREAD_SIZE +
917 (unsigned long)task_stack_page(tsk));
918 show_trace(tsk, sp, NULL);
921 void dump_stack(void)
923 show_stack(NULL, NULL);
925 EXPORT_SYMBOL(dump_stack);