2 * 'traps.c' handles hardware traps and faults after we have saved some
5 * SuperH version: Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf
7 * Copyright (C) 2000 David Howells
8 * Copyright (C) 2002 - 2010 Paul Mundt
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/hardirq.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/module.h>
20 #include <linux/kallsyms.h>
22 #include <linux/bug.h>
23 #include <linux/debug_locks.h>
24 #include <linux/kdebug.h>
25 #include <linux/kexec.h>
26 #include <linux/limits.h>
27 #include <linux/sysfs.h>
28 #include <linux/uaccess.h>
29 #include <linux/perf_event.h>
30 #include <asm/system.h>
31 #include <asm/alignment.h>
33 #include <asm/kprobes.h>
36 # define TRAP_RESERVED_INST 4
37 # define TRAP_ILLEGAL_SLOT_INST 6
38 # define TRAP_ADDRESS_ERROR 9
39 # ifdef CONFIG_CPU_SH2A
41 # define TRAP_FPU_ERROR 13
42 # define TRAP_DIVZERO_ERROR 17
43 # define TRAP_DIVOVF_ERROR 18
46 #define TRAP_RESERVED_INST 12
47 #define TRAP_ILLEGAL_SLOT_INST 13
50 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
55 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
57 for (p = bottom & ~31; p < top; ) {
58 printk("%04lx: ", p & 0xffff);
60 for (i = 0; i < 8; i++, p += 4) {
63 if (p < bottom || p >= top)
66 if (__get_user(val, (unsigned int __user *)p)) {
77 static DEFINE_SPINLOCK(die_lock);
79 void die(const char * str, struct pt_regs * regs, long err)
81 static int die_counter;
85 spin_lock_irq(&die_lock);
89 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
93 printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
94 task_pid_nr(current), task_stack_page(current) + 1);
96 if (!user_mode(regs) || in_interrupt())
97 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
98 (unsigned long)task_stack_page(current));
100 notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
103 add_taint(TAINT_DIE);
104 spin_unlock_irq(&die_lock);
107 if (kexec_should_crash(current))
111 panic("Fatal exception in interrupt");
114 panic("Fatal exception");
119 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
122 if (!user_mode(regs))
127 * try and fix up kernelspace address errors
128 * - userspace errors just cause EFAULT to be returned, resulting in SEGV
129 * - kernel/userspace interfaces cause a jump to an appropriate handler
130 * - other kernel errors are bad
132 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
134 if (!user_mode(regs)) {
135 const struct exception_table_entry *fixup;
136 fixup = search_exception_tables(regs->pc);
138 regs->pc = fixup->fixup;
146 static inline void sign_extend(unsigned int count, unsigned char *dst)
148 #ifdef __LITTLE_ENDIAN__
149 if ((count == 1) && dst[0] & 0x80) {
154 if ((count == 2) && dst[1] & 0x80) {
159 if ((count == 1) && dst[3] & 0x80) {
164 if ((count == 2) && dst[2] & 0x80) {
171 static struct mem_access user_mem_access = {
177 * handle an instruction that does an unaligned memory access by emulating the
179 * - note that PC _may not_ point to the faulting instruction
180 * (if that instruction is in a branch delay slot)
181 * - return 0 if emulation okay, -EFAULT on existential error
183 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
184 struct mem_access *ma)
186 int ret, index, count;
187 unsigned long *rm, *rn;
188 unsigned char *src, *dst;
189 unsigned char __user *srcu, *dstu;
191 index = (instruction>>8)&15; /* 0x0F00 */
192 rn = ®s->regs[index];
194 index = (instruction>>4)&15; /* 0x00F0 */
195 rm = ®s->regs[index];
197 count = 1<<(instruction&3);
200 case 1: inc_unaligned_byte_access(); break;
201 case 2: inc_unaligned_word_access(); break;
202 case 4: inc_unaligned_dword_access(); break;
203 case 8: inc_unaligned_multi_access(); break;
207 switch (instruction>>12) {
208 case 0: /* mov.[bwl] to/from memory via r0+rn */
209 if (instruction & 8) {
211 srcu = (unsigned char __user *)*rm;
212 srcu += regs->regs[0];
213 dst = (unsigned char *)rn;
214 *(unsigned long *)dst = 0;
216 #if !defined(__LITTLE_ENDIAN__)
219 if (ma->from(dst, srcu, count))
222 sign_extend(count, dst);
225 src = (unsigned char *)rm;
226 #if !defined(__LITTLE_ENDIAN__)
229 dstu = (unsigned char __user *)*rn;
230 dstu += regs->regs[0];
232 if (ma->to(dstu, src, count))
238 case 1: /* mov.l Rm,@(disp,Rn) */
239 src = (unsigned char*) rm;
240 dstu = (unsigned char __user *)*rn;
241 dstu += (instruction&0x000F)<<2;
243 if (ma->to(dstu, src, 4))
248 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
251 src = (unsigned char*) rm;
252 dstu = (unsigned char __user *)*rn;
253 #if !defined(__LITTLE_ENDIAN__)
256 if (ma->to(dstu, src, count))
261 case 5: /* mov.l @(disp,Rm),Rn */
262 srcu = (unsigned char __user *)*rm;
263 srcu += (instruction & 0x000F) << 2;
264 dst = (unsigned char *)rn;
265 *(unsigned long *)dst = 0;
267 if (ma->from(dst, srcu, 4))
272 case 6: /* mov.[bwl] from memory, possibly with post-increment */
273 srcu = (unsigned char __user *)*rm;
276 dst = (unsigned char*) rn;
277 *(unsigned long*)dst = 0;
279 #if !defined(__LITTLE_ENDIAN__)
282 if (ma->from(dst, srcu, count))
284 sign_extend(count, dst);
289 switch ((instruction&0xFF00)>>8) {
290 case 0x81: /* mov.w R0,@(disp,Rn) */
291 src = (unsigned char *) ®s->regs[0];
292 #if !defined(__LITTLE_ENDIAN__)
295 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
296 dstu += (instruction & 0x000F) << 1;
298 if (ma->to(dstu, src, 2))
303 case 0x85: /* mov.w @(disp,Rm),R0 */
304 srcu = (unsigned char __user *)*rm;
305 srcu += (instruction & 0x000F) << 1;
306 dst = (unsigned char *) ®s->regs[0];
307 *(unsigned long *)dst = 0;
309 #if !defined(__LITTLE_ENDIAN__)
312 if (ma->from(dst, srcu, 2))
320 case 9: /* mov.w @(disp,PC),Rn */
321 srcu = (unsigned char __user *)regs->pc;
323 srcu += (instruction & 0x00FF) << 1;
324 dst = (unsigned char *)rn;
325 *(unsigned long *)dst = 0;
327 #if !defined(__LITTLE_ENDIAN__)
331 if (ma->from(dst, srcu, 2))
337 case 0xd: /* mov.l @(disp,PC),Rn */
338 srcu = (unsigned char __user *)(regs->pc & ~0x3);
340 srcu += (instruction & 0x00FF) << 2;
341 dst = (unsigned char *)rn;
342 *(unsigned long *)dst = 0;
344 if (ma->from(dst, srcu, 4))
352 /* Argh. Address not only misaligned but also non-existent.
353 * Raise an EFAULT and see if it's trapped
355 die_if_no_fixup("Fault in unaligned fixup", regs, 0);
360 * emulate the instruction in the delay slot
361 * - fetches the instruction from PC+2
363 static inline int handle_delayslot(struct pt_regs *regs,
364 insn_size_t old_instruction,
365 struct mem_access *ma)
367 insn_size_t instruction;
368 void __user *addr = (void __user *)(regs->pc +
369 instruction_size(old_instruction));
371 if (copy_from_user(&instruction, addr, sizeof(instruction))) {
372 /* the instruction-fetch faulted */
377 die("delay-slot-insn faulting in handle_unaligned_delayslot",
381 return handle_unaligned_ins(instruction, regs, ma);
385 * handle an instruction that does an unaligned memory access
386 * - have to be careful of branch delay-slot instructions that fault
388 * - if the branch would be taken PC points to the branch
389 * - if the branch would not be taken, PC points to delay-slot
391 * - PC always points to delayed branch
392 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
395 /* Macros to determine offset from current PC for branch instructions */
396 /* Explicit type coercion is used to force sign extension where needed */
397 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
398 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
400 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
401 struct mem_access *ma, int expected,
402 unsigned long address)
408 * XXX: We can't handle mixed 16/32-bit instructions yet
410 if (instruction_size(instruction) != 2)
413 index = (instruction>>8)&15; /* 0x0F00 */
414 rm = regs->regs[index];
417 * Log the unexpected fixups, and then pass them on to perf.
419 * We intentionally don't report the expected cases to perf as
420 * otherwise the trapped I/O case will skew the results too much
424 unaligned_fixups_notify(current, instruction, regs);
425 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1,
430 switch (instruction&0xF000) {
432 if (instruction==0x000B) {
434 ret = handle_delayslot(regs, instruction, ma);
438 else if ((instruction&0x00FF)==0x0023) {
440 ret = handle_delayslot(regs, instruction, ma);
444 else if ((instruction&0x00FF)==0x0003) {
446 ret = handle_delayslot(regs, instruction, ma);
448 regs->pr = regs->pc + 4;
453 /* mov.[bwl] to/from memory via r0+rn */
458 case 0x1000: /* mov.l Rm,@(disp,Rn) */
461 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
465 if ((instruction&0x00FF)==0x002B) {
467 ret = handle_delayslot(regs, instruction, ma);
471 else if ((instruction&0x00FF)==0x000B) {
473 ret = handle_delayslot(regs, instruction, ma);
475 regs->pr = regs->pc + 4;
480 /* mov.[bwl] to/from memory via r0+rn */
485 case 0x5000: /* mov.l @(disp,Rm),Rn */
488 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
491 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
492 switch (instruction&0x0F00) {
493 case 0x0100: /* mov.w R0,@(disp,Rm) */
495 case 0x0500: /* mov.w @(disp,Rm),R0 */
497 case 0x0B00: /* bf lab - no delayslot*/
500 case 0x0F00: /* bf/s lab */
501 ret = handle_delayslot(regs, instruction, ma);
503 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
504 if ((regs->sr & 0x00000001) != 0)
505 regs->pc += 4; /* next after slot */
508 regs->pc += SH_PC_8BIT_OFFSET(instruction);
511 case 0x0900: /* bt lab - no delayslot */
514 case 0x0D00: /* bt/s lab */
515 ret = handle_delayslot(regs, instruction, ma);
517 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
518 if ((regs->sr & 0x00000001) == 0)
519 regs->pc += 4; /* next after slot */
522 regs->pc += SH_PC_8BIT_OFFSET(instruction);
528 case 0x9000: /* mov.w @(disp,Rm),Rn */
531 case 0xA000: /* bra label */
532 ret = handle_delayslot(regs, instruction, ma);
534 regs->pc += SH_PC_12BIT_OFFSET(instruction);
537 case 0xB000: /* bsr label */
538 ret = handle_delayslot(regs, instruction, ma);
540 regs->pr = regs->pc + 4;
541 regs->pc += SH_PC_12BIT_OFFSET(instruction);
545 case 0xD000: /* mov.l @(disp,Rm),Rn */
550 /* handle non-delay-slot instruction */
552 ret = handle_unaligned_ins(instruction, regs, ma);
554 regs->pc += instruction_size(instruction);
559 * Handle various address error exceptions:
560 * - instruction address error:
562 * PC >= 0x80000000 in user mode
563 * - data address error (read and write)
564 * misaligned data access
565 * access to >= 0x80000000 is user mode
566 * Unfortuntaly we can't distinguish between instruction address error
567 * and data address errors caused by read accesses.
569 asmlinkage void do_address_error(struct pt_regs *regs,
570 unsigned long writeaccess,
571 unsigned long address)
573 unsigned long error_code = 0;
576 insn_size_t instruction;
579 /* Intentional ifdef */
580 #ifdef CONFIG_CPU_HAS_SR_RB
581 error_code = lookup_exception_vector();
586 if (user_mode(regs)) {
587 int si_code = BUS_ADRERR;
588 unsigned int user_action;
591 inc_unaligned_user_access();
594 if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
595 sizeof(instruction))) {
601 /* shout about userspace fixups */
602 unaligned_fixups_notify(current, instruction, regs);
604 user_action = unaligned_user_action();
605 if (user_action & UM_FIXUP)
607 if (user_action & UM_SIGNAL)
611 regs->pc += instruction_size(instruction);
616 /* bad PC is not something we can fix */
618 si_code = BUS_ADRALN;
623 tmp = handle_unaligned_access(instruction, regs,
631 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
632 "access (PC %lx PR %lx)\n", current->comm, regs->pc,
635 info.si_signo = SIGBUS;
637 info.si_code = si_code;
638 info.si_addr = (void __user *)address;
639 force_sig_info(SIGBUS, &info, current);
641 inc_unaligned_kernel_access();
644 die("unaligned program counter", regs, error_code);
647 if (copy_from_user(&instruction, (void __user *)(regs->pc),
648 sizeof(instruction))) {
649 /* Argh. Fault on the instruction itself.
650 This should never happen non-SMP
653 die("insn faulting in do_address_error", regs, 0);
656 unaligned_fixups_notify(current, instruction, regs);
658 handle_unaligned_access(instruction, regs, &user_mem_access,
666 * SH-DSP support gerg@snapgear.com.
668 int is_dsp_inst(struct pt_regs *regs)
670 unsigned short inst = 0;
673 * Safe guard if DSP mode is already enabled or we're lacking
674 * the DSP altogether.
676 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
679 get_user(inst, ((unsigned short *) regs->pc));
683 /* Check for any type of DSP or support instruction */
684 if ((inst == 0xf000) || (inst == 0x4000))
690 #define is_dsp_inst(regs) (0)
691 #endif /* CONFIG_SH_DSP */
693 #ifdef CONFIG_CPU_SH2A
694 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
695 unsigned long r6, unsigned long r7,
696 struct pt_regs __regs)
701 case TRAP_DIVZERO_ERROR:
702 info.si_code = FPE_INTDIV;
704 case TRAP_DIVOVF_ERROR:
705 info.si_code = FPE_INTOVF;
709 force_sig_info(SIGFPE, &info, current);
713 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
714 unsigned long r6, unsigned long r7,
715 struct pt_regs __regs)
717 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
718 unsigned long error_code;
719 struct task_struct *tsk = current;
721 #ifdef CONFIG_SH_FPU_EMU
722 unsigned short inst = 0;
725 get_user(inst, (unsigned short*)regs->pc);
727 err = do_fpu_inst(inst, regs);
729 regs->pc += instruction_size(inst);
732 /* not a FPU inst. */
736 /* Check if it's a DSP instruction */
737 if (is_dsp_inst(regs)) {
738 /* Enable DSP mode, and restart instruction. */
741 tsk->thread.dsp_status.status |= SR_DSP;
746 error_code = lookup_exception_vector();
749 force_sig(SIGILL, tsk);
750 die_if_no_fixup("reserved instruction", regs, error_code);
753 #ifdef CONFIG_SH_FPU_EMU
754 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
757 * bfs: 8fxx: PC+=d*2+4;
758 * bts: 8dxx: PC+=d*2+4;
759 * bra: axxx: PC+=D*2+4;
760 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
761 * braf:0x23: PC+=Rn*2+4;
762 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
764 * jsr: 4x0b: PC=Rn after PR=PC+4;
767 if (((inst & 0xf000) == 0xb000) || /* bsr */
768 ((inst & 0xf0ff) == 0x0003) || /* bsrf */
769 ((inst & 0xf0ff) == 0x400b)) /* jsr */
770 regs->pr = regs->pc + 4;
772 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */
773 regs->pc += SH_PC_8BIT_OFFSET(inst);
777 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */
778 regs->pc += SH_PC_12BIT_OFFSET(inst);
782 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */
783 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
787 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */
788 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
792 if ((inst & 0xffff) == 0x000b) { /* rts */
801 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
802 unsigned long r6, unsigned long r7,
803 struct pt_regs __regs)
805 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
807 struct task_struct *tsk = current;
809 if (kprobe_handle_illslot(regs->pc) == 0)
812 #ifdef CONFIG_SH_FPU_EMU
813 get_user(inst, (unsigned short *)regs->pc + 1);
814 if (!do_fpu_inst(inst, regs)) {
815 get_user(inst, (unsigned short *)regs->pc);
816 if (!emulate_branch(inst, regs))
818 /* fault in branch.*/
820 /* not a FPU inst. */
823 inst = lookup_exception_vector();
826 force_sig(SIGILL, tsk);
827 die_if_no_fixup("illegal slot instruction", regs, inst);
830 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
831 unsigned long r6, unsigned long r7,
832 struct pt_regs __regs)
834 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
837 ex = lookup_exception_vector();
838 die_if_kernel("exception", regs, ex);
841 void __cpuinit per_cpu_trap_init(void)
843 extern void *vbr_base;
845 /* NOTE: The VBR value should be at P1
846 (or P2, virtural "fixed" address space).
847 It's definitely should not in physical address. */
849 asm volatile("ldc %0, vbr"
854 /* disable exception blocking now when the vbr has been setup */
858 void *set_exception_table_vec(unsigned int vec, void *handler)
860 extern void *exception_handling_table[];
863 old_handler = exception_handling_table[vec];
864 exception_handling_table[vec] = handler;
868 void __init trap_init(void)
870 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
871 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
873 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
874 defined(CONFIG_SH_FPU_EMU)
876 * For SH-4 lacking an FPU, treat floating point instructions as
877 * reserved. They'll be handled in the math-emu case, or faulted on
880 set_exception_table_evt(0x800, do_reserved_inst);
881 set_exception_table_evt(0x820, do_illegal_slot_inst);
882 #elif defined(CONFIG_SH_FPU)
883 set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
884 set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
887 #ifdef CONFIG_CPU_SH2
888 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
890 #ifdef CONFIG_CPU_SH2A
891 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
892 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
894 set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
899 set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
903 void show_stack(struct task_struct *tsk, unsigned long *sp)
910 sp = (unsigned long *)current_stack_pointer;
912 sp = (unsigned long *)tsk->thread.sp;
914 stack = (unsigned long)sp;
915 dump_mem("Stack: ", stack, THREAD_SIZE +
916 (unsigned long)task_stack_page(tsk));
917 show_trace(tsk, sp, NULL);
920 void dump_stack(void)
922 show_stack(NULL, NULL);
924 EXPORT_SYMBOL(dump_stack);