arch/sh/kernel/traps_64.c

   1 /*
   2  * arch/sh/kernel/traps_64.c
   3  *
   4  * Copyright (C) 2000, 2001  Paolo Alberelli
   5  * Copyright (C) 2003, 2004  Paul Mundt
   6  * Copyright (C) 2003, 2004  Richard Curnow
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/sched.h>
  13 #include <linux/kernel.h>
  14 #include <linux/string.h>
  15 #include <linux/errno.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/timer.h>
  18 #include <linux/mm.h>
  19 #include <linux/smp.h>
  20 #include <linux/init.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/kallsyms.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysctl.h>
  26 #include <linux/module.h>
  27 #include <linux/perf_event.h>
  28 #include <asm/uaccess.h>
  29 #include <asm/io.h>
  30 #include <linux/atomic.h>
  31 #include <asm/processor.h>
  32 #include <asm/pgtable.h>
  33 #include <asm/fpu.h>
  34
  35 #undef DEBUG_EXCEPTION
  36 #ifdef DEBUG_EXCEPTION
  37 /* implemented in ../lib/dbg.c */
  38 extern void show_excp_regs(char *fname, int trapnr, int signr,
  39                            struct pt_regs *regs);
  40 #else
  41 #define show_excp_regs(a, b, c, d)
  42 #endif
  43
  44 static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
  45                 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk);
  46
  47 #define DO_ERROR(trapnr, signr, str, name, tsk) \
  48 asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \
  49 { \
  50         do_unhandled_exception(trapnr, signr, str, __stringify(name), error_code, regs, current); \
  51 }
  52
  53 static DEFINE_SPINLOCK(die_lock);
  54
  55 void die(const char * str, struct pt_regs * regs, long err)
  56 {
  57         console_verbose();
  58         spin_lock_irq(&die_lock);
  59         printk("%s: %lx\n", str, (err & 0xffffff));
  60         show_regs(regs);
  61         spin_unlock_irq(&die_lock);
  62         do_exit(SIGSEGV);
  63 }
  64
  65 static inline void die_if_kernel(const char * str, struct pt_regs * regs, long err)
  66 {
  67         if (!user_mode(regs))
  68                 die(str, regs, err);
  69 }
  70
  71 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
  72 {
  73         if (!user_mode(regs)) {
  74                 const struct exception_table_entry *fixup;
  75                 fixup = search_exception_tables(regs->pc);
  76                 if (fixup) {
  77                         regs->pc = fixup->fixup;
  78                         return;
  79                 }
  80                 die(str, regs, err);
  81         }
  82 }
  83
  84 DO_ERROR(13, SIGILL,  "illegal slot instruction", illegal_slot_inst, current)
  85 DO_ERROR(87, SIGSEGV, "address error (exec)", address_error_exec, current)
  86
  87
  88 /* Implement misaligned load/store handling for kernel (and optionally for user
  89    mode too).  Limitation : only SHmedia mode code is handled - there is no
  90    handling at all for misaligned accesses occurring in SHcompact code yet. */
  91
  92 static int misaligned_fixup(struct pt_regs *regs);
  93
  94 asmlinkage void do_address_error_load(unsigned long error_code, struct pt_regs *regs)
  95 {
  96         if (misaligned_fixup(regs) < 0) {
  97                 do_unhandled_exception(7, SIGSEGV, "address error(load)",
  98                                 "do_address_error_load",
  99                                 error_code, regs, current);
 100         }
 101         return;
 102 }
 103
 104 asmlinkage void do_address_error_store(unsigned long error_code, struct pt_regs *regs)
 105 {
 106         if (misaligned_fixup(regs) < 0) {
 107                 do_unhandled_exception(8, SIGSEGV, "address error(store)",
 108                                 "do_address_error_store",
 109                                 error_code, regs, current);
 110         }
 111         return;
 112 }
 113
 114 #if defined(CONFIG_SH64_ID2815_WORKAROUND)
 115
 116 #define OPCODE_INVALID      0
 117 #define OPCODE_USER_VALID   1
 118 #define OPCODE_PRIV_VALID   2
 119
 120 /* getcon/putcon - requires checking which control register is referenced. */
 121 #define OPCODE_CTRL_REG     3
 122
 123 /* Table of valid opcodes for SHmedia mode.
 124    Form a 10-bit value by concatenating the major/minor opcodes i.e.
 125    opcode[31:26,20:16].  The 6 MSBs of this value index into the following
 126    array.  The 4 LSBs select the bit-pair in the entry (bits 1:0 correspond to
 127    LSBs==4'b0000 etc). */
 128 static unsigned long shmedia_opcode_table[64] = {
 129         0x55554044,0x54445055,0x15141514,0x14541414,0x00000000,0x10001000,0x01110055,0x04050015,
 130         0x00000444,0xc0000000,0x44545515,0x40405555,0x55550015,0x10005555,0x55555505,0x04050000,
 131         0x00000555,0x00000404,0x00040445,0x15151414,0x00000000,0x00000000,0x00000000,0x00000000,
 132         0x00000055,0x40404444,0x00000404,0xc0009495,0x00000000,0x00000000,0x00000000,0x00000000,
 133         0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
 134         0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
 135         0x80005050,0x04005055,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
 136         0x81055554,0x00000404,0x55555555,0x55555555,0x00000000,0x00000000,0x00000000,0x00000000
 137 };
 138
 139 void do_reserved_inst(unsigned long error_code, struct pt_regs *regs)
 140 {
 141         /* Workaround SH5-101 cut2 silicon defect #2815 :
 142            in some situations, inter-mode branches from SHcompact -> SHmedia
 143            which should take ITLBMISS or EXECPROT exceptions at the target
 144            falsely take RESINST at the target instead. */
 145
 146         unsigned long opcode = 0x6ff4fff0; /* guaranteed reserved opcode */
 147         unsigned long pc, aligned_pc;
 148         int get_user_error;
 149         int trapnr = 12;
 150         int signr = SIGILL;
 151         char *exception_name = "reserved_instruction";
 152
 153         pc = regs->pc;
 154         if ((pc & 3) == 1) {
 155                 /* SHmedia : check for defect.  This requires executable vmas
 156                    to be readable too. */
 157                 aligned_pc = pc & ~3;
 158                 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
 159                         get_user_error = -EFAULT;
 160                 } else {
 161                         get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
 162                 }
 163                 if (get_user_error >= 0) {
 164                         unsigned long index, shift;
 165                         unsigned long major, minor, combined;
 166                         unsigned long reserved_field;
 167                         reserved_field = opcode & 0xf; /* These bits are currently reserved as zero in all valid opcodes */
 168                         major = (opcode >> 26) & 0x3f;
 169                         minor = (opcode >> 16) & 0xf;
 170                         combined = (major << 4) | minor;
 171                         index = major;
 172                         shift = minor << 1;
 173                         if (reserved_field == 0) {
 174                                 int opcode_state = (shmedia_opcode_table[index] >> shift) & 0x3;
 175                                 switch (opcode_state) {
 176                                         case OPCODE_INVALID:
 177                                                 /* Trap. */
 178                                                 break;
 179                                         case OPCODE_USER_VALID:
 180                                                 /* Restart the instruction : the branch to the instruction will now be from an RTE
 181                                                    not from SHcompact so the silicon defect won't be triggered. */
 182                                                 return;
 183                                         case OPCODE_PRIV_VALID:
 184                                                 if (!user_mode(regs)) {
 185                                                         /* Should only ever get here if a module has
 186                                                            SHcompact code inside it.  If so, the same fix up is needed. */
 187                                                         return; /* same reason */
 188                                                 }
 189                                                 /* Otherwise, user mode trying to execute a privileged instruction -
 190                                                    fall through to trap. */
 191                                                 break;
 192                                         case OPCODE_CTRL_REG:
 193                                                 /* If in privileged mode, return as above. */
 194                                                 if (!user_mode(regs)) return;
 195                                                 /* In user mode ... */
 196                                                 if (combined == 0x9f) { /* GETCON */
 197                                                         unsigned long regno = (opcode >> 20) & 0x3f;
 198                                                         if (regno >= 62) {
 199                                                                 return;
 200                                                         }
 201                                                         /* Otherwise, reserved or privileged control register, => trap */
 202                                                 } else if (combined == 0x1bf) { /* PUTCON */
 203                                                         unsigned long regno = (opcode >> 4) & 0x3f;
 204                                                         if (regno >= 62) {
 205                                                                 return;
 206                                                         }
 207                                                         /* Otherwise, reserved or privileged control register, => trap */
 208                                                 } else {
 209                                                         /* Trap */
 210                                                 }
 211                                                 break;
 212                                         default:
 213                                                 /* Fall through to trap. */
 214                                                 break;
 215                                 }
 216                         }
 217                         /* fall through to normal resinst processing */
 218                 } else {
 219                         /* Error trying to read opcode.  This typically means a
 220                            real fault, not a RESINST any more.  So change the
 221                            codes. */
 222                         trapnr = 87;
 223                         exception_name = "address error (exec)";
 224                         signr = SIGSEGV;
 225                 }
 226         }
 227
 228         do_unhandled_exception(trapnr, signr, exception_name, "do_reserved_inst", error_code, regs, current);
 229 }
 230
 231 #else /* CONFIG_SH64_ID2815_WORKAROUND */
 232
 233 /* If the workaround isn't needed, this is just a straightforward reserved
 234    instruction */
 235 DO_ERROR(12, SIGILL,  "reserved instruction", reserved_inst, current)
 236
 237 #endif /* CONFIG_SH64_ID2815_WORKAROUND */
 238
 239 /* Called with interrupts disabled */
 240 asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs)
 241 {
 242         show_excp_regs(__func__, -1, -1, regs);
 243         die_if_kernel("exception", regs, ex);
 244 }
 245
 246 int do_unknown_trapa(unsigned long scId, struct pt_regs *regs)
 247 {
 248         /* Syscall debug */
 249         printk("System call ID error: [0x1#args:8 #syscall:16  0x%lx]\n", scId);
 250
 251         die_if_kernel("unknown trapa", regs, scId);
 252
 253         return -ENOSYS;
 254 }
 255
 256 void show_stack(struct task_struct *tsk, unsigned long *sp)
 257 {
 258 #ifdef CONFIG_KALLSYMS
 259         extern void sh64_unwind(struct pt_regs *regs);
 260         struct pt_regs *regs;
 261
 262         regs = tsk ? tsk->thread.kregs : NULL;
 263
 264         sh64_unwind(regs);
 265 #else
 266         printk(KERN_ERR "Can't backtrace on sh64 without CONFIG_KALLSYMS\n");
 267 #endif
 268 }
 269
 270 void show_task(unsigned long *sp)
 271 {
 272         show_stack(NULL, sp);
 273 }
 274
 275 void dump_stack(void)
 276 {
 277         show_task(NULL);
 278 }
 279 /* Needed by any user of WARN_ON in view of the defn in include/asm-sh/bug.h */
 280 EXPORT_SYMBOL(dump_stack);
 281
 282 static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
 283                 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk)
 284 {
 285         show_excp_regs(fn_name, trapnr, signr, regs);
 286         tsk->thread.error_code = error_code;
 287         tsk->thread.trap_no = trapnr;
 288
 289         if (user_mode(regs))
 290                 force_sig(signr, tsk);
 291
 292         die_if_no_fixup(str, regs, error_code);
 293 }
 294
 295 static int read_opcode(unsigned long long pc, unsigned long *result_opcode, int from_user_mode)
 296 {
 297         int get_user_error;
 298         unsigned long aligned_pc;
 299         unsigned long opcode;
 300
 301         if ((pc & 3) == 1) {
 302                 /* SHmedia */
 303                 aligned_pc = pc & ~3;
 304                 if (from_user_mode) {
 305                         if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
 306                                 get_user_error = -EFAULT;
 307                         } else {
 308                                 get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
 309                                 *result_opcode = opcode;
 310                         }
 311                         return get_user_error;
 312                 } else {
 313                         /* If the fault was in the kernel, we can either read
 314                          * this directly, or if not, we fault.
 315                         */
 316                         *result_opcode = *(unsigned long *) aligned_pc;
 317                         return 0;
 318                 }
 319         } else if ((pc & 1) == 0) {
 320                 /* SHcompact */
 321                 /* TODO : provide handling for this.  We don't really support
 322                    user-mode SHcompact yet, and for a kernel fault, this would
 323                    have to come from a module built for SHcompact.  */
 324                 return -EFAULT;
 325         } else {
 326                 /* misaligned */
 327                 return -EFAULT;
 328         }
 329 }
 330
 331 static int address_is_sign_extended(__u64 a)
 332 {
 333         __u64 b;
 334 #if (NEFF == 32)
 335         b = (__u64)(__s64)(__s32)(a & 0xffffffffUL);
 336         return (b == a) ? 1 : 0;
 337 #else
 338 #error "Sign extend check only works for NEFF==32"
 339 #endif
 340 }
 341
 342 static int generate_and_check_address(struct pt_regs *regs,
 343                                       __u32 opcode,
 344                                       int displacement_not_indexed,
 345                                       int width_shift,
 346                                       __u64 *address)
 347 {
 348         /* return -1 for fault, 0 for OK */
 349
 350         __u64 base_address, addr;
 351         int basereg;
 352
 353         basereg = (opcode >> 20) & 0x3f;
 354         base_address = regs->regs[basereg];
 355         if (displacement_not_indexed) {
 356                 __s64 displacement;
 357                 displacement = (opcode >> 10) & 0x3ff;
 358                 displacement = ((displacement << 54) >> 54); /* sign extend */
 359                 addr = (__u64)((__s64)base_address + (displacement << width_shift));
 360         } else {
 361                 __u64 offset;
 362                 int offsetreg;
 363                 offsetreg = (opcode >> 10) & 0x3f;
 364                 offset = regs->regs[offsetreg];
 365                 addr = base_address + offset;
 366         }
 367
 368         /* Check sign extended */
 369         if (!address_is_sign_extended(addr)) {
 370                 return -1;
 371         }
 372
 373         /* Check accessible.  For misaligned access in the kernel, assume the
 374            address is always accessible (and if not, just fault when the
 375            load/store gets done.) */
 376         if (user_mode(regs)) {
 377                 if (addr >= TASK_SIZE) {
 378                         return -1;
 379                 }
 380                 /* Do access_ok check later - it depends on whether it's a load or a store. */
 381         }
 382
 383         *address = addr;
 384         return 0;
 385 }
 386
 387 static int user_mode_unaligned_fixup_count = 10;
 388 static int user_mode_unaligned_fixup_enable = 1;
 389 static int kernel_mode_unaligned_fixup_count = 32;
 390
 391 static void misaligned_kernel_word_load(__u64 address, int do_sign_extend, __u64 *result)
 392 {
 393         unsigned short x;
 394         unsigned char *p, *q;
 395         p = (unsigned char *) (int) address;
 396         q = (unsigned char *) &x;
 397         q[0] = p[0];
 398         q[1] = p[1];
 399
 400         if (do_sign_extend) {
 401                 *result = (__u64)(__s64) *(short *) &x;
 402         } else {
 403                 *result = (__u64) x;
 404         }
 405 }
 406
 407 static void misaligned_kernel_word_store(__u64 address, __u64 value)
 408 {
 409         unsigned short x;
 410         unsigned char *p, *q;
 411         p = (unsigned char *) (int) address;
 412         q = (unsigned char *) &x;
 413
 414         x = (__u16) value;
 415         p[0] = q[0];
 416         p[1] = q[1];
 417 }
 418
 419 static int misaligned_load(struct pt_regs *regs,
 420                            __u32 opcode,
 421                            int displacement_not_indexed,
 422                            int width_shift,
 423                            int do_sign_extend)
 424 {
 425         /* Return -1 for a fault, 0 for OK */
 426         int error;
 427         int destreg;
 428         __u64 address;
 429
 430         error = generate_and_check_address(regs, opcode,
 431                         displacement_not_indexed, width_shift, &address);
 432         if (error < 0) {
 433                 return error;
 434         }
 435
 436         perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, address);
 437
 438         destreg = (opcode >> 4) & 0x3f;
 439         if (user_mode(regs)) {
 440                 __u64 buffer;
 441
 442                 if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
 443                         return -1;
 444                 }
 445
 446                 if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
 447                         return -1; /* fault */
 448                 }
 449                 switch (width_shift) {
 450                 case 1:
 451                         if (do_sign_extend) {
 452                                 regs->regs[destreg] = (__u64)(__s64) *(__s16 *) &buffer;
 453                         } else {
 454                                 regs->regs[destreg] = (__u64) *(__u16 *) &buffer;
 455                         }
 456                         break;
 457                 case 2:
 458                         regs->regs[destreg] = (__u64)(__s64) *(__s32 *) &buffer;
 459                         break;
 460                 case 3:
 461                         regs->regs[destreg] = buffer;
 462                         break;
 463                 default:
 464                         printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
 465                                 width_shift, (unsigned long) regs->pc);
 466                         break;
 467                 }
 468         } else {
 469                 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
 470                 __u64 lo, hi;
 471
 472                 switch (width_shift) {
 473                 case 1:
 474                         misaligned_kernel_word_load(address, do_sign_extend, &regs->regs[destreg]);
 475                         break;
 476                 case 2:
 477                         asm ("ldlo.l %1, 0, %0" : "=r" (lo) : "r" (address));
 478                         asm ("ldhi.l %1, 3, %0" : "=r" (hi) : "r" (address));
 479                         regs->regs[destreg] = lo | hi;
 480                         break;
 481                 case 3:
 482                         asm ("ldlo.q %1, 0, %0" : "=r" (lo) : "r" (address));
 483                         asm ("ldhi.q %1, 7, %0" : "=r" (hi) : "r" (address));
 484                         regs->regs[destreg] = lo | hi;
 485                         break;
 486
 487                 default:
 488                         printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
 489                                 width_shift, (unsigned long) regs->pc);
 490                         break;
 491                 }
 492         }
 493
 494         return 0;
 495
 496 }
 497
 498 static int misaligned_store(struct pt_regs *regs,
 499                             __u32 opcode,
 500                             int displacement_not_indexed,
 501                             int width_shift)
 502 {
 503         /* Return -1 for a fault, 0 for OK */
 504         int error;
 505         int srcreg;
 506         __u64 address;
 507
 508         error = generate_and_check_address(regs, opcode,
 509                         displacement_not_indexed, width_shift, &address);
 510         if (error < 0) {
 511                 return error;
 512         }
 513
 514         perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, address);
 515
 516         srcreg = (opcode >> 4) & 0x3f;
 517         if (user_mode(regs)) {
 518                 __u64 buffer;
 519
 520                 if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
 521                         return -1;
 522                 }
 523
 524                 switch (width_shift) {
 525                 case 1:
 526                         *(__u16 *) &buffer = (__u16) regs->regs[srcreg];
 527                         break;
 528                 case 2:
 529                         *(__u32 *) &buffer = (__u32) regs->regs[srcreg];
 530                         break;
 531                 case 3:
 532                         buffer = regs->regs[srcreg];
 533                         break;
 534                 default:
 535                         printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
 536                                 width_shift, (unsigned long) regs->pc);
 537                         break;
 538                 }
 539
 540                 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
 541                         return -1; /* fault */
 542                 }
 543         } else {
 544                 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
 545                 __u64 val = regs->regs[srcreg];
 546
 547                 switch (width_shift) {
 548                 case 1:
 549                         misaligned_kernel_word_store(address, val);
 550                         break;
 551                 case 2:
 552                         asm ("stlo.l %1, 0, %0" : : "r" (val), "r" (address));
 553                         asm ("sthi.l %1, 3, %0" : : "r" (val), "r" (address));
 554                         break;
 555                 case 3:
 556                         asm ("stlo.q %1, 0, %0" : : "r" (val), "r" (address));
 557                         asm ("sthi.q %1, 7, %0" : : "r" (val), "r" (address));
 558                         break;
 559
 560                 default:
 561                         printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
 562                                 width_shift, (unsigned long) regs->pc);
 563                         break;
 564                 }
 565         }
 566
 567         return 0;
 568
 569 }
 570
 571 /* Never need to fix up misaligned FPU accesses within the kernel since that's a real
 572    error. */
 573 static int misaligned_fpu_load(struct pt_regs *regs,
 574                            __u32 opcode,
 575                            int displacement_not_indexed,
 576                            int width_shift,
 577                            int do_paired_load)
 578 {
 579         /* Return -1 for a fault, 0 for OK */
 580         int error;
 581         int destreg;
 582         __u64 address;
 583
 584         error = generate_and_check_address(regs, opcode,
 585                         displacement_not_indexed, width_shift, &address);
 586         if (error < 0) {
 587                 return error;
 588         }
 589
 590         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, address);
 591
 592         destreg = (opcode >> 4) & 0x3f;
 593         if (user_mode(regs)) {
 594                 __u64 buffer;
 595                 __u32 buflo, bufhi;
 596
 597                 if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
 598                         return -1;
 599                 }
 600
 601                 if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
 602                         return -1; /* fault */
 603                 }
 604                 /* 'current' may be the current owner of the FPU state, so
 605                    context switch the registers into memory so they can be
 606                    indexed by register number. */
 607                 if (last_task_used_math == current) {
 608                         enable_fpu();
 609                         save_fpu(current);
 610                         disable_fpu();
 611                         last_task_used_math = NULL;
 612                         regs->sr |= SR_FD;
 613                 }
 614
 615                 buflo = *(__u32*) &buffer;
 616                 bufhi = *(1 + (__u32*) &buffer);
 617
 618                 switch (width_shift) {
 619                 case 2:
 620                         current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
 621                         break;
 622                 case 3:
 623                         if (do_paired_load) {
 624                                 current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
 625                                 current->thread.xstate->hardfpu.fp_regs[destreg+1] = bufhi;
 626                         } else {
 627 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
 628                                 current->thread.xstate->hardfpu.fp_regs[destreg] = bufhi;
 629                                 current->thread.xstate->hardfpu.fp_regs[destreg+1] = buflo;
 630 #else
 631                                 current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
 632                                 current->thread.xstate->hardfpu.fp_regs[destreg+1] = bufhi;
 633 #endif
 634                         }
 635                         break;
 636                 default:
 637                         printk("Unexpected width_shift %d in misaligned_fpu_load, PC=%08lx\n",
 638                                 width_shift, (unsigned long) regs->pc);
 639                         break;
 640                 }
 641                 return 0;
 642         } else {
 643                 die ("Misaligned FPU load inside kernel", regs, 0);
 644                 return -1;
 645         }
 646
 647
 648 }
 649
 650 static int misaligned_fpu_store(struct pt_regs *regs,
 651                            __u32 opcode,
 652                            int displacement_not_indexed,
 653                            int width_shift,
 654                            int do_paired_load)
 655 {
 656         /* Return -1 for a fault, 0 for OK */
 657         int error;
 658         int srcreg;
 659         __u64 address;
 660
 661         error = generate_and_check_address(regs, opcode,
 662                         displacement_not_indexed, width_shift, &address);
 663         if (error < 0) {
 664                 return error;
 665         }
 666
 667         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, address);
 668
 669         srcreg = (opcode >> 4) & 0x3f;
 670         if (user_mode(regs)) {
 671                 __u64 buffer;
 672                 /* Initialise these to NaNs. */
 673                 __u32 buflo=0xffffffffUL, bufhi=0xffffffffUL;
 674
 675                 if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
 676                         return -1;
 677                 }
 678
 679                 /* 'current' may be the current owner of the FPU state, so
 680                    context switch the registers into memory so they can be
 681                    indexed by register number. */
 682                 if (last_task_used_math == current) {
 683                         enable_fpu();
 684                         save_fpu(current);
 685                         disable_fpu();
 686                         last_task_used_math = NULL;
 687                         regs->sr |= SR_FD;
 688                 }
 689
 690                 switch (width_shift) {
 691                 case 2:
 692                         buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
 693                         break;
 694                 case 3:
 695                         if (do_paired_load) {
 696                                 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
 697                                 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
 698                         } else {
 699 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
 700                                 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg];
 701                                 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
 702 #else
 703                                 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
 704                                 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
 705 #endif
 706                         }
 707                         break;
 708                 default:
 709                         printk("Unexpected width_shift %d in misaligned_fpu_store, PC=%08lx\n",
 710                                 width_shift, (unsigned long) regs->pc);
 711                         break;
 712                 }
 713
 714                 *(__u32*) &buffer = buflo;
 715                 *(1 + (__u32*) &buffer) = bufhi;
 716                 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
 717                         return -1; /* fault */
 718                 }
 719                 return 0;
 720         } else {
 721                 die ("Misaligned FPU load inside kernel", regs, 0);
 722                 return -1;
 723         }
 724 }
 725
 726 static int misaligned_fixup(struct pt_regs *regs)
 727 {
 728         unsigned long opcode;
 729         int error;
 730         int major, minor;
 731
 732         if (!user_mode_unaligned_fixup_enable)
 733                 return -1;
 734
 735         error = read_opcode(regs->pc, &opcode, user_mode(regs));
 736         if (error < 0) {
 737                 return error;
 738         }
 739         major = (opcode >> 26) & 0x3f;
 740         minor = (opcode >> 16) & 0xf;
 741
 742         if (user_mode(regs) && (user_mode_unaligned_fixup_count > 0)) {
 743                 --user_mode_unaligned_fixup_count;
 744                 /* Only do 'count' worth of these reports, to remove a potential DoS against syslog */
 745                 printk("Fixing up unaligned userspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
 746                        current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
 747         } else if (!user_mode(regs) && (kernel_mode_unaligned_fixup_count > 0)) {
 748                 --kernel_mode_unaligned_fixup_count;
 749                 if (in_interrupt()) {
 750                         printk("Fixing up unaligned kernelspace access in interrupt pc=0x%08x ins=0x%08lx\n",
 751                                (__u32)regs->pc, opcode);
 752                 } else {
 753                         printk("Fixing up unaligned kernelspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
 754                                current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
 755                 }
 756         }
 757
 758
 759         switch (major) {
 760                 case (0x84>>2): /* LD.W */
 761                         error = misaligned_load(regs, opcode, 1, 1, 1);
 762                         break;
 763                 case (0xb0>>2): /* LD.UW */
 764                         error = misaligned_load(regs, opcode, 1, 1, 0);
 765                         break;
 766                 case (0x88>>2): /* LD.L */
 767                         error = misaligned_load(regs, opcode, 1, 2, 1);
 768                         break;
 769                 case (0x8c>>2): /* LD.Q */
 770                         error = misaligned_load(regs, opcode, 1, 3, 0);
 771                         break;
 772
 773                 case (0xa4>>2): /* ST.W */
 774                         error = misaligned_store(regs, opcode, 1, 1);
 775                         break;
 776                 case (0xa8>>2): /* ST.L */
 777                         error = misaligned_store(regs, opcode, 1, 2);
 778                         break;
 779                 case (0xac>>2): /* ST.Q */
 780                         error = misaligned_store(regs, opcode, 1, 3);
 781                         break;
 782
 783                 case (0x40>>2): /* indexed loads */
 784                         switch (minor) {
 785                                 case 0x1: /* LDX.W */
 786                                         error = misaligned_load(regs, opcode, 0, 1, 1);
 787                                         break;
 788                                 case 0x5: /* LDX.UW */
 789                                         error = misaligned_load(regs, opcode, 0, 1, 0);
 790                                         break;
 791                                 case 0x2: /* LDX.L */
 792                                         error = misaligned_load(regs, opcode, 0, 2, 1);
 793                                         break;
 794                                 case 0x3: /* LDX.Q */
 795                                         error = misaligned_load(regs, opcode, 0, 3, 0);
 796                                         break;
 797                                 default:
 798                                         error = -1;
 799                                         break;
 800                         }
 801                         break;
 802
 803                 case (0x60>>2): /* indexed stores */
 804                         switch (minor) {
 805                                 case 0x1: /* STX.W */
 806                                         error = misaligned_store(regs, opcode, 0, 1);
 807                                         break;
 808                                 case 0x2: /* STX.L */
 809                                         error = misaligned_store(regs, opcode, 0, 2);
 810                                         break;
 811                                 case 0x3: /* STX.Q */
 812                                         error = misaligned_store(regs, opcode, 0, 3);
 813                                         break;
 814                                 default:
 815                                         error = -1;
 816                                         break;
 817                         }
 818                         break;
 819
 820                 case (0x94>>2): /* FLD.S */
 821                         error = misaligned_fpu_load(regs, opcode, 1, 2, 0);
 822                         break;
 823                 case (0x98>>2): /* FLD.P */
 824                         error = misaligned_fpu_load(regs, opcode, 1, 3, 1);
 825                         break;
 826                 case (0x9c>>2): /* FLD.D */
 827                         error = misaligned_fpu_load(regs, opcode, 1, 3, 0);
 828                         break;
 829                 case (0x1c>>2): /* floating indexed loads */
 830                         switch (minor) {
 831                         case 0x8: /* FLDX.S */
 832                                 error = misaligned_fpu_load(regs, opcode, 0, 2, 0);
 833                                 break;
 834                         case 0xd: /* FLDX.P */
 835                                 error = misaligned_fpu_load(regs, opcode, 0, 3, 1);
 836                                 break;
 837                         case 0x9: /* FLDX.D */
 838                                 error = misaligned_fpu_load(regs, opcode, 0, 3, 0);
 839                                 break;
 840                         default:
 841                                 error = -1;
 842                                 break;
 843                         }
 844                         break;
 845                 case (0xb4>>2): /* FLD.S */
 846                         error = misaligned_fpu_store(regs, opcode, 1, 2, 0);
 847                         break;
 848                 case (0xb8>>2): /* FLD.P */
 849                         error = misaligned_fpu_store(regs, opcode, 1, 3, 1);
 850                         break;
 851                 case (0xbc>>2): /* FLD.D */
 852                         error = misaligned_fpu_store(regs, opcode, 1, 3, 0);
 853                         break;
 854                 case (0x3c>>2): /* floating indexed stores */
 855                         switch (minor) {
 856                         case 0x8: /* FSTX.S */
 857                                 error = misaligned_fpu_store(regs, opcode, 0, 2, 0);
 858                                 break;
 859                         case 0xd: /* FSTX.P */
 860                                 error = misaligned_fpu_store(regs, opcode, 0, 3, 1);
 861                                 break;
 862                         case 0x9: /* FSTX.D */
 863                                 error = misaligned_fpu_store(regs, opcode, 0, 3, 0);
 864                                 break;
 865                         default:
 866                                 error = -1;
 867                                 break;
 868                         }
 869                         break;
 870
 871                 default:
 872                         /* Fault */
 873                         error = -1;
 874                         break;
 875         }
 876
 877         if (error < 0) {
 878                 return error;
 879         } else {
 880                 regs->pc += 4; /* Skip the instruction that's just been emulated */
 881                 return 0;
 882         }
 883
 884 }
 885
 886 static ctl_table unaligned_table[] = {
 887         {
 888                 .procname       = "kernel_reports",
 889                 .data           = &kernel_mode_unaligned_fixup_count,
 890                 .maxlen         = sizeof(int),
 891                 .mode           = 0644,
 892                 .proc_handler   = proc_dointvec
 893         },
 894         {
 895                 .procname       = "user_reports",
 896                 .data           = &user_mode_unaligned_fixup_count,
 897                 .maxlen         = sizeof(int),
 898                 .mode           = 0644,
 899                 .proc_handler   = proc_dointvec
 900         },
 901         {
 902                 .procname       = "user_enable",
 903                 .data           = &user_mode_unaligned_fixup_enable,
 904                 .maxlen         = sizeof(int),
 905                 .mode           = 0644,
 906                 .proc_handler   = proc_dointvec},
 907         {}
 908 };
 909
 910 static ctl_table unaligned_root[] = {
 911         {
 912                 .procname       = "unaligned_fixup",
 913                 .mode           = 0555,
 914                 .child          = unaligned_table
 915         },
 916         {}
 917 };
 918
 919 static ctl_table sh64_root[] = {
 920         {
 921                 .procname       = "sh64",
 922                 .mode           = 0555,
 923                 .child          = unaligned_root
 924         },
 925         {}
 926 };
 927 static struct ctl_table_header *sysctl_header;
 928 static int __init init_sysctl(void)
 929 {
 930         sysctl_header = register_sysctl_table(sh64_root);
 931         return 0;
 932 }
 933
 934 __initcall(init_sysctl);
 935
 936
 937 asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs)
 938 {
 939         u64 peek_real_address_q(u64 addr);
 940         u64 poke_real_address_q(u64 addr, u64 val);
 941         unsigned long long DM_EXP_CAUSE_PHY = 0x0c100010;
 942         unsigned long long exp_cause;
 943         /* It's not worth ioremapping the debug module registers for the amount
 944            of access we make to them - just go direct to their physical
 945            addresses. */
 946         exp_cause = peek_real_address_q(DM_EXP_CAUSE_PHY);
 947         if (exp_cause & ~4) {
 948                 printk("DM.EXP_CAUSE had unexpected bits set (=%08lx)\n",
 949                         (unsigned long)(exp_cause & 0xffffffff));
 950         }
 951         show_state();
 952         /* Clear all DEBUGINT causes */
 953         poke_real_address_q(DM_EXP_CAUSE_PHY, 0x0);
 954 }
 955
 956 void __cpuinit per_cpu_trap_init(void)
 957 {
 958         /* Nothing to do for now, VBR initialization later. */
 959 }