2 * arch/sh/kernel/traps_64.c
4 * Copyright (C) 2000, 2001 Paolo Alberelli
5 * Copyright (C) 2003, 2004 Paul Mundt
6 * Copyright (C) 2003, 2004 Richard Curnow
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/errno.h>
16 #include <linux/ptrace.h>
17 #include <linux/timer.h>
19 #include <linux/smp.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/kallsyms.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysctl.h>
26 #include <linux/module.h>
27 #include <linux/perf_event.h>
28 #include <asm/system.h>
29 #include <asm/uaccess.h>
31 #include <asm/atomic.h>
32 #include <asm/processor.h>
33 #include <asm/pgtable.h>
36 #undef DEBUG_EXCEPTION
37 #ifdef DEBUG_EXCEPTION
38 /* implemented in ../lib/dbg.c */
39 extern void show_excp_regs(char *fname, int trapnr, int signr,
40 struct pt_regs *regs);
42 #define show_excp_regs(a, b, c, d)
45 static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
46 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk);
48 #define DO_ERROR(trapnr, signr, str, name, tsk) \
49 asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \
51 do_unhandled_exception(trapnr, signr, str, __stringify(name), error_code, regs, current); \
54 static DEFINE_SPINLOCK(die_lock);
56 void die(const char * str, struct pt_regs * regs, long err)
59 spin_lock_irq(&die_lock);
60 printk("%s: %lx\n", str, (err & 0xffffff));
62 spin_unlock_irq(&die_lock);
66 static inline void die_if_kernel(const char * str, struct pt_regs * regs, long err)
72 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
74 if (!user_mode(regs)) {
75 const struct exception_table_entry *fixup;
76 fixup = search_exception_tables(regs->pc);
78 regs->pc = fixup->fixup;
85 DO_ERROR(13, SIGILL, "illegal slot instruction", illegal_slot_inst, current)
86 DO_ERROR(87, SIGSEGV, "address error (exec)", address_error_exec, current)
89 /* Implement misaligned load/store handling for kernel (and optionally for user
90 mode too). Limitation : only SHmedia mode code is handled - there is no
91 handling at all for misaligned accesses occurring in SHcompact code yet. */
93 static int misaligned_fixup(struct pt_regs *regs);
95 asmlinkage void do_address_error_load(unsigned long error_code, struct pt_regs *regs)
97 if (misaligned_fixup(regs) < 0) {
98 do_unhandled_exception(7, SIGSEGV, "address error(load)",
99 "do_address_error_load",
100 error_code, regs, current);
105 asmlinkage void do_address_error_store(unsigned long error_code, struct pt_regs *regs)
107 if (misaligned_fixup(regs) < 0) {
108 do_unhandled_exception(8, SIGSEGV, "address error(store)",
109 "do_address_error_store",
110 error_code, regs, current);
115 #if defined(CONFIG_SH64_ID2815_WORKAROUND)
117 #define OPCODE_INVALID 0
118 #define OPCODE_USER_VALID 1
119 #define OPCODE_PRIV_VALID 2
121 /* getcon/putcon - requires checking which control register is referenced. */
122 #define OPCODE_CTRL_REG 3
124 /* Table of valid opcodes for SHmedia mode.
125 Form a 10-bit value by concatenating the major/minor opcodes i.e.
126 opcode[31:26,20:16]. The 6 MSBs of this value index into the following
127 array. The 4 LSBs select the bit-pair in the entry (bits 1:0 correspond to
128 LSBs==4'b0000 etc). */
129 static unsigned long shmedia_opcode_table[64] = {
130 0x55554044,0x54445055,0x15141514,0x14541414,0x00000000,0x10001000,0x01110055,0x04050015,
131 0x00000444,0xc0000000,0x44545515,0x40405555,0x55550015,0x10005555,0x55555505,0x04050000,
132 0x00000555,0x00000404,0x00040445,0x15151414,0x00000000,0x00000000,0x00000000,0x00000000,
133 0x00000055,0x40404444,0x00000404,0xc0009495,0x00000000,0x00000000,0x00000000,0x00000000,
134 0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
135 0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
136 0x80005050,0x04005055,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
137 0x81055554,0x00000404,0x55555555,0x55555555,0x00000000,0x00000000,0x00000000,0x00000000
140 void do_reserved_inst(unsigned long error_code, struct pt_regs *regs)
142 /* Workaround SH5-101 cut2 silicon defect #2815 :
143 in some situations, inter-mode branches from SHcompact -> SHmedia
144 which should take ITLBMISS or EXECPROT exceptions at the target
145 falsely take RESINST at the target instead. */
147 unsigned long opcode = 0x6ff4fff0; /* guaranteed reserved opcode */
148 unsigned long pc, aligned_pc;
152 char *exception_name = "reserved_instruction";
156 /* SHmedia : check for defect. This requires executable vmas
157 to be readable too. */
158 aligned_pc = pc & ~3;
159 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
160 get_user_error = -EFAULT;
162 get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
164 if (get_user_error >= 0) {
165 unsigned long index, shift;
166 unsigned long major, minor, combined;
167 unsigned long reserved_field;
168 reserved_field = opcode & 0xf; /* These bits are currently reserved as zero in all valid opcodes */
169 major = (opcode >> 26) & 0x3f;
170 minor = (opcode >> 16) & 0xf;
171 combined = (major << 4) | minor;
174 if (reserved_field == 0) {
175 int opcode_state = (shmedia_opcode_table[index] >> shift) & 0x3;
176 switch (opcode_state) {
180 case OPCODE_USER_VALID:
181 /* Restart the instruction : the branch to the instruction will now be from an RTE
182 not from SHcompact so the silicon defect won't be triggered. */
184 case OPCODE_PRIV_VALID:
185 if (!user_mode(regs)) {
186 /* Should only ever get here if a module has
187 SHcompact code inside it. If so, the same fix up is needed. */
188 return; /* same reason */
190 /* Otherwise, user mode trying to execute a privileged instruction -
191 fall through to trap. */
193 case OPCODE_CTRL_REG:
194 /* If in privileged mode, return as above. */
195 if (!user_mode(regs)) return;
196 /* In user mode ... */
197 if (combined == 0x9f) { /* GETCON */
198 unsigned long regno = (opcode >> 20) & 0x3f;
202 /* Otherwise, reserved or privileged control register, => trap */
203 } else if (combined == 0x1bf) { /* PUTCON */
204 unsigned long regno = (opcode >> 4) & 0x3f;
208 /* Otherwise, reserved or privileged control register, => trap */
214 /* Fall through to trap. */
218 /* fall through to normal resinst processing */
220 /* Error trying to read opcode. This typically means a
221 real fault, not a RESINST any more. So change the
224 exception_name = "address error (exec)";
229 do_unhandled_exception(trapnr, signr, exception_name, "do_reserved_inst", error_code, regs, current);
232 #else /* CONFIG_SH64_ID2815_WORKAROUND */
234 /* If the workaround isn't needed, this is just a straightforward reserved
236 DO_ERROR(12, SIGILL, "reserved instruction", reserved_inst, current)
238 #endif /* CONFIG_SH64_ID2815_WORKAROUND */
240 /* Called with interrupts disabled */
241 asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs)
243 show_excp_regs(__func__, -1, -1, regs);
244 die_if_kernel("exception", regs, ex);
247 int do_unknown_trapa(unsigned long scId, struct pt_regs *regs)
250 printk("System call ID error: [0x1#args:8 #syscall:16 0x%lx]\n", scId);
252 die_if_kernel("unknown trapa", regs, scId);
257 void show_stack(struct task_struct *tsk, unsigned long *sp)
259 #ifdef CONFIG_KALLSYMS
260 extern void sh64_unwind(struct pt_regs *regs);
261 struct pt_regs *regs;
263 regs = tsk ? tsk->thread.kregs : NULL;
267 printk(KERN_ERR "Can't backtrace on sh64 without CONFIG_KALLSYMS\n");
271 void show_task(unsigned long *sp)
273 show_stack(NULL, sp);
276 void dump_stack(void)
280 /* Needed by any user of WARN_ON in view of the defn in include/asm-sh/bug.h */
281 EXPORT_SYMBOL(dump_stack);
283 static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
284 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk)
286 show_excp_regs(fn_name, trapnr, signr, regs);
287 tsk->thread.error_code = error_code;
288 tsk->thread.trap_no = trapnr;
291 force_sig(signr, tsk);
293 die_if_no_fixup(str, regs, error_code);
296 static int read_opcode(unsigned long long pc, unsigned long *result_opcode, int from_user_mode)
299 unsigned long aligned_pc;
300 unsigned long opcode;
304 aligned_pc = pc & ~3;
305 if (from_user_mode) {
306 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
307 get_user_error = -EFAULT;
309 get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
310 *result_opcode = opcode;
312 return get_user_error;
314 /* If the fault was in the kernel, we can either read
315 * this directly, or if not, we fault.
317 *result_opcode = *(unsigned long *) aligned_pc;
320 } else if ((pc & 1) == 0) {
322 /* TODO : provide handling for this. We don't really support
323 user-mode SHcompact yet, and for a kernel fault, this would
324 have to come from a module built for SHcompact. */
332 static int address_is_sign_extended(__u64 a)
336 b = (__u64)(__s64)(__s32)(a & 0xffffffffUL);
337 return (b == a) ? 1 : 0;
339 #error "Sign extend check only works for NEFF==32"
343 static int generate_and_check_address(struct pt_regs *regs,
345 int displacement_not_indexed,
349 /* return -1 for fault, 0 for OK */
351 __u64 base_address, addr;
354 basereg = (opcode >> 20) & 0x3f;
355 base_address = regs->regs[basereg];
356 if (displacement_not_indexed) {
358 displacement = (opcode >> 10) & 0x3ff;
359 displacement = ((displacement << 54) >> 54); /* sign extend */
360 addr = (__u64)((__s64)base_address + (displacement << width_shift));
364 offsetreg = (opcode >> 10) & 0x3f;
365 offset = regs->regs[offsetreg];
366 addr = base_address + offset;
369 /* Check sign extended */
370 if (!address_is_sign_extended(addr)) {
374 /* Check accessible. For misaligned access in the kernel, assume the
375 address is always accessible (and if not, just fault when the
376 load/store gets done.) */
377 if (user_mode(regs)) {
378 if (addr >= TASK_SIZE) {
381 /* Do access_ok check later - it depends on whether it's a load or a store. */
388 static int user_mode_unaligned_fixup_count = 10;
389 static int user_mode_unaligned_fixup_enable = 1;
390 static int kernel_mode_unaligned_fixup_count = 32;
392 static void misaligned_kernel_word_load(__u64 address, int do_sign_extend, __u64 *result)
395 unsigned char *p, *q;
396 p = (unsigned char *) (int) address;
397 q = (unsigned char *) &x;
401 if (do_sign_extend) {
402 *result = (__u64)(__s64) *(short *) &x;
408 static void misaligned_kernel_word_store(__u64 address, __u64 value)
411 unsigned char *p, *q;
412 p = (unsigned char *) (int) address;
413 q = (unsigned char *) &x;
420 static int misaligned_load(struct pt_regs *regs,
422 int displacement_not_indexed,
426 /* Return -1 for a fault, 0 for OK */
431 error = generate_and_check_address(regs, opcode,
432 displacement_not_indexed, width_shift, &address);
437 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, address);
439 destreg = (opcode >> 4) & 0x3f;
440 if (user_mode(regs)) {
443 if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
447 if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
448 return -1; /* fault */
450 switch (width_shift) {
452 if (do_sign_extend) {
453 regs->regs[destreg] = (__u64)(__s64) *(__s16 *) &buffer;
455 regs->regs[destreg] = (__u64) *(__u16 *) &buffer;
459 regs->regs[destreg] = (__u64)(__s64) *(__s32 *) &buffer;
462 regs->regs[destreg] = buffer;
465 printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
466 width_shift, (unsigned long) regs->pc);
470 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
473 switch (width_shift) {
475 misaligned_kernel_word_load(address, do_sign_extend, ®s->regs[destreg]);
478 asm ("ldlo.l %1, 0, %0" : "=r" (lo) : "r" (address));
479 asm ("ldhi.l %1, 3, %0" : "=r" (hi) : "r" (address));
480 regs->regs[destreg] = lo | hi;
483 asm ("ldlo.q %1, 0, %0" : "=r" (lo) : "r" (address));
484 asm ("ldhi.q %1, 7, %0" : "=r" (hi) : "r" (address));
485 regs->regs[destreg] = lo | hi;
489 printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
490 width_shift, (unsigned long) regs->pc);
499 static int misaligned_store(struct pt_regs *regs,
501 int displacement_not_indexed,
504 /* Return -1 for a fault, 0 for OK */
509 error = generate_and_check_address(regs, opcode,
510 displacement_not_indexed, width_shift, &address);
515 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, address);
517 srcreg = (opcode >> 4) & 0x3f;
518 if (user_mode(regs)) {
521 if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
525 switch (width_shift) {
527 *(__u16 *) &buffer = (__u16) regs->regs[srcreg];
530 *(__u32 *) &buffer = (__u32) regs->regs[srcreg];
533 buffer = regs->regs[srcreg];
536 printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
537 width_shift, (unsigned long) regs->pc);
541 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
542 return -1; /* fault */
545 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
546 __u64 val = regs->regs[srcreg];
548 switch (width_shift) {
550 misaligned_kernel_word_store(address, val);
553 asm ("stlo.l %1, 0, %0" : : "r" (val), "r" (address));
554 asm ("sthi.l %1, 3, %0" : : "r" (val), "r" (address));
557 asm ("stlo.q %1, 0, %0" : : "r" (val), "r" (address));
558 asm ("sthi.q %1, 7, %0" : : "r" (val), "r" (address));
562 printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
563 width_shift, (unsigned long) regs->pc);
572 /* Never need to fix up misaligned FPU accesses within the kernel since that's a real
574 static int misaligned_fpu_load(struct pt_regs *regs,
576 int displacement_not_indexed,
580 /* Return -1 for a fault, 0 for OK */
585 error = generate_and_check_address(regs, opcode,
586 displacement_not_indexed, width_shift, &address);
591 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, address);
593 destreg = (opcode >> 4) & 0x3f;
594 if (user_mode(regs)) {
598 if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
602 if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
603 return -1; /* fault */
605 /* 'current' may be the current owner of the FPU state, so
606 context switch the registers into memory so they can be
607 indexed by register number. */
608 if (last_task_used_math == current) {
612 last_task_used_math = NULL;
616 buflo = *(__u32*) &buffer;
617 bufhi = *(1 + (__u32*) &buffer);
619 switch (width_shift) {
621 current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
624 if (do_paired_load) {
625 current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
626 current->thread.xstate->hardfpu.fp_regs[destreg+1] = bufhi;
628 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
629 current->thread.xstate->hardfpu.fp_regs[destreg] = bufhi;
630 current->thread.xstate->hardfpu.fp_regs[destreg+1] = buflo;
632 current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
633 current->thread.xstate->hardfpu.fp_regs[destreg+1] = bufhi;
638 printk("Unexpected width_shift %d in misaligned_fpu_load, PC=%08lx\n",
639 width_shift, (unsigned long) regs->pc);
644 die ("Misaligned FPU load inside kernel", regs, 0);
651 static int misaligned_fpu_store(struct pt_regs *regs,
653 int displacement_not_indexed,
657 /* Return -1 for a fault, 0 for OK */
662 error = generate_and_check_address(regs, opcode,
663 displacement_not_indexed, width_shift, &address);
668 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, address);
670 srcreg = (opcode >> 4) & 0x3f;
671 if (user_mode(regs)) {
673 /* Initialise these to NaNs. */
674 __u32 buflo=0xffffffffUL, bufhi=0xffffffffUL;
676 if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
680 /* 'current' may be the current owner of the FPU state, so
681 context switch the registers into memory so they can be
682 indexed by register number. */
683 if (last_task_used_math == current) {
687 last_task_used_math = NULL;
691 switch (width_shift) {
693 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
696 if (do_paired_load) {
697 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
698 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
700 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
701 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg];
702 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
704 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
705 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
710 printk("Unexpected width_shift %d in misaligned_fpu_store, PC=%08lx\n",
711 width_shift, (unsigned long) regs->pc);
715 *(__u32*) &buffer = buflo;
716 *(1 + (__u32*) &buffer) = bufhi;
717 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
718 return -1; /* fault */
722 die ("Misaligned FPU load inside kernel", regs, 0);
727 static int misaligned_fixup(struct pt_regs *regs)
729 unsigned long opcode;
733 if (!user_mode_unaligned_fixup_enable)
736 error = read_opcode(regs->pc, &opcode, user_mode(regs));
740 major = (opcode >> 26) & 0x3f;
741 minor = (opcode >> 16) & 0xf;
743 if (user_mode(regs) && (user_mode_unaligned_fixup_count > 0)) {
744 --user_mode_unaligned_fixup_count;
745 /* Only do 'count' worth of these reports, to remove a potential DoS against syslog */
746 printk("Fixing up unaligned userspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
747 current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
748 } else if (!user_mode(regs) && (kernel_mode_unaligned_fixup_count > 0)) {
749 --kernel_mode_unaligned_fixup_count;
750 if (in_interrupt()) {
751 printk("Fixing up unaligned kernelspace access in interrupt pc=0x%08x ins=0x%08lx\n",
752 (__u32)regs->pc, opcode);
754 printk("Fixing up unaligned kernelspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
755 current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
761 case (0x84>>2): /* LD.W */
762 error = misaligned_load(regs, opcode, 1, 1, 1);
764 case (0xb0>>2): /* LD.UW */
765 error = misaligned_load(regs, opcode, 1, 1, 0);
767 case (0x88>>2): /* LD.L */
768 error = misaligned_load(regs, opcode, 1, 2, 1);
770 case (0x8c>>2): /* LD.Q */
771 error = misaligned_load(regs, opcode, 1, 3, 0);
774 case (0xa4>>2): /* ST.W */
775 error = misaligned_store(regs, opcode, 1, 1);
777 case (0xa8>>2): /* ST.L */
778 error = misaligned_store(regs, opcode, 1, 2);
780 case (0xac>>2): /* ST.Q */
781 error = misaligned_store(regs, opcode, 1, 3);
784 case (0x40>>2): /* indexed loads */
786 case 0x1: /* LDX.W */
787 error = misaligned_load(regs, opcode, 0, 1, 1);
789 case 0x5: /* LDX.UW */
790 error = misaligned_load(regs, opcode, 0, 1, 0);
792 case 0x2: /* LDX.L */
793 error = misaligned_load(regs, opcode, 0, 2, 1);
795 case 0x3: /* LDX.Q */
796 error = misaligned_load(regs, opcode, 0, 3, 0);
804 case (0x60>>2): /* indexed stores */
806 case 0x1: /* STX.W */
807 error = misaligned_store(regs, opcode, 0, 1);
809 case 0x2: /* STX.L */
810 error = misaligned_store(regs, opcode, 0, 2);
812 case 0x3: /* STX.Q */
813 error = misaligned_store(regs, opcode, 0, 3);
821 case (0x94>>2): /* FLD.S */
822 error = misaligned_fpu_load(regs, opcode, 1, 2, 0);
824 case (0x98>>2): /* FLD.P */
825 error = misaligned_fpu_load(regs, opcode, 1, 3, 1);
827 case (0x9c>>2): /* FLD.D */
828 error = misaligned_fpu_load(regs, opcode, 1, 3, 0);
830 case (0x1c>>2): /* floating indexed loads */
832 case 0x8: /* FLDX.S */
833 error = misaligned_fpu_load(regs, opcode, 0, 2, 0);
835 case 0xd: /* FLDX.P */
836 error = misaligned_fpu_load(regs, opcode, 0, 3, 1);
838 case 0x9: /* FLDX.D */
839 error = misaligned_fpu_load(regs, opcode, 0, 3, 0);
846 case (0xb4>>2): /* FLD.S */
847 error = misaligned_fpu_store(regs, opcode, 1, 2, 0);
849 case (0xb8>>2): /* FLD.P */
850 error = misaligned_fpu_store(regs, opcode, 1, 3, 1);
852 case (0xbc>>2): /* FLD.D */
853 error = misaligned_fpu_store(regs, opcode, 1, 3, 0);
855 case (0x3c>>2): /* floating indexed stores */
857 case 0x8: /* FSTX.S */
858 error = misaligned_fpu_store(regs, opcode, 0, 2, 0);
860 case 0xd: /* FSTX.P */
861 error = misaligned_fpu_store(regs, opcode, 0, 3, 1);
863 case 0x9: /* FSTX.D */
864 error = misaligned_fpu_store(regs, opcode, 0, 3, 0);
881 regs->pc += 4; /* Skip the instruction that's just been emulated */
887 static ctl_table unaligned_table[] = {
889 .procname = "kernel_reports",
890 .data = &kernel_mode_unaligned_fixup_count,
891 .maxlen = sizeof(int),
893 .proc_handler = proc_dointvec
896 .procname = "user_reports",
897 .data = &user_mode_unaligned_fixup_count,
898 .maxlen = sizeof(int),
900 .proc_handler = proc_dointvec
903 .procname = "user_enable",
904 .data = &user_mode_unaligned_fixup_enable,
905 .maxlen = sizeof(int),
907 .proc_handler = proc_dointvec},
911 static ctl_table unaligned_root[] = {
913 .procname = "unaligned_fixup",
915 .child = unaligned_table
920 static ctl_table sh64_root[] = {
924 .child = unaligned_root
928 static struct ctl_table_header *sysctl_header;
929 static int __init init_sysctl(void)
931 sysctl_header = register_sysctl_table(sh64_root);
935 __initcall(init_sysctl);
938 asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs)
940 u64 peek_real_address_q(u64 addr);
941 u64 poke_real_address_q(u64 addr, u64 val);
942 unsigned long long DM_EXP_CAUSE_PHY = 0x0c100010;
943 unsigned long long exp_cause;
944 /* It's not worth ioremapping the debug module registers for the amount
945 of access we make to them - just go direct to their physical
947 exp_cause = peek_real_address_q(DM_EXP_CAUSE_PHY);
948 if (exp_cause & ~4) {
949 printk("DM.EXP_CAUSE had unexpected bits set (=%08lx)\n",
950 (unsigned long)(exp_cause & 0xffffffff));
953 /* Clear all DEBUGINT causes */
954 poke_real_address_q(DM_EXP_CAUSE_PHY, 0x0);
957 void __cpuinit per_cpu_trap_init(void)
959 /* Nothing to do for now, VBR initialization later. */