5 select SH_WRITETHROUGH if !CPU_SH2A
21 select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
32 config CPU_SUBTYPE_ST40
35 select CPU_HAS_INTC2_IRQ
44 prompt "Processor sub-type selection"
50 # SH-2 Processor Support
52 config CPU_SUBTYPE_SH7619
53 bool "Support SH7619 processor"
55 select CPU_HAS_IPR_IRQ
57 # SH-2A Processor Support
59 config CPU_SUBTYPE_SH7206
60 bool "Support SH7206 processor"
62 select CPU_HAS_IPR_IRQ
64 # SH-3 Processor Support
66 config CPU_SUBTYPE_SH7705
67 bool "Support SH7705 processor"
69 select CPU_HAS_INTC_IRQ
71 config CPU_SUBTYPE_SH7706
72 bool "Support SH7706 processor"
74 select CPU_HAS_INTC_IRQ
76 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
78 config CPU_SUBTYPE_SH7707
79 bool "Support SH7707 processor"
81 select CPU_HAS_INTC_IRQ
83 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
85 config CPU_SUBTYPE_SH7708
86 bool "Support SH7708 processor"
88 select CPU_HAS_INTC_IRQ
90 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
91 if you have a 100 Mhz SH-3 HD6417708R CPU.
93 config CPU_SUBTYPE_SH7709
94 bool "Support SH7709 processor"
96 select CPU_HAS_INTC_IRQ
98 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
100 config CPU_SUBTYPE_SH7710
101 bool "Support SH7710 processor"
103 select CPU_HAS_INTC_IRQ
106 Select SH7710 if you have a SH3-DSP SH7710 CPU.
108 config CPU_SUBTYPE_SH7712
109 bool "Support SH7712 processor"
111 select CPU_HAS_INTC_IRQ
114 Select SH7712 if you have a SH3-DSP SH7712 CPU.
116 # SH-4 Processor Support
118 config CPU_SUBTYPE_SH7750
119 bool "Support SH7750 processor"
121 select CPU_HAS_INTC_IRQ
123 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
125 config CPU_SUBTYPE_SH7091
126 bool "Support SH7091 processor"
128 select CPU_HAS_INTC_IRQ
130 Select SH7091 if you have an SH-4 based Sega device (such as
131 the Dreamcast, Naomi, and Naomi 2).
133 config CPU_SUBTYPE_SH7750R
134 bool "Support SH7750R processor"
136 select CPU_HAS_INTC_IRQ
138 config CPU_SUBTYPE_SH7750S
139 bool "Support SH7750S processor"
141 select CPU_HAS_INTC_IRQ
143 config CPU_SUBTYPE_SH7751
144 bool "Support SH7751 processor"
146 select CPU_HAS_INTC_IRQ
148 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
149 or if you have a HD6417751R CPU.
151 config CPU_SUBTYPE_SH7751R
152 bool "Support SH7751R processor"
154 select CPU_HAS_INTC_IRQ
156 config CPU_SUBTYPE_SH7760
157 bool "Support SH7760 processor"
159 select CPU_HAS_INTC2_IRQ
160 select CPU_HAS_IPR_IRQ
162 config CPU_SUBTYPE_SH4_202
163 bool "Support SH4-202 processor"
166 # ST40 Processor Support
168 config CPU_SUBTYPE_ST40STB1
169 bool "Support ST40STB1/ST40RA processors"
170 select CPU_SUBTYPE_ST40
172 Select ST40STB1 if you have a ST40RA CPU.
173 This was previously called the ST40STB1, hence the option name.
175 config CPU_SUBTYPE_ST40GX1
176 bool "Support ST40GX1 processor"
177 select CPU_SUBTYPE_ST40
179 Select ST40GX1 if you have a ST40GX1 CPU.
181 # SH-4A Processor Support
183 config CPU_SUBTYPE_SH7770
184 bool "Support SH7770 processor"
187 config CPU_SUBTYPE_SH7780
188 bool "Support SH7780 processor"
190 select CPU_HAS_INTC_IRQ
192 config CPU_SUBTYPE_SH7785
193 bool "Support SH7785 processor"
196 select CPU_HAS_INTC2_IRQ
198 config CPU_SUBTYPE_SHX3
199 bool "Support SH-X3 processor"
202 select CPU_HAS_INTC2_IRQ
204 # SH4AL-DSP Processor Support
206 config CPU_SUBTYPE_SH7343
207 bool "Support SH7343 processor"
210 config CPU_SUBTYPE_SH7722
211 bool "Support SH7722 processor"
214 select CPU_HAS_INTC_IRQ
215 select ARCH_SPARSEMEM_ENABLE
216 select SYS_SUPPORTS_NUMA
220 menu "Memory management options"
226 bool "Support for memory management hardware"
230 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
231 boot on these systems, this option must not be set.
233 On other systems (such as the SH-3 and 4) where an MMU exists,
234 turning this off will boot the kernel on these machines with the
235 MMU implicitly switched off.
239 default "0x80000000" if MMU
243 hex "Physical memory start address"
246 Computers built with Hitachi SuperH processors always
247 map the ROM starting at address zero. But the processor
248 does not specify the range that RAM takes.
250 The physical memory (RAM) start address will be automatically
251 set to 08000000. Other platforms, such as the Solution Engine
252 boards typically map RAM at 0C000000.
254 Tweak this only when porting to a new machine which does not
255 already have a defconfig. Changing it from the known correct
256 value on any of the known systems will only lead to disaster.
259 hex "Physical memory size"
262 This sets the default memory size assumed by your SH kernel. It can
263 be overridden as normal by the 'mem=' argument on the kernel command
264 line. If unsure, consult your board specifications or just leave it
265 as 0x00400000 which was the default value before this became
269 bool "Support 32-bit physical addressing through PMB"
270 depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
273 If you say Y here, physical addressing will be extended to
274 32-bits through the SH-4A PMB. If this is not set, legacy
275 29-bit physical addressing will be used.
278 bool "Enable extended TLB mode"
279 depends on CPU_SHX2 && MMU && EXPERIMENTAL
281 Selecting this option will enable the extended mode of the SH-X2
282 TLB. For legacy SH-X behaviour and interoperability, say N. For
283 all of the fun new features and a willingless to submit bug reports,
287 bool "Support vsyscall page"
291 This will enable support for the kernel mapping a vDSO page
292 in process space, and subsequently handing down the entry point
293 to the libc through the ELF auxiliary vector.
295 From the kernel side this is used for the signal trampoline.
296 For systems with an MMU that can afford to give up a page,
297 (the default value) say Y.
300 bool "Non Uniform Memory Access (NUMA) Support"
301 depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
304 Some SH systems have many various memories scattered around
305 the address space, each with varying latencies. This enables
306 support for these blocks by binding them to nodes and allowing
307 memory policies to be used for prioritizing and controlling
308 allocation behaviour.
313 depends on NEED_MULTIPLE_NODES
315 config ARCH_FLATMEM_ENABLE
319 config ARCH_SPARSEMEM_ENABLE
321 select SPARSEMEM_STATIC
323 config ARCH_SPARSEMEM_DEFAULT
326 config MAX_ACTIVE_REGIONS
328 default "2" if (CPU_SUBTYPE_SH7722 && SPARSEMEM)
331 config ARCH_POPULATES_NODE_MAP
334 config ARCH_SELECT_MEMORY_MODEL
337 config ARCH_ENABLE_MEMORY_HOTPLUG
341 config ARCH_MEMORY_PROBE
343 depends on MEMORY_HOTPLUG
346 prompt "Kernel page size"
347 default PAGE_SIZE_4KB
352 This is the default page size used by all SuperH CPUs.
356 depends on EXPERIMENTAL && X2TLB
358 This enables 8kB pages as supported by SH-X2 and later MMUs.
360 config PAGE_SIZE_64KB
362 depends on EXPERIMENTAL && CPU_SH4
364 This enables support for 64kB pages, possible on all SH-4
365 CPUs and later. Highly experimental, not recommended.
370 prompt "HugeTLB page size"
371 depends on HUGETLB_PAGE && CPU_SH4 && MMU
372 default HUGETLB_PAGE_SIZE_64K
374 config HUGETLB_PAGE_SIZE_64K
377 config HUGETLB_PAGE_SIZE_256K
381 config HUGETLB_PAGE_SIZE_1MB
384 config HUGETLB_PAGE_SIZE_4MB
388 config HUGETLB_PAGE_SIZE_64MB
398 menu "Cache configuration"
400 config SH7705_CACHE_32KB
401 bool "Enable 32KB cache size for SH7705"
402 depends on CPU_SUBTYPE_SH7705
405 config SH_DIRECT_MAPPED
406 bool "Use direct-mapped caching"
409 Selecting this option will configure the caches to be direct-mapped,
410 even if the cache supports a 2 or 4-way mode. This is useful primarily
411 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
412 SH4-202, SH4-501, etc.)
414 Turn this option off for platforms that do not have a direct-mapped
415 cache, and you have no need to run the caches in such a configuration.
417 config SH_WRITETHROUGH
418 bool "Use write-through caching"
420 Selecting this option will configure the caches in write-through
421 mode, as opposed to the default write-back configuration.
423 Since there's sill some aliasing issues on SH-4, this option will
424 unfortunately still require the majority of flushing functions to
425 be implemented to deal with aliasing.