5 select SH_WRITETHROUGH if !CPU_SH2A
21 select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
31 config CPU_SUBTYPE_ST40
34 select CPU_HAS_INTC2_IRQ
40 prompt "Processor sub-type selection"
46 # SH-2 Processor Support
48 config CPU_SUBTYPE_SH7604
49 bool "Support SH7604 processor"
52 config CPU_SUBTYPE_SH7619
53 bool "Support SH7619 processor"
56 # SH-2A Processor Support
58 config CPU_SUBTYPE_SH7206
59 bool "Support SH7206 processor"
62 # SH-3 Processor Support
64 config CPU_SUBTYPE_SH7300
65 bool "Support SH7300 processor"
68 config CPU_SUBTYPE_SH7705
69 bool "Support SH7705 processor"
71 select CPU_HAS_IPR_IRQ
72 select CPU_HAS_PINT_IRQ
74 config CPU_SUBTYPE_SH7706
75 bool "Support SH7706 processor"
77 select CPU_HAS_IPR_IRQ
79 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
81 config CPU_SUBTYPE_SH7707
82 bool "Support SH7707 processor"
84 select CPU_HAS_PINT_IRQ
86 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
88 config CPU_SUBTYPE_SH7708
89 bool "Support SH7708 processor"
92 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
93 if you have a 100 Mhz SH-3 HD6417708R CPU.
95 config CPU_SUBTYPE_SH7709
96 bool "Support SH7709 processor"
98 select CPU_HAS_IPR_IRQ
99 select CPU_HAS_PINT_IRQ
101 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
103 config CPU_SUBTYPE_SH7710
104 bool "Support SH7710 processor"
106 select CPU_HAS_IPR_IRQ
108 Select SH7710 if you have a SH3-DSP SH7710 CPU.
110 config CPU_SUBTYPE_SH7712
111 bool "Support SH7712 processor"
113 select CPU_HAS_IPR_IRQ
115 Select SH7712 if you have a SH3-DSP SH7712 CPU.
117 # SH-4 Processor Support
119 config CPU_SUBTYPE_SH7750
120 bool "Support SH7750 processor"
122 select CPU_HAS_IPR_IRQ
124 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
126 config CPU_SUBTYPE_SH7091
127 bool "Support SH7091 processor"
129 select CPU_SUBTYPE_SH7750
131 Select SH7091 if you have an SH-4 based Sega device (such as
132 the Dreamcast, Naomi, and Naomi 2).
134 config CPU_SUBTYPE_SH7750R
135 bool "Support SH7750R processor"
137 select CPU_SUBTYPE_SH7750
138 select CPU_HAS_IPR_IRQ
140 config CPU_SUBTYPE_SH7750S
141 bool "Support SH7750S processor"
143 select CPU_SUBTYPE_SH7750
144 select CPU_HAS_IPR_IRQ
146 config CPU_SUBTYPE_SH7751
147 bool "Support SH7751 processor"
149 select CPU_HAS_IPR_IRQ
151 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
152 or if you have a HD6417751R CPU.
154 config CPU_SUBTYPE_SH7751R
155 bool "Support SH7751R processor"
157 select CPU_SUBTYPE_SH7751
158 select CPU_HAS_IPR_IRQ
160 config CPU_SUBTYPE_SH7760
161 bool "Support SH7760 processor"
163 select CPU_HAS_INTC2_IRQ
164 select CPU_HAS_IPR_IRQ
166 config CPU_SUBTYPE_SH4_202
167 bool "Support SH4-202 processor"
170 # ST40 Processor Support
172 config CPU_SUBTYPE_ST40STB1
173 bool "Support ST40STB1/ST40RA processors"
174 select CPU_SUBTYPE_ST40
176 Select ST40STB1 if you have a ST40RA CPU.
177 This was previously called the ST40STB1, hence the option name.
179 config CPU_SUBTYPE_ST40GX1
180 bool "Support ST40GX1 processor"
181 select CPU_SUBTYPE_ST40
183 Select ST40GX1 if you have a ST40GX1 CPU.
185 # SH-4A Processor Support
187 config CPU_SUBTYPE_SH7770
188 bool "Support SH7770 processor"
191 config CPU_SUBTYPE_SH7780
192 bool "Support SH7780 processor"
194 select CPU_HAS_INTC2_IRQ
196 config CPU_SUBTYPE_SH7785
197 bool "Support SH7785 processor"
200 select CPU_HAS_INTC2_IRQ
202 # SH4AL-DSP Processor Support
204 config CPU_SUBTYPE_SH73180
205 bool "Support SH73180 processor"
208 config CPU_SUBTYPE_SH7343
209 bool "Support SH7343 processor"
212 config CPU_SUBTYPE_SH7722
213 bool "Support SH7722 processor"
216 select CPU_HAS_IPR_IRQ
220 menu "Memory management options"
226 bool "Support for memory management hardware"
230 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
231 boot on these systems, this option must not be set.
233 On other systems (such as the SH-3 and 4) where an MMU exists,
234 turning this off will boot the kernel on these machines with the
235 MMU implicitly switched off.
239 default "0x80000000" if MMU
243 hex "Physical memory start address"
246 Computers built with Hitachi SuperH processors always
247 map the ROM starting at address zero. But the processor
248 does not specify the range that RAM takes.
250 The physical memory (RAM) start address will be automatically
251 set to 08000000. Other platforms, such as the Solution Engine
252 boards typically map RAM at 0C000000.
254 Tweak this only when porting to a new machine which does not
255 already have a defconfig. Changing it from the known correct
256 value on any of the known systems will only lead to disaster.
259 hex "Physical memory size"
262 This sets the default memory size assumed by your SH kernel. It can
263 be overridden as normal by the 'mem=' argument on the kernel command
264 line. If unsure, consult your board specifications or just leave it
265 as 0x00400000 which was the default value before this became
269 bool "Support 32-bit physical addressing through PMB"
270 depends on CPU_SH4A && MMU && (!X2TLB || BROKEN)
273 If you say Y here, physical addressing will be extended to
274 32-bits through the SH-4A PMB. If this is not set, legacy
275 29-bit physical addressing will be used.
278 bool "Enable extended TLB mode"
279 depends on CPU_SHX2 && MMU && EXPERIMENTAL
281 Selecting this option will enable the extended mode of the SH-X2
282 TLB. For legacy SH-X behaviour and interoperability, say N. For
283 all of the fun new features and a willingless to submit bug reports,
287 bool "Support vsyscall page"
291 This will enable support for the kernel mapping a vDSO page
292 in process space, and subsequently handing down the entry point
293 to the libc through the ELF auxiliary vector.
295 From the kernel side this is used for the signal trampoline.
296 For systems with an MMU that can afford to give up a page,
297 (the default value) say Y.
302 depends on NEED_MULTIPLE_NODES
304 config ARCH_FLATMEM_ENABLE
307 config MAX_ACTIVE_REGIONS
311 config ARCH_POPULATES_NODE_MAP
315 prompt "Kernel page size"
316 default PAGE_SIZE_4KB
321 This is the default page size used by all SuperH CPUs.
325 depends on EXPERIMENTAL && X2TLB
327 This enables 8kB pages as supported by SH-X2 and later MMUs.
329 config PAGE_SIZE_64KB
331 depends on EXPERIMENTAL && CPU_SH4
333 This enables support for 64kB pages, possible on all SH-4
334 CPUs and later. Highly experimental, not recommended.
339 prompt "HugeTLB page size"
340 depends on HUGETLB_PAGE && CPU_SH4 && MMU
341 default HUGETLB_PAGE_SIZE_64K
343 config HUGETLB_PAGE_SIZE_64K
346 config HUGETLB_PAGE_SIZE_256K
350 config HUGETLB_PAGE_SIZE_1MB
353 config HUGETLB_PAGE_SIZE_4MB
357 config HUGETLB_PAGE_SIZE_64MB
367 menu "Cache configuration"
369 config SH7705_CACHE_32KB
370 bool "Enable 32KB cache size for SH7705"
371 depends on CPU_SUBTYPE_SH7705
374 config SH_DIRECT_MAPPED
375 bool "Use direct-mapped caching"
378 Selecting this option will configure the caches to be direct-mapped,
379 even if the cache supports a 2 or 4-way mode. This is useful primarily
380 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
381 SH4-202, SH4-501, etc.)
383 Turn this option off for platforms that do not have a direct-mapped
384 cache, and you have no need to run the caches in such a configuration.
386 config SH_WRITETHROUGH
387 bool "Use write-through caching"
389 Selecting this option will configure the caches in write-through
390 mode, as opposed to the default write-back configuration.
392 Since there's sill some aliasing issues on SH-4, this option will
393 unfortunately still require the majority of flushing functions to
394 be implemented to deal with aliasing.
399 bool "Operand Cache RAM (OCRAM) support"
401 Selecting this option will automatically tear down the number of
402 sets in the dcache by half, which in turn exposes a memory range.
404 The addresses for the OC RAM base will vary according to the
405 processor version. Consult vendor documentation for specifics.