1 menu "Processor selection"
7 select SH_WRITETHROUGH if !CPU_SH2A
23 select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
33 config CPU_SUBTYPE_ST40
36 select CPU_HAS_INTC2_IRQ
45 comment "SH-2 Processor Support"
47 config CPU_SUBTYPE_SH7604
48 bool "Support SH7604 processor"
51 config CPU_SUBTYPE_SH7619
52 bool "Support SH7619 processor"
55 comment "SH-2A Processor Support"
57 config CPU_SUBTYPE_SH7206
58 bool "Support SH7206 processor"
61 comment "SH-3 Processor Support"
63 config CPU_SUBTYPE_SH7300
64 bool "Support SH7300 processor"
67 config CPU_SUBTYPE_SH7705
68 bool "Support SH7705 processor"
70 select CPU_HAS_PINT_IRQ
72 config CPU_SUBTYPE_SH7706
73 bool "Support SH7706 processor"
75 select CPU_HAS_IPR_IRQ
77 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
79 config CPU_SUBTYPE_SH7707
80 bool "Support SH7707 processor"
82 select CPU_HAS_PINT_IRQ
84 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
86 config CPU_SUBTYPE_SH7708
87 bool "Support SH7708 processor"
90 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
91 if you have a 100 Mhz SH-3 HD6417708R CPU.
93 config CPU_SUBTYPE_SH7709
94 bool "Support SH7709 processor"
96 select CPU_HAS_IPR_IRQ
97 select CPU_HAS_PINT_IRQ
99 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
101 config CPU_SUBTYPE_SH7710
102 bool "Support SH7710 processor"
105 Select SH7710 if you have a SH3-DSP SH7710 CPU.
107 comment "SH-4 Processor Support"
109 config CPU_SUBTYPE_SH7750
110 bool "Support SH7750 processor"
112 select CPU_HAS_IPR_IRQ
114 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
116 config CPU_SUBTYPE_SH7091
117 bool "Support SH7091 processor"
119 select CPU_SUBTYPE_SH7750
121 Select SH7091 if you have an SH-4 based Sega device (such as
122 the Dreamcast, Naomi, and Naomi 2).
124 config CPU_SUBTYPE_SH7750R
125 bool "Support SH7750R processor"
127 select CPU_SUBTYPE_SH7750
128 select CPU_HAS_IPR_IRQ
130 config CPU_SUBTYPE_SH7750S
131 bool "Support SH7750S processor"
133 select CPU_SUBTYPE_SH7750
134 select CPU_HAS_IPR_IRQ
136 config CPU_SUBTYPE_SH7751
137 bool "Support SH7751 processor"
139 select CPU_HAS_IPR_IRQ
141 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
142 or if you have a HD6417751R CPU.
144 config CPU_SUBTYPE_SH7751R
145 bool "Support SH7751R processor"
147 select CPU_SUBTYPE_SH7751
148 select CPU_HAS_IPR_IRQ
150 config CPU_SUBTYPE_SH7760
151 bool "Support SH7760 processor"
153 select CPU_HAS_INTC2_IRQ
155 config CPU_SUBTYPE_SH4_202
156 bool "Support SH4-202 processor"
159 comment "ST40 Processor Support"
161 config CPU_SUBTYPE_ST40STB1
162 bool "Support ST40STB1/ST40RA processors"
163 select CPU_SUBTYPE_ST40
165 Select ST40STB1 if you have a ST40RA CPU.
166 This was previously called the ST40STB1, hence the option name.
168 config CPU_SUBTYPE_ST40GX1
169 bool "Support ST40GX1 processor"
170 select CPU_SUBTYPE_ST40
172 Select ST40GX1 if you have a ST40GX1 CPU.
174 comment "SH-4A Processor Support"
176 config CPU_SUBTYPE_SH7770
177 bool "Support SH7770 processor"
180 config CPU_SUBTYPE_SH7780
181 bool "Support SH7780 processor"
183 select CPU_HAS_INTC2_IRQ
185 config CPU_SUBTYPE_SH7785
186 bool "Support SH7785 processor"
189 select CPU_HAS_INTC2_IRQ
191 comment "SH4AL-DSP Processor Support"
193 config CPU_SUBTYPE_SH73180
194 bool "Support SH73180 processor"
197 config CPU_SUBTYPE_SH7343
198 bool "Support SH7343 processor"
201 config CPU_SUBTYPE_SH7722
202 bool "Support SH7722 processor"
205 select CPU_HAS_IPR_IRQ
209 menu "Memory management options"
212 bool "Support for memory management hardware"
216 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
217 boot on these systems, this option must not be set.
219 On other systems (such as the SH-3 and 4) where an MMU exists,
220 turning this off will boot the kernel on these machines with the
221 MMU implicitly switched off.
225 default "0x80000000" if MMU
229 hex "Physical memory start address"
232 Computers built with Hitachi SuperH processors always
233 map the ROM starting at address zero. But the processor
234 does not specify the range that RAM takes.
236 The physical memory (RAM) start address will be automatically
237 set to 08000000. Other platforms, such as the Solution Engine
238 boards typically map RAM at 0C000000.
240 Tweak this only when porting to a new machine which does not
241 already have a defconfig. Changing it from the known correct
242 value on any of the known systems will only lead to disaster.
245 hex "Physical memory size"
248 This sets the default memory size assumed by your SH kernel. It can
249 be overridden as normal by the 'mem=' argument on the kernel command
250 line. If unsure, consult your board specifications or just leave it
251 as 0x00400000 which was the default value before this became
255 bool "Support 32-bit physical addressing through PMB"
256 depends on CPU_SH4A && MMU && (!X2TLB || BROKEN)
259 If you say Y here, physical addressing will be extended to
260 32-bits through the SH-4A PMB. If this is not set, legacy
261 29-bit physical addressing will be used.
264 bool "Enable extended TLB mode"
265 depends on CPU_SHX2 && MMU && EXPERIMENTAL
267 Selecting this option will enable the extended mode of the SH-X2
268 TLB. For legacy SH-X behaviour and interoperability, say N. For
269 all of the fun new features and a willingless to submit bug reports,
273 bool "Support vsyscall page"
277 This will enable support for the kernel mapping a vDSO page
278 in process space, and subsequently handing down the entry point
279 to the libc through the ELF auxiliary vector.
281 From the kernel side this is used for the signal trampoline.
282 For systems with an MMU that can afford to give up a page,
283 (the default value) say Y.
286 prompt "Kernel page size"
287 default PAGE_SIZE_4KB
292 This is the default page size used by all SuperH CPUs.
296 depends on EXPERIMENTAL && X2TLB
298 This enables 8kB pages as supported by SH-X2 and later MMUs.
300 config PAGE_SIZE_64KB
302 depends on EXPERIMENTAL && CPU_SH4
304 This enables support for 64kB pages, possible on all SH-4
305 CPUs and later. Highly experimental, not recommended.
310 prompt "HugeTLB page size"
311 depends on HUGETLB_PAGE && CPU_SH4 && MMU
312 default HUGETLB_PAGE_SIZE_64K
314 config HUGETLB_PAGE_SIZE_64K
317 config HUGETLB_PAGE_SIZE_256K
321 config HUGETLB_PAGE_SIZE_1MB
324 config HUGETLB_PAGE_SIZE_4MB
328 config HUGETLB_PAGE_SIZE_64MB
338 menu "Cache configuration"
340 config SH7705_CACHE_32KB
341 bool "Enable 32KB cache size for SH7705"
342 depends on CPU_SUBTYPE_SH7705
345 config SH_DIRECT_MAPPED
346 bool "Use direct-mapped caching"
349 Selecting this option will configure the caches to be direct-mapped,
350 even if the cache supports a 2 or 4-way mode. This is useful primarily
351 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
352 SH4-202, SH4-501, etc.)
354 Turn this option off for platforms that do not have a direct-mapped
355 cache, and you have no need to run the caches in such a configuration.
357 config SH_WRITETHROUGH
358 bool "Use write-through caching"
360 Selecting this option will configure the caches in write-through
361 mode, as opposed to the default write-back configuration.
363 Since there's sill some aliasing issues on SH-4, this option will
364 unfortunately still require the majority of flushing functions to
365 be implemented to deal with aliasing.
370 bool "Operand Cache RAM (OCRAM) support"
372 Selecting this option will automatically tear down the number of
373 sets in the dcache by half, which in turn exposes a memory range.
375 The addresses for the OC RAM base will vary according to the
376 processor version. Consult vendor documentation for specifics.