1 menu "Memory management options"
7 bool "Support for memory management hardware"
11 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12 boot on these systems, this option must not be set.
14 On other systems (such as the SH-3 and 4) where an MMU exists,
15 turning this off will boot the kernel on these machines with the
16 MMU implicitly switched off.
20 default "0x80000000" if MMU
24 hex "Physical memory start address"
27 Computers built with Hitachi SuperH processors always
28 map the ROM starting at address zero. But the processor
29 does not specify the range that RAM takes.
31 The physical memory (RAM) start address will be automatically
32 set to 08000000. Other platforms, such as the Solution Engine
33 boards typically map RAM at 0C000000.
35 Tweak this only when porting to a new machine which does not
36 already have a defconfig. Changing it from the known correct
37 value on any of the known systems will only lead to disaster.
40 hex "Physical memory size"
43 This sets the default memory size assumed by your SH kernel. It can
44 be overridden as normal by the 'mem=' argument on the kernel command
45 line. If unsure, consult your board specifications or just leave it
46 as 0x00400000 which was the default value before this became
50 bool "Support 32-bit physical addressing through PMB"
51 depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
54 If you say Y here, physical addressing will be extended to
55 32-bits through the SH-4A PMB. If this is not set, legacy
56 29-bit physical addressing will be used.
59 bool "Enable extended TLB mode"
60 depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL
62 Selecting this option will enable the extended mode of the SH-X2
63 TLB. For legacy SH-X behaviour and interoperability, say N. For
64 all of the fun new features and a willingless to submit bug reports,
68 bool "Support vsyscall page"
69 depends on MMU && (CPU_SH3 || CPU_SH4)
72 This will enable support for the kernel mapping a vDSO page
73 in process space, and subsequently handing down the entry point
74 to the libc through the ELF auxiliary vector.
76 From the kernel side this is used for the signal trampoline.
77 For systems with an MMU that can afford to give up a page,
78 (the default value) say Y.
81 bool "Non Uniform Memory Access (NUMA) Support"
82 depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
85 Some SH systems have many various memories scattered around
86 the address space, each with varying latencies. This enables
87 support for these blocks by binding them to nodes and allowing
88 memory policies to be used for prioritizing and controlling
93 default "3" if CPU_SUBTYPE_SHX3
95 depends on NEED_MULTIPLE_NODES
97 config ARCH_FLATMEM_ENABLE
101 config ARCH_SPARSEMEM_ENABLE
103 select SPARSEMEM_STATIC
105 config ARCH_SPARSEMEM_DEFAULT
108 config MAX_ACTIVE_REGIONS
110 default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
111 default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \
115 config ARCH_POPULATES_NODE_MAP
118 config ARCH_SELECT_MEMORY_MODEL
121 config ARCH_ENABLE_MEMORY_HOTPLUG
125 config ARCH_MEMORY_PROBE
127 depends on MEMORY_HOTPLUG
130 prompt "Kernel page size"
131 default PAGE_SIZE_8KB if X2TLB
132 default PAGE_SIZE_4KB
138 This is the default page size used by all SuperH CPUs.
144 This enables 8kB pages as supported by SH-X2 and later MMUs.
146 config PAGE_SIZE_64KB
150 This enables support for 64kB pages, possible on all SH-4
156 prompt "HugeTLB page size"
157 depends on HUGETLB_PAGE && CPU_SH4 && MMU
158 default HUGETLB_PAGE_SIZE_64K
160 config HUGETLB_PAGE_SIZE_64K
163 config HUGETLB_PAGE_SIZE_256K
167 config HUGETLB_PAGE_SIZE_1MB
170 config HUGETLB_PAGE_SIZE_4MB
174 config HUGETLB_PAGE_SIZE_64MB
178 config HUGETLB_PAGE_SIZE_512MB
188 menu "Cache configuration"
190 config SH7705_CACHE_32KB
191 bool "Enable 32KB cache size for SH7705"
192 depends on CPU_SUBTYPE_SH7705
195 config SH_DIRECT_MAPPED
196 bool "Use direct-mapped caching"
199 Selecting this option will configure the caches to be direct-mapped,
200 even if the cache supports a 2 or 4-way mode. This is useful primarily
201 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
202 SH4-202, SH4-501, etc.)
204 Turn this option off for platforms that do not have a direct-mapped
205 cache, and you have no need to run the caches in such a configuration.
209 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
210 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
212 config CACHE_WRITEBACK
214 depends on CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
216 config CACHE_WRITETHROUGH
219 Selecting this option will configure the caches in write-through
220 mode, as opposed to the default write-back configuration.
222 Since there's sill some aliasing issues on SH-4, this option will
223 unfortunately still require the majority of flushing functions to
224 be implemented to deal with aliasing.