5 select SH_WRITETHROUGH if !CPU_SH2A
21 select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
32 config CPU_SUBTYPE_ST40
35 select CPU_HAS_INTC2_IRQ
44 prompt "Processor sub-type selection"
50 # SH-2 Processor Support
52 config CPU_SUBTYPE_SH7619
53 bool "Support SH7619 processor"
55 select CPU_HAS_IPR_IRQ
57 # SH-2A Processor Support
59 config CPU_SUBTYPE_SH7206
60 bool "Support SH7206 processor"
62 select CPU_HAS_IPR_IRQ
64 # SH-3 Processor Support
66 config CPU_SUBTYPE_SH7300
67 bool "Support SH7300 processor"
70 config CPU_SUBTYPE_SH7705
71 bool "Support SH7705 processor"
73 select CPU_HAS_IPR_IRQ
75 config CPU_SUBTYPE_SH7706
76 bool "Support SH7706 processor"
78 select CPU_HAS_IPR_IRQ
80 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
82 config CPU_SUBTYPE_SH7707
83 bool "Support SH7707 processor"
86 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
88 config CPU_SUBTYPE_SH7708
89 bool "Support SH7708 processor"
92 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
93 if you have a 100 Mhz SH-3 HD6417708R CPU.
95 config CPU_SUBTYPE_SH7709
96 bool "Support SH7709 processor"
98 select CPU_HAS_IPR_IRQ
100 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
102 config CPU_SUBTYPE_SH7710
103 bool "Support SH7710 processor"
105 select CPU_HAS_IPR_IRQ
108 Select SH7710 if you have a SH3-DSP SH7710 CPU.
110 config CPU_SUBTYPE_SH7712
111 bool "Support SH7712 processor"
113 select CPU_HAS_IPR_IRQ
116 Select SH7712 if you have a SH3-DSP SH7712 CPU.
118 # SH-4 Processor Support
120 config CPU_SUBTYPE_SH7750
121 bool "Support SH7750 processor"
123 select CPU_HAS_INTC_IRQ
125 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
127 config CPU_SUBTYPE_SH7091
128 bool "Support SH7091 processor"
130 select CPU_HAS_INTC_IRQ
132 Select SH7091 if you have an SH-4 based Sega device (such as
133 the Dreamcast, Naomi, and Naomi 2).
135 config CPU_SUBTYPE_SH7750R
136 bool "Support SH7750R processor"
138 select CPU_HAS_INTC_IRQ
140 config CPU_SUBTYPE_SH7750S
141 bool "Support SH7750S processor"
143 select CPU_HAS_INTC_IRQ
145 config CPU_SUBTYPE_SH7751
146 bool "Support SH7751 processor"
148 select CPU_HAS_INTC_IRQ
150 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
151 or if you have a HD6417751R CPU.
153 config CPU_SUBTYPE_SH7751R
154 bool "Support SH7751R processor"
156 select CPU_HAS_INTC_IRQ
158 config CPU_SUBTYPE_SH7760
159 bool "Support SH7760 processor"
161 select CPU_HAS_INTC2_IRQ
162 select CPU_HAS_IPR_IRQ
164 config CPU_SUBTYPE_SH4_202
165 bool "Support SH4-202 processor"
168 # ST40 Processor Support
170 config CPU_SUBTYPE_ST40STB1
171 bool "Support ST40STB1/ST40RA processors"
172 select CPU_SUBTYPE_ST40
174 Select ST40STB1 if you have a ST40RA CPU.
175 This was previously called the ST40STB1, hence the option name.
177 config CPU_SUBTYPE_ST40GX1
178 bool "Support ST40GX1 processor"
179 select CPU_SUBTYPE_ST40
181 Select ST40GX1 if you have a ST40GX1 CPU.
183 # SH-4A Processor Support
185 config CPU_SUBTYPE_SH7770
186 bool "Support SH7770 processor"
189 config CPU_SUBTYPE_SH7780
190 bool "Support SH7780 processor"
192 select CPU_HAS_INTC_IRQ
194 config CPU_SUBTYPE_SH7785
195 bool "Support SH7785 processor"
198 select CPU_HAS_INTC2_IRQ
200 config CPU_SUBTYPE_SHX3
201 bool "Support SH-X3 processor"
204 select CPU_HAS_INTC2_IRQ
206 # SH4AL-DSP Processor Support
208 config CPU_SUBTYPE_SH7343
209 bool "Support SH7343 processor"
212 config CPU_SUBTYPE_SH7722
213 bool "Support SH7722 processor"
216 select CPU_HAS_INTC_IRQ
217 select ARCH_SPARSEMEM_ENABLE
218 select SYS_SUPPORTS_NUMA
222 menu "Memory management options"
228 bool "Support for memory management hardware"
232 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
233 boot on these systems, this option must not be set.
235 On other systems (such as the SH-3 and 4) where an MMU exists,
236 turning this off will boot the kernel on these machines with the
237 MMU implicitly switched off.
241 default "0x80000000" if MMU
245 hex "Physical memory start address"
248 Computers built with Hitachi SuperH processors always
249 map the ROM starting at address zero. But the processor
250 does not specify the range that RAM takes.
252 The physical memory (RAM) start address will be automatically
253 set to 08000000. Other platforms, such as the Solution Engine
254 boards typically map RAM at 0C000000.
256 Tweak this only when porting to a new machine which does not
257 already have a defconfig. Changing it from the known correct
258 value on any of the known systems will only lead to disaster.
261 hex "Physical memory size"
264 This sets the default memory size assumed by your SH kernel. It can
265 be overridden as normal by the 'mem=' argument on the kernel command
266 line. If unsure, consult your board specifications or just leave it
267 as 0x00400000 which was the default value before this became
271 bool "Support 32-bit physical addressing through PMB"
272 depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
275 If you say Y here, physical addressing will be extended to
276 32-bits through the SH-4A PMB. If this is not set, legacy
277 29-bit physical addressing will be used.
280 bool "Enable extended TLB mode"
281 depends on CPU_SHX2 && MMU && EXPERIMENTAL
283 Selecting this option will enable the extended mode of the SH-X2
284 TLB. For legacy SH-X behaviour and interoperability, say N. For
285 all of the fun new features and a willingless to submit bug reports,
289 bool "Support vsyscall page"
293 This will enable support for the kernel mapping a vDSO page
294 in process space, and subsequently handing down the entry point
295 to the libc through the ELF auxiliary vector.
297 From the kernel side this is used for the signal trampoline.
298 For systems with an MMU that can afford to give up a page,
299 (the default value) say Y.
302 bool "Non Uniform Memory Access (NUMA) Support"
303 depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
306 Some SH systems have many various memories scattered around
307 the address space, each with varying latencies. This enables
308 support for these blocks by binding them to nodes and allowing
309 memory policies to be used for prioritizing and controlling
310 allocation behaviour.
315 depends on NEED_MULTIPLE_NODES
317 config ARCH_FLATMEM_ENABLE
321 config ARCH_SPARSEMEM_ENABLE
323 select SPARSEMEM_STATIC
325 config ARCH_SPARSEMEM_DEFAULT
328 config MAX_ACTIVE_REGIONS
330 default "2" if (CPU_SUBTYPE_SH7722 && SPARSEMEM)
333 config ARCH_POPULATES_NODE_MAP
336 config ARCH_SELECT_MEMORY_MODEL
339 config ARCH_ENABLE_MEMORY_HOTPLUG
343 config ARCH_MEMORY_PROBE
345 depends on MEMORY_HOTPLUG
348 prompt "Kernel page size"
349 default PAGE_SIZE_4KB
354 This is the default page size used by all SuperH CPUs.
358 depends on EXPERIMENTAL && X2TLB
360 This enables 8kB pages as supported by SH-X2 and later MMUs.
362 config PAGE_SIZE_64KB
364 depends on EXPERIMENTAL && CPU_SH4
366 This enables support for 64kB pages, possible on all SH-4
367 CPUs and later. Highly experimental, not recommended.
372 prompt "HugeTLB page size"
373 depends on HUGETLB_PAGE && CPU_SH4 && MMU
374 default HUGETLB_PAGE_SIZE_64K
376 config HUGETLB_PAGE_SIZE_64K
379 config HUGETLB_PAGE_SIZE_256K
383 config HUGETLB_PAGE_SIZE_1MB
386 config HUGETLB_PAGE_SIZE_4MB
390 config HUGETLB_PAGE_SIZE_64MB
400 menu "Cache configuration"
402 config SH7705_CACHE_32KB
403 bool "Enable 32KB cache size for SH7705"
404 depends on CPU_SUBTYPE_SH7705
407 config SH_DIRECT_MAPPED
408 bool "Use direct-mapped caching"
411 Selecting this option will configure the caches to be direct-mapped,
412 even if the cache supports a 2 or 4-way mode. This is useful primarily
413 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
414 SH4-202, SH4-501, etc.)
416 Turn this option off for platforms that do not have a direct-mapped
417 cache, and you have no need to run the caches in such a configuration.
419 config SH_WRITETHROUGH
420 bool "Use write-through caching"
422 Selecting this option will configure the caches in write-through
423 mode, as opposed to the default write-back configuration.
425 Since there's sill some aliasing issues on SH-4, this option will
426 unfortunately still require the majority of flushing functions to
427 be implemented to deal with aliasing.