2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * arch/sh64/kernel/time.c
8 * Copyright (C) 2000, 2001 Paolo Alberelli
9 * Copyright (C) 2003 - 2007 Paul Mundt
10 * Copyright (C) 2003 Richard Curnow
12 * Original TMU/RTC code taken from sh version.
13 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
14 * Some code taken from i386 version.
15 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
17 #include <linux/errno.h>
18 #include <linux/rwsem.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
21 #include <linux/param.h>
22 #include <linux/string.h>
24 #include <linux/interrupt.h>
25 #include <linux/time.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/profile.h>
29 #include <linux/smp.h>
30 #include <linux/module.h>
31 #include <linux/bcd.h>
32 #include <linux/timex.h>
33 #include <linux/irq.h>
34 #include <linux/platform_device.h>
35 #include <asm/registers.h> /* required by inline __asm__ stmt. */
36 #include <asm/processor.h>
37 #include <asm/uaccess.h>
40 #include <asm/delay.h>
41 #include <asm/hardware.h>
43 #define TMU_TOCR_INIT 0x00
44 #define TMU0_TCR_INIT 0x0020
45 #define TMU_TSTR_INIT 1
46 #define TMU_TSTR_OFF 0
49 #define RTC_BLOCK_OFF 0x01040000
50 #define RTC_BASE PHYS_PERIPHERAL_BLOCK + RTC_BLOCK_OFF
51 #define RTC_RCR1_CIE 0x10 /* Carry Interrupt Enable */
52 #define RTC_RCR1 (rtc_base + 0x38)
54 /* Clock, Power and Reset Controller */
55 #define CPRC_BLOCK_OFF 0x01010000
56 #define CPRC_BASE PHYS_PERIPHERAL_BLOCK + CPRC_BLOCK_OFF
58 #define FRQCR (cprc_base+0x0)
59 #define WTCSR (cprc_base+0x0018)
60 #define STBCR (cprc_base+0x0030)
62 /* Time Management Unit */
63 #define TMU_BLOCK_OFF 0x01020000
64 #define TMU_BASE PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF
65 #define TMU0_BASE tmu_base + 0x8 + (0xc * 0x0)
66 #define TMU1_BASE tmu_base + 0x8 + (0xc * 0x1)
67 #define TMU2_BASE tmu_base + 0x8 + (0xc * 0x2)
69 #define TMU_TOCR tmu_base+0x0 /* Byte access */
70 #define TMU_TSTR tmu_base+0x4 /* Byte access */
72 #define TMU0_TCOR TMU0_BASE+0x0 /* Long access */
73 #define TMU0_TCNT TMU0_BASE+0x4 /* Long access */
74 #define TMU0_TCR TMU0_BASE+0x8 /* Word access */
76 #define TICK_SIZE (tick_nsec / 1000)
78 static unsigned long tmu_base, rtc_base;
79 unsigned long cprc_base;
81 /* Variables to allow interpolation of time of day to resolution better than a
84 /* This is effectively protected by xtime_lock */
85 static unsigned long ctc_last_interrupt;
86 static unsigned long long usecs_per_jiffy = 1000000/HZ; /* Approximation */
88 #define CTC_JIFFY_SCALE_SHIFT 40
90 /* 2**CTC_JIFFY_SCALE_SHIFT / ctc_ticks_per_jiffy */
91 static unsigned long long scaled_recip_ctc_ticks_per_jiffy;
93 /* Estimate number of microseconds that have elapsed since the last timer tick,
94 by scaling the delta that has occurred in the CTC register.
96 WARNING WARNING WARNING : This algorithm relies on the CTC decrementing at
97 the CPU clock rate. If the CPU sleeps, the CTC stops counting. Bear this
98 in mind if enabling SLEEP_WORKS in process.c. In that case, this algorithm
99 probably needs to use TMU.TCNT0 instead. This will work even if the CPU is
100 sleeping, though will be coarser.
102 FIXME : What if usecs_per_tick is moving around too much, e.g. if an adjtime
103 is running or if the freq or tick arguments of adjtimex are modified after
104 we have calibrated the scaling factor? This will result in either a jump at
105 the end of a tick period, or a wrap backwards at the start of the next one,
106 if the application is reading the time of day often enough. I think we
107 ought to do better than this. For this reason, usecs_per_jiffy is left
108 separated out in the calculation below. This allows some future hook into
109 the adjtime-related stuff in kernel/timer.c to remove this hazard.
113 static unsigned long usecs_since_tick(void)
115 unsigned long long current_ctc;
116 long ctc_ticks_since_interrupt;
117 unsigned long long ull_ctc_ticks_since_interrupt;
118 unsigned long result;
120 unsigned long long mul1_out;
121 unsigned long long mul1_out_high;
122 unsigned long long mul2_out_low, mul2_out_high;
124 /* Read CTC register */
125 asm ("getcon cr62, %0" : "=r" (current_ctc));
126 /* Note, the CTC counts down on each CPU clock, not up.
127 Note(2), use long type to get correct wraparound arithmetic when
128 the counter crosses zero. */
129 ctc_ticks_since_interrupt = (long) ctc_last_interrupt - (long) current_ctc;
130 ull_ctc_ticks_since_interrupt = (unsigned long long) ctc_ticks_since_interrupt;
132 /* Inline assembly to do 32x32x32->64 multiplier */
133 asm volatile ("mulu.l %1, %2, %0" :
135 "r" (ull_ctc_ticks_since_interrupt), "r" (usecs_per_jiffy));
137 mul1_out_high = mul1_out >> 32;
139 asm volatile ("mulu.l %1, %2, %0" :
140 "=r" (mul2_out_low) :
141 "r" (mul1_out), "r" (scaled_recip_ctc_ticks_per_jiffy));
144 asm volatile ("mulu.l %1, %2, %0" :
145 "=r" (mul2_out_high) :
146 "r" (mul1_out_high), "r" (scaled_recip_ctc_ticks_per_jiffy));
149 result = (unsigned long) (((mul2_out_high << 32) + mul2_out_low) >> CTC_JIFFY_SCALE_SHIFT);
154 void do_gettimeofday(struct timeval *tv)
158 unsigned long usec, sec;
161 seq = read_seqbegin_irqsave(&xtime_lock, flags);
162 usec = usecs_since_tick();
164 usec += xtime.tv_nsec / 1000;
165 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
167 while (usec >= 1000000) {
176 int do_settimeofday(struct timespec *tv)
178 time_t wtm_sec, sec = tv->tv_sec;
179 long wtm_nsec, nsec = tv->tv_nsec;
181 if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
184 write_seqlock_irq(&xtime_lock);
186 * This is revolting. We need to set "xtime" correctly. However, the
187 * value in this location is the value at the most recent update of
188 * wall time. Discover what correction gettimeofday() would have
189 * made, and then undo it!
191 nsec -= 1000 * usecs_since_tick();
193 wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
194 wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
196 set_normalized_timespec(&xtime, sec, nsec);
197 set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
200 write_sequnlock_irq(&xtime_lock);
205 EXPORT_SYMBOL(do_settimeofday);
208 static void null_rtc_get_time(struct timespec *tv)
210 tv->tv_sec = mktime(2000, 1, 1, 0, 0, 0);
214 static int null_rtc_set_time(const time_t secs)
219 void (*rtc_sh_get_time)(struct timespec *) = null_rtc_get_time;
220 int (*rtc_sh_set_time)(const time_t) = null_rtc_set_time;
222 /* last time the RTC clock got updated */
223 static long last_rtc_update;
226 * timer_interrupt() needs to keep up the real-time clock,
227 * as well as call the "do_timer()" routine every clocktick
229 static inline void do_timer_interrupt(void)
231 unsigned long long current_ctc;
232 asm ("getcon cr62, %0" : "=r" (current_ctc));
233 ctc_last_interrupt = (unsigned long) current_ctc;
237 update_process_times(user_mode(get_irq_regs()));
240 profile_tick(CPU_PROFILING);
242 #ifdef CONFIG_HEARTBEAT
244 extern void heartbeat(void);
251 * If we have an externally synchronized Linux clock, then update
252 * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
253 * called as close as possible to 500 ms before the new second starts.
256 xtime.tv_sec > last_rtc_update + 660 &&
257 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
258 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
259 if (rtc_sh_set_time(xtime.tv_sec) == 0)
260 last_rtc_update = xtime.tv_sec;
262 /* do it again in 60 s */
263 last_rtc_update = xtime.tv_sec - 600;
268 * This is the same as the above, except we _also_ save the current
269 * Time Stamp Counter value at the time of the timer interrupt, so that
270 * we later on can estimate the time of day more exactly.
272 static irqreturn_t timer_interrupt(int irq, void *dev_id)
274 unsigned long timer_status;
277 timer_status = ctrl_inw(TMU0_TCR);
278 timer_status &= ~0x100;
279 ctrl_outw(timer_status, TMU0_TCR);
282 * Here we are in the timer irq handler. We just have irqs locally
283 * disabled but we don't know if the timer_bh is running on the other
284 * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
285 * the irq version of write_lock because as just said we have irq
286 * locally disabled. -arca
288 write_lock(&xtime_lock);
289 do_timer_interrupt();
290 write_unlock(&xtime_lock);
296 static __init unsigned int get_cpu_hz(void)
299 unsigned long __dummy;
300 unsigned long ctc_val_init, ctc_val;
303 ** Regardless the toolchain, force the compiler to use the
304 ** arbitrary register r3 as a clock tick counter.
305 ** NOTE: r3 must be in accordance with sh64_rtc_interrupt()
307 register unsigned long long __rtc_irq_flag __asm__ ("r3");
310 do {} while (ctrl_inb(rtc_base) != 0);
311 ctrl_outb(RTC_RCR1_CIE, RTC_RCR1); /* Enable carry interrupt */
314 * r3 is arbitrary. CDC does not support "=z".
316 ctc_val_init = 0xffffffff;
317 ctc_val = ctc_val_init;
319 asm volatile("gettr tr0, %1\n\t"
320 "putcon %0, " __CTC "\n\t"
321 "and %2, r63, %2\n\t"
323 "beq/l %2, r63, tr0\n\t"
325 "getcon " __CTC ", %0\n\t"
326 : "=r"(ctc_val), "=r" (__dummy), "=r" (__rtc_irq_flag)
331 * CPU clock = 4 stages * loop
335 * (if) pipe line stole
341 * CPU clock = 6 stages * loop
346 * Use CTC register to count. This approach returns the right value
347 * even if the I-cache is disabled (e.g. whilst debugging.)
351 count = ctc_val_init - ctc_val; /* CTC counts down */
353 #if defined (CONFIG_SH_SIMULATOR)
355 * Let's pretend we are a 5MHz SH-5 to avoid a too
356 * little timer interval. Also to keep delay
357 * calibration within a reasonable time.
362 * This really is count by the number of clock cycles
363 * by the ratio between a complete R64CNT
364 * wrap-around (128) and CUI interrupt being raised (64).
370 static irqreturn_t sh64_rtc_interrupt(int irq, void *dev_id)
372 struct pt_regs *regs = get_irq_regs();
374 ctrl_outb(0, RTC_RCR1); /* Disable Carry Interrupts */
375 regs->regs[3] = 1; /* Using r3 */
380 static struct irqaction irq0 = {
381 .handler = timer_interrupt,
382 .flags = IRQF_DISABLED,
383 .mask = CPU_MASK_NONE,
386 static struct irqaction irq1 = {
387 .handler = sh64_rtc_interrupt,
388 .flags = IRQF_DISABLED,
389 .mask = CPU_MASK_NONE,
393 void __init time_init(void)
395 unsigned int cpu_clock, master_clock, bus_clock, module_clock;
396 unsigned long interval;
397 unsigned long frqcr, ifc, pfc;
398 static int ifc_table[] = { 2, 4, 6, 8, 10, 12, 16, 24 };
399 #define bfc_table ifc_table /* Same */
400 #define pfc_table ifc_table /* Same */
402 tmu_base = onchip_remap(TMU_BASE, 1024, "TMU");
404 panic("Unable to remap TMU\n");
407 rtc_base = onchip_remap(RTC_BASE, 1024, "RTC");
409 panic("Unable to remap RTC\n");
412 cprc_base = onchip_remap(CPRC_BASE, 1024, "CPRC");
414 panic("Unable to remap CPRC\n");
417 rtc_sh_get_time(&xtime);
419 setup_irq(TIMER_IRQ, &irq0);
420 setup_irq(RTC_IRQ, &irq1);
422 /* Check how fast it is.. */
423 cpu_clock = get_cpu_hz();
425 /* Note careful order of operations to maintain reasonable precision and avoid overflow. */
426 scaled_recip_ctc_ticks_per_jiffy = ((1ULL << CTC_JIFFY_SCALE_SHIFT) / (unsigned long long)(cpu_clock / HZ));
428 free_irq(RTC_IRQ, NULL);
430 printk("CPU clock: %d.%02dMHz\n",
431 (cpu_clock / 1000000), (cpu_clock % 1000000)/10000);
434 frqcr = ctrl_inl(FRQCR);
435 ifc = ifc_table[(frqcr>> 6) & 0x0007];
436 bfc = bfc_table[(frqcr>> 3) & 0x0007];
437 pfc = pfc_table[(frqcr>> 12) & 0x0007];
438 master_clock = cpu_clock * ifc;
439 bus_clock = master_clock/bfc;
442 printk("Bus clock: %d.%02dMHz\n",
443 (bus_clock/1000000), (bus_clock % 1000000)/10000);
444 module_clock = master_clock/pfc;
445 printk("Module clock: %d.%02dMHz\n",
446 (module_clock/1000000), (module_clock % 1000000)/10000);
447 interval = (module_clock/(HZ*4));
449 printk("Interval = %ld\n", interval);
451 current_cpu_data.cpu_clock = cpu_clock;
452 current_cpu_data.master_clock = master_clock;
453 current_cpu_data.bus_clock = bus_clock;
454 current_cpu_data.module_clock = module_clock;
457 ctrl_outb(TMU_TSTR_OFF, TMU_TSTR);
458 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
459 ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
460 ctrl_outl(interval, TMU0_TCOR);
461 ctrl_outl(interval, TMU0_TCNT);
462 ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
465 void enter_deep_standby(void)
467 /* Disable watchdog timer */
468 ctrl_outl(0xa5000000, WTCSR);
469 /* Configure deep standby on sleep */
470 ctrl_outl(0x03, STBCR);
472 #ifdef CONFIG_SH_ALPHANUMERIC
474 extern void mach_alphanum(int position, unsigned char value);
475 extern void mach_alphanum_brightness(int setting);
476 char halted[] = "Halted. ";
478 mach_alphanum_brightness(6); /* dimmest setting above off */
479 for (i=0; i<8; i++) {
480 mach_alphanum(i, halted[i]);
482 asm __volatile__ ("synco");
486 asm __volatile__ ("sleep");
487 asm __volatile__ ("synci");
488 asm __volatile__ ("nop");
489 asm __volatile__ ("nop");
490 asm __volatile__ ("nop");
491 asm __volatile__ ("nop");
492 panic("Unexpected wakeup!\n");
495 static struct resource rtc_resources[] = {
497 /* RTC base, filled in by rtc_init */
498 .flags = IORESOURCE_IO,
503 .flags = IORESOURCE_IRQ,
508 .flags = IORESOURCE_IRQ,
513 .flags = IORESOURCE_IRQ,
517 static struct platform_device rtc_device = {
520 .num_resources = ARRAY_SIZE(rtc_resources),
521 .resource = rtc_resources,
524 static int __init rtc_init(void)
526 rtc_resources[0].start = rtc_base;
527 rtc_resources[0].end = rtc_resources[0].start + 0x58 - 1;
529 return platform_device_register(&rtc_device);
531 device_initcall(rtc_init);