2 * pgtable.h: SpitFire page table operations.
4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #ifndef _SPARC64_PGTABLE_H
9 #define _SPARC64_PGTABLE_H
11 /* This file contains the functions and defines necessary to modify and use
12 * the SpitFire page tables.
15 #include <linux/compiler.h>
16 #include <linux/const.h>
17 #include <asm/types.h>
18 #include <asm/spitfire.h>
21 #include <asm/processor.h>
23 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB).
24 * The page copy blockops can use 0x6000000 to 0x8000000.
25 * The 8K TSB is mapped in the 0x8000000 to 0x8400000 range.
26 * The 4M TSB is mapped in the 0x8400000 to 0x8800000 range.
27 * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
28 * The vmalloc area spans 0x100000000 to 0x200000000.
29 * Since modules need to be in the lowest 32-bits of the address space,
30 * we place them right before the OBP area from 0x10000000 to 0xf0000000.
31 * There is a single static kernel PMD which maps from 0x0 to address
34 #define TLBTEMP_BASE _AC(0x0000000006000000,UL)
35 #define TSBMAP_8K_BASE _AC(0x0000000008000000,UL)
36 #define TSBMAP_4M_BASE _AC(0x0000000008400000,UL)
37 #define MODULES_VADDR _AC(0x0000000010000000,UL)
38 #define MODULES_LEN _AC(0x00000000e0000000,UL)
39 #define MODULES_END _AC(0x00000000f0000000,UL)
40 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
41 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
42 #define VMALLOC_START _AC(0x0000000100000000,UL)
43 #define VMALLOC_END _AC(0x0000010000000000,UL)
44 #define VMEMMAP_BASE _AC(0x0000010000000000,UL)
46 #define vmemmap ((struct page *)VMEMMAP_BASE)
48 /* PMD_SHIFT determines the size of the area a second-level page
51 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
52 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
53 #define PMD_MASK (~(PMD_SIZE-1))
54 #define PMD_BITS (PAGE_SHIFT - 3)
56 /* PUD_SHIFT determines the size of the area a third-level page
59 #define PUD_SHIFT (PMD_SHIFT + PMD_BITS)
60 #define PUD_SIZE (_AC(1,UL) << PUD_SHIFT)
61 #define PUD_MASK (~(PUD_SIZE-1))
62 #define PUD_BITS (PAGE_SHIFT - 3)
64 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */
65 #define PGDIR_SHIFT (PUD_SHIFT + PUD_BITS)
66 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
67 #define PGDIR_MASK (~(PGDIR_SIZE-1))
68 #define PGDIR_BITS (PAGE_SHIFT - 3)
70 #if (PGDIR_SHIFT + PGDIR_BITS) != 53
71 #error Page table parameters do not cover virtual address space properly.
74 #if (PMD_SHIFT != HPAGE_SHIFT)
75 #error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages.
80 #include <linux/sched.h>
82 extern unsigned long sparc64_valid_addr_bitmap[];
84 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
85 static inline bool __kern_addr_valid(unsigned long paddr)
87 if ((paddr >> MAX_PHYS_ADDRESS_BITS) != 0UL)
89 return test_bit(paddr >> ILOG2_4MB, sparc64_valid_addr_bitmap);
92 static inline bool kern_addr_valid(unsigned long addr)
94 unsigned long paddr = __pa(addr);
96 return __kern_addr_valid(paddr);
99 /* Entries per page directory level. */
100 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
101 #define PTRS_PER_PMD (1UL << PMD_BITS)
102 #define PTRS_PER_PUD (1UL << PUD_BITS)
103 #define PTRS_PER_PGD (1UL << PGDIR_BITS)
105 /* Kernel has a separate 44bit address space. */
106 #define FIRST_USER_ADDRESS 0
108 #define pmd_ERROR(e) \
109 pr_err("%s:%d: bad pmd %p(%016lx) seen at (%pS)\n", \
110 __FILE__, __LINE__, &(e), pmd_val(e), __builtin_return_address(0))
111 #define pud_ERROR(e) \
112 pr_err("%s:%d: bad pud %p(%016lx) seen at (%pS)\n", \
113 __FILE__, __LINE__, &(e), pud_val(e), __builtin_return_address(0))
114 #define pgd_ERROR(e) \
115 pr_err("%s:%d: bad pgd %p(%016lx) seen at (%pS)\n", \
116 __FILE__, __LINE__, &(e), pgd_val(e), __builtin_return_address(0))
118 #endif /* !(__ASSEMBLY__) */
120 /* PTE bits which are the same in SUN4U and SUN4V format. */
121 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
122 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
123 #define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */
124 #define _PAGE_PMD_HUGE _AC(0x0100000000000000,UL) /* Huge page */
126 /* Advertise support for _PAGE_SPECIAL */
127 #define __HAVE_ARCH_PTE_SPECIAL
129 /* SUN4U pte bits... */
130 #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */
131 #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */
132 #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */
133 #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */
134 #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */
135 #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */
136 #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
137 #define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */
138 #define _PAGE_PMD_HUGE_4U _AC(0x0100000000000000,UL) /* Huge page */
139 #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */
140 #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
141 #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
142 #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */
143 #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
144 #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */
145 #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */
146 #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */
147 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */
148 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */
149 #define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */
150 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
151 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */
152 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */
153 #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */
154 #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */
155 #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
156 #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
157 #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */
158 #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */
159 #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */
161 /* SUN4V pte bits... */
162 #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */
163 #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
164 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */
165 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */
166 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */
167 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */
168 #define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */
169 #define _PAGE_PMD_HUGE_4V _AC(0x0100000000000000,UL) /* Huge page */
170 #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */
171 #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */
172 #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */
173 #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
174 #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
175 #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */
176 #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */
177 #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */
178 #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */
179 #define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */
180 #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */
181 #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */
182 #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */
183 #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */
184 #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */
185 #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */
186 #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */
187 #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */
188 #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */
189 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */
190 #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */
192 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
193 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
195 #if REAL_HPAGE_SHIFT != 22
196 #error REAL_HPAGE_SHIFT and _PAGE_SZHUGE_foo must match up
199 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
200 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
202 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
203 #define __P000 __pgprot(0)
204 #define __P001 __pgprot(0)
205 #define __P010 __pgprot(0)
206 #define __P011 __pgprot(0)
207 #define __P100 __pgprot(0)
208 #define __P101 __pgprot(0)
209 #define __P110 __pgprot(0)
210 #define __P111 __pgprot(0)
212 #define __S000 __pgprot(0)
213 #define __S001 __pgprot(0)
214 #define __S010 __pgprot(0)
215 #define __S011 __pgprot(0)
216 #define __S100 __pgprot(0)
217 #define __S101 __pgprot(0)
218 #define __S110 __pgprot(0)
219 #define __S111 __pgprot(0)
223 extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
225 extern unsigned long pte_sz_bits(unsigned long size);
227 extern pgprot_t PAGE_KERNEL;
228 extern pgprot_t PAGE_KERNEL_LOCKED;
229 extern pgprot_t PAGE_COPY;
230 extern pgprot_t PAGE_SHARED;
232 /* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */
233 extern unsigned long _PAGE_IE;
234 extern unsigned long _PAGE_E;
235 extern unsigned long _PAGE_CACHE;
237 extern unsigned long pg_iobits;
238 extern unsigned long _PAGE_ALL_SZ_BITS;
240 extern struct page *mem_map_zero;
241 #define ZERO_PAGE(vaddr) (mem_map_zero)
243 /* PFNs are real physical page numbers. However, mem_map only begins to record
244 * per-page information starting at pfn_base. This is to handle systems where
245 * the first physical page in the machine is at some huge physical address,
246 * such as 4GB. This is common on a partitioned E10000, for example.
248 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
250 unsigned long paddr = pfn << PAGE_SHIFT;
252 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL);
253 return __pte(paddr | pgprot_val(prot));
255 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
257 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
258 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
260 pte_t pte = pfn_pte(page_nr, pgprot);
262 return __pmd(pte_val(pte));
264 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
267 /* This one can be done with two shifts. */
268 static inline unsigned long pte_pfn(pte_t pte)
272 __asm__ __volatile__(
273 "\n661: sllx %1, %2, %0\n"
275 " .section .sun4v_2insn_patch, \"ax\"\n"
281 : "r" (pte_val(pte)),
282 "i" (21), "i" (21 + PAGE_SHIFT),
283 "i" (8), "i" (8 + PAGE_SHIFT));
287 #define pte_page(x) pfn_to_page(pte_pfn(x))
289 static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
291 unsigned long mask, tmp;
293 /* SUN4U: 0x630107ffffffec38 (negated == 0x9cfef800000013c7)
294 * SUN4V: 0x33ffffffffffee07 (negated == 0xcc000000000011f8)
296 * Even if we use negation tricks the result is still a 6
297 * instruction sequence, so don't try to play fancy and just
298 * do the most straightforward implementation.
300 * Note: We encode this into 3 sun4v 2-insn patch sequences.
303 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL);
304 __asm__ __volatile__(
305 "\n661: sethi %%uhi(%2), %1\n"
306 " sethi %%hi(%2), %0\n"
307 "\n662: or %1, %%ulo(%2), %1\n"
308 " or %0, %%lo(%2), %0\n"
309 "\n663: sllx %1, 32, %1\n"
311 " .section .sun4v_2insn_patch, \"ax\"\n"
313 " sethi %%uhi(%3), %1\n"
314 " sethi %%hi(%3), %0\n"
316 " or %1, %%ulo(%3), %1\n"
317 " or %0, %%lo(%3), %0\n"
322 : "=r" (mask), "=r" (tmp)
323 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U |
324 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U |
325 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4U),
326 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
327 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V |
328 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V));
330 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
333 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
334 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
336 pte_t pte = __pte(pmd_val(pmd));
338 pte = pte_modify(pte, newprot);
340 return __pmd(pte_val(pte));
344 static inline pte_t pgoff_to_pte(unsigned long off)
348 __asm__ __volatile__(
349 "\n661: or %0, %2, %0\n"
350 " .section .sun4v_1insn_patch, \"ax\"\n"
355 : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
360 static inline pgprot_t pgprot_noncached(pgprot_t prot)
362 unsigned long val = pgprot_val(prot);
364 __asm__ __volatile__(
365 "\n661: andn %0, %2, %0\n"
367 " .section .sun4v_2insn_patch, \"ax\"\n"
373 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U),
374 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V));
376 return __pgprot(val);
378 /* Various pieces of code check for platform support by ifdef testing
379 * on "pgprot_noncached". That's broken and should be fixed, but for
382 #define pgprot_noncached pgprot_noncached
384 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
385 static inline pte_t pte_mkhuge(pte_t pte)
389 __asm__ __volatile__(
390 "\n661: sethi %%uhi(%1), %0\n"
392 " .section .sun4v_2insn_patch, \"ax\"\n"
398 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V));
400 return __pte(pte_val(pte) | mask);
402 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
403 static inline pmd_t pmd_mkhuge(pmd_t pmd)
405 pte_t pte = __pte(pmd_val(pmd));
407 pte = pte_mkhuge(pte);
408 pte_val(pte) |= _PAGE_PMD_HUGE;
410 return __pmd(pte_val(pte));
415 static inline pte_t pte_mkdirty(pte_t pte)
417 unsigned long val = pte_val(pte), tmp;
419 __asm__ __volatile__(
420 "\n661: or %0, %3, %0\n"
424 " .section .sun4v_2insn_patch, \"ax\"\n"
426 " sethi %%uhi(%4), %1\n"
429 " or %1, %%lo(%4), %1\n"
432 : "=r" (val), "=r" (tmp)
433 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
434 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
439 static inline pte_t pte_mkclean(pte_t pte)
441 unsigned long val = pte_val(pte), tmp;
443 __asm__ __volatile__(
444 "\n661: andn %0, %3, %0\n"
448 " .section .sun4v_2insn_patch, \"ax\"\n"
450 " sethi %%uhi(%4), %1\n"
453 " or %1, %%lo(%4), %1\n"
456 : "=r" (val), "=r" (tmp)
457 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
458 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
463 static inline pte_t pte_mkwrite(pte_t pte)
465 unsigned long val = pte_val(pte), mask;
467 __asm__ __volatile__(
468 "\n661: mov %1, %0\n"
470 " .section .sun4v_2insn_patch, \"ax\"\n"
472 " sethi %%uhi(%2), %0\n"
476 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
478 return __pte(val | mask);
481 static inline pte_t pte_wrprotect(pte_t pte)
483 unsigned long val = pte_val(pte), tmp;
485 __asm__ __volatile__(
486 "\n661: andn %0, %3, %0\n"
490 " .section .sun4v_2insn_patch, \"ax\"\n"
492 " sethi %%uhi(%4), %1\n"
495 " or %1, %%lo(%4), %1\n"
498 : "=r" (val), "=r" (tmp)
499 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U),
500 "i" (_PAGE_WRITE_4V | _PAGE_W_4V));
505 static inline pte_t pte_mkold(pte_t pte)
509 __asm__ __volatile__(
510 "\n661: mov %1, %0\n"
512 " .section .sun4v_2insn_patch, \"ax\"\n"
514 " sethi %%uhi(%2), %0\n"
518 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
522 return __pte(pte_val(pte) & ~mask);
525 static inline pte_t pte_mkyoung(pte_t pte)
529 __asm__ __volatile__(
530 "\n661: mov %1, %0\n"
532 " .section .sun4v_2insn_patch, \"ax\"\n"
534 " sethi %%uhi(%2), %0\n"
538 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
542 return __pte(pte_val(pte) | mask);
545 static inline pte_t pte_mkspecial(pte_t pte)
547 pte_val(pte) |= _PAGE_SPECIAL;
551 static inline unsigned long pte_young(pte_t pte)
555 __asm__ __volatile__(
556 "\n661: mov %1, %0\n"
558 " .section .sun4v_2insn_patch, \"ax\"\n"
560 " sethi %%uhi(%2), %0\n"
564 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
566 return (pte_val(pte) & mask);
569 static inline unsigned long pte_dirty(pte_t pte)
573 __asm__ __volatile__(
574 "\n661: mov %1, %0\n"
576 " .section .sun4v_2insn_patch, \"ax\"\n"
578 " sethi %%uhi(%2), %0\n"
582 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V));
584 return (pte_val(pte) & mask);
587 static inline unsigned long pte_write(pte_t pte)
591 __asm__ __volatile__(
592 "\n661: mov %1, %0\n"
594 " .section .sun4v_2insn_patch, \"ax\"\n"
596 " sethi %%uhi(%2), %0\n"
600 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
602 return (pte_val(pte) & mask);
605 static inline unsigned long pte_exec(pte_t pte)
609 __asm__ __volatile__(
610 "\n661: sethi %%hi(%1), %0\n"
611 " .section .sun4v_1insn_patch, \"ax\"\n"
616 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V));
618 return (pte_val(pte) & mask);
621 static inline unsigned long pte_file(pte_t pte)
623 unsigned long val = pte_val(pte);
625 __asm__ __volatile__(
626 "\n661: and %0, %2, %0\n"
627 " .section .sun4v_1insn_patch, \"ax\"\n"
632 : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
637 static inline unsigned long pte_present(pte_t pte)
639 unsigned long val = pte_val(pte);
641 __asm__ __volatile__(
642 "\n661: and %0, %2, %0\n"
643 " .section .sun4v_1insn_patch, \"ax\"\n"
648 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V));
653 #define pte_accessible pte_accessible
654 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a)
656 return pte_val(a) & _PAGE_VALID;
659 static inline unsigned long pte_special(pte_t pte)
661 return pte_val(pte) & _PAGE_SPECIAL;
664 static inline unsigned long pmd_large(pmd_t pmd)
666 pte_t pte = __pte(pmd_val(pmd));
668 return pte_val(pte) & _PAGE_PMD_HUGE;
671 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
672 static inline unsigned long pmd_young(pmd_t pmd)
674 pte_t pte = __pte(pmd_val(pmd));
676 return pte_young(pte);
679 static inline unsigned long pmd_write(pmd_t pmd)
681 pte_t pte = __pte(pmd_val(pmd));
683 return pte_write(pte);
686 static inline unsigned long pmd_pfn(pmd_t pmd)
688 pte_t pte = __pte(pmd_val(pmd));
693 static inline unsigned long pmd_trans_huge(pmd_t pmd)
695 pte_t pte = __pte(pmd_val(pmd));
697 return pte_val(pte) & _PAGE_PMD_HUGE;
700 static inline unsigned long pmd_trans_splitting(pmd_t pmd)
702 pte_t pte = __pte(pmd_val(pmd));
704 return pmd_trans_huge(pmd) && pte_special(pte);
707 #define has_transparent_hugepage() 1
709 static inline pmd_t pmd_mkold(pmd_t pmd)
711 pte_t pte = __pte(pmd_val(pmd));
713 pte = pte_mkold(pte);
715 return __pmd(pte_val(pte));
718 static inline pmd_t pmd_wrprotect(pmd_t pmd)
720 pte_t pte = __pte(pmd_val(pmd));
722 pte = pte_wrprotect(pte);
724 return __pmd(pte_val(pte));
727 static inline pmd_t pmd_mkdirty(pmd_t pmd)
729 pte_t pte = __pte(pmd_val(pmd));
731 pte = pte_mkdirty(pte);
733 return __pmd(pte_val(pte));
736 static inline pmd_t pmd_mkyoung(pmd_t pmd)
738 pte_t pte = __pte(pmd_val(pmd));
740 pte = pte_mkyoung(pte);
742 return __pmd(pte_val(pte));
745 static inline pmd_t pmd_mkwrite(pmd_t pmd)
747 pte_t pte = __pte(pmd_val(pmd));
749 pte = pte_mkwrite(pte);
751 return __pmd(pte_val(pte));
754 static inline pmd_t pmd_mksplitting(pmd_t pmd)
756 pte_t pte = __pte(pmd_val(pmd));
758 pte = pte_mkspecial(pte);
760 return __pmd(pte_val(pte));
763 static inline pgprot_t pmd_pgprot(pmd_t entry)
765 unsigned long val = pmd_val(entry);
767 return __pgprot(val);
771 static inline int pmd_present(pmd_t pmd)
773 return pmd_val(pmd) != 0UL;
776 #define pmd_none(pmd) (!pmd_val(pmd))
778 /* pmd_bad() is only called on non-trans-huge PMDs. Our encoding is
779 * very simple, it's just the physical address. PTE tables are of
780 * size PAGE_SIZE so make sure the sub-PAGE_SIZE bits are clear and
781 * the top bits outside of the range of any physical address size we
782 * support are clear as well. We also validate the physical itself.
784 #define pmd_bad(pmd) ((pmd_val(pmd) & ~PAGE_MASK) || \
785 !__kern_addr_valid(pmd_val(pmd)))
787 #define pud_none(pud) (!pud_val(pud))
789 #define pud_bad(pud) ((pud_val(pud) & ~PAGE_MASK) || \
790 !__kern_addr_valid(pud_val(pud)))
792 #define pgd_none(pgd) (!pgd_val(pgd))
794 #define pgd_bad(pgd) ((pgd_val(pgd) & ~PAGE_MASK) || \
795 !__kern_addr_valid(pgd_val(pgd)))
797 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
798 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
799 pmd_t *pmdp, pmd_t pmd);
801 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
802 pmd_t *pmdp, pmd_t pmd)
808 static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
810 unsigned long val = __pa((unsigned long) (ptep));
812 pmd_val(*pmdp) = val;
815 #define pud_set(pudp, pmdp) \
816 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp))))
817 static inline unsigned long __pmd_page(pmd_t pmd)
819 pte_t pte = __pte(pmd_val(pmd));
824 return ((unsigned long) __va(pfn << PAGE_SHIFT));
826 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
827 #define pud_page_vaddr(pud) \
828 ((unsigned long) __va(pud_val(pud)))
829 #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud))
830 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
831 #define pud_present(pud) (pud_val(pud) != 0U)
832 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL)
833 #define pgd_page_vaddr(pgd) \
834 ((unsigned long) __va(pgd_val(pgd)))
835 #define pgd_present(pgd) (pgd_val(pgd) != 0U)
836 #define pgd_clear(pgdp) (pgd_val(*(pgd)) = 0UL)
838 /* Same in both SUN4V and SUN4U. */
839 #define pte_none(pte) (!pte_val(pte))
841 #define pgd_set(pgdp, pudp) \
842 (pgd_val(*(pgdp)) = (__pa((unsigned long) (pudp))))
844 /* to find an entry in a page-table-directory. */
845 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
846 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
848 /* to find an entry in a kernel page-table-directory */
849 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
851 /* Find an entry in the third-level page table.. */
852 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
853 #define pud_offset(pgdp, address) \
854 ((pud_t *) pgd_page_vaddr(*(pgdp)) + pud_index(address))
856 /* Find an entry in the second-level page table.. */
857 #define pmd_offset(pudp, address) \
858 ((pmd_t *) pud_page_vaddr(*(pudp)) + \
859 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
861 /* Find an entry in the third-level page table.. */
862 #define pte_index(dir, address) \
863 ((pte_t *) __pmd_page(*(dir)) + \
864 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
865 #define pte_offset_kernel pte_index
866 #define pte_offset_map pte_index
867 #define pte_unmap(pte) do { } while (0)
869 /* Actual page table PTE updates. */
870 extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr,
871 pte_t *ptep, pte_t orig, int fullmm);
873 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR
874 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
879 set_pmd_at(mm, addr, pmdp, __pmd(0UL));
883 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
884 pte_t *ptep, pte_t pte, int fullmm)
890 /* It is more efficient to let flush_tlb_kernel_range()
891 * handle init_mm tlb flushes.
893 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
894 * and SUN4V pte layout, so this inline test is fine.
896 if (likely(mm != &init_mm) && pte_accessible(mm, orig))
897 tlb_batch_add(mm, addr, ptep, orig, fullmm);
900 #define set_pte_at(mm,addr,ptep,pte) \
901 __set_pte_at((mm), (addr), (ptep), (pte), 0)
903 #define pte_clear(mm,addr,ptep) \
904 set_pte_at((mm), (addr), (ptep), __pte(0UL))
906 #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
907 #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \
908 __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm))
910 #ifdef DCACHE_ALIASING_POSSIBLE
911 #define __HAVE_ARCH_MOVE_PTE
912 #define move_pte(pte, prot, old_addr, new_addr) \
914 pte_t newpte = (pte); \
915 if (tlb_type != hypervisor && pte_present(pte)) { \
916 unsigned long this_pfn = pte_pfn(pte); \
918 if (pfn_valid(this_pfn) && \
919 (((old_addr) ^ (new_addr)) & (1 << 13))) \
920 flush_dcache_page_all(current->mm, \
921 pfn_to_page(this_pfn)); \
927 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
928 extern pmd_t swapper_low_pmd_dir[PTRS_PER_PMD];
930 extern void paging_init(void);
931 extern unsigned long find_ecache_flush_span(unsigned long size);
934 extern void mmu_info(struct seq_file *);
936 struct vm_area_struct;
937 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
938 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
939 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
942 #define __HAVE_ARCH_PMDP_INVALIDATE
943 extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
946 #define __HAVE_ARCH_PGTABLE_DEPOSIT
947 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
950 #define __HAVE_ARCH_PGTABLE_WITHDRAW
951 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
954 /* Encode and de-code a swap entry */
955 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
956 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
957 #define __swp_entry(type, offset) \
960 (((long)(type) << PAGE_SHIFT) | \
961 ((long)(offset) << (PAGE_SHIFT + 8UL))) \
963 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
964 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
966 /* File offset in PTE support. */
967 extern unsigned long pte_file(pte_t);
968 #define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT)
969 extern pte_t pgoff_to_pte(unsigned long);
970 #define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL)
972 extern int page_in_phys_avail(unsigned long paddr);
975 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
976 * its high 4 bits. These macros/functions put it there or get it from there.
978 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
979 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
980 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL)
982 extern int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long,
983 unsigned long, pgprot_t);
985 static inline int io_remap_pfn_range(struct vm_area_struct *vma,
986 unsigned long from, unsigned long pfn,
987 unsigned long size, pgprot_t prot)
989 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT;
990 int space = GET_IOSPACE(pfn);
991 unsigned long phys_base;
993 phys_base = offset | (((unsigned long) space) << 32UL);
995 return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot);
997 #define io_remap_pfn_range io_remap_pfn_range
999 #include <asm/tlbflush.h>
1000 #include <asm-generic/pgtable.h>
1002 /* We provide our own get_unmapped_area to cope with VA holes and
1003 * SHM area cache aliasing for userland.
1005 #define HAVE_ARCH_UNMAPPED_AREA
1006 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
1008 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use
1009 * the largest alignment possible such that larget PTEs can be used.
1011 extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
1012 unsigned long, unsigned long,
1014 #define HAVE_ARCH_FB_UNMAPPED_AREA
1016 extern void pgtable_cache_init(void);
1017 extern void sun4v_register_fault_status(void);
1018 extern void sun4v_ktsb_register(void);
1019 extern void __init cheetah_ecache_flush_init(void);
1020 extern void sun4v_patch_tlb_handlers(void);
1022 extern unsigned long cmdline_memory_size;
1024 extern asmlinkage void do_sparc64_fault(struct pt_regs *regs);
1026 #endif /* !(__ASSEMBLY__) */
1028 #endif /* !(_SPARC64_PGTABLE_H) */