2 * pgtable.h: SpitFire page table operations.
4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #ifndef _SPARC64_PGTABLE_H
9 #define _SPARC64_PGTABLE_H
11 /* This file contains the functions and defines necessary to modify and use
12 * the SpitFire page tables.
15 #include <linux/compiler.h>
16 #include <linux/const.h>
17 #include <asm/types.h>
18 #include <asm/spitfire.h>
21 #include <asm/processor.h>
23 #include <asm-generic/pgtable-nopud.h>
25 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB).
26 * The page copy blockops can use 0x6000000 to 0x8000000.
27 * The TSB is mapped in the 0x8000000 to 0xa000000 range.
28 * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
29 * The vmalloc area spans 0x100000000 to 0x200000000.
30 * Since modules need to be in the lowest 32-bits of the address space,
31 * we place them right before the OBP area from 0x10000000 to 0xf0000000.
32 * There is a single static kernel PMD which maps from 0x0 to address
35 #define TLBTEMP_BASE _AC(0x0000000006000000,UL)
36 #define TSBMAP_BASE _AC(0x0000000008000000,UL)
37 #define MODULES_VADDR _AC(0x0000000010000000,UL)
38 #define MODULES_LEN _AC(0x00000000e0000000,UL)
39 #define MODULES_END _AC(0x00000000f0000000,UL)
40 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
41 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
42 #define VMALLOC_START _AC(0x0000000100000000,UL)
43 #define VMALLOC_END _AC(0x0000010000000000,UL)
44 #define VMEMMAP_BASE _AC(0x0000010000000000,UL)
46 #define vmemmap ((struct page *)VMEMMAP_BASE)
48 /* PMD_SHIFT determines the size of the area a second-level page
51 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
52 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
53 #define PMD_MASK (~(PMD_SIZE-1))
54 #define PMD_BITS (PAGE_SHIFT - 3)
56 /* PGDIR_SHIFT determines what a third-level page table entry can map */
57 #define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS)
58 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
59 #define PGDIR_MASK (~(PGDIR_SIZE-1))
60 #define PGDIR_BITS (PAGE_SHIFT - 3)
62 #if (PGDIR_SHIFT + PGDIR_BITS) != 43
63 #error Page table parameters do not cover virtual address space properly.
66 #if (PMD_SHIFT != HPAGE_SHIFT)
67 #error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages.
72 #include <linux/sched.h>
74 extern unsigned long sparc64_valid_addr_bitmap[];
76 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
77 static inline bool __kern_addr_valid(unsigned long paddr)
79 if ((paddr >> MAX_PHYS_ADDRESS_BITS) != 0UL)
81 return test_bit(paddr >> ILOG2_4MB, sparc64_valid_addr_bitmap);
84 static inline bool kern_addr_valid(unsigned long addr)
86 unsigned long paddr = __pa(addr);
88 return __kern_addr_valid(paddr);
91 /* Entries per page directory level. */
92 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
93 #define PTRS_PER_PMD (1UL << PMD_BITS)
94 #define PTRS_PER_PGD (1UL << PGDIR_BITS)
96 /* Kernel has a separate 44bit address space. */
97 #define FIRST_USER_ADDRESS 0
99 #define pte_ERROR(e) __builtin_trap()
100 #define pmd_ERROR(e) __builtin_trap()
101 #define pgd_ERROR(e) __builtin_trap()
103 #endif /* !(__ASSEMBLY__) */
105 /* PTE bits which are the same in SUN4U and SUN4V format. */
106 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
107 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
108 #define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */
109 #define _PAGE_PMD_HUGE _AC(0x0100000000000000,UL) /* Huge page */
111 /* Advertise support for _PAGE_SPECIAL */
112 #define __HAVE_ARCH_PTE_SPECIAL
114 /* SUN4U pte bits... */
115 #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */
116 #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */
117 #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */
118 #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */
119 #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */
120 #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */
121 #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
122 #define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */
123 #define _PAGE_PMD_HUGE_4U _AC(0x0100000000000000,UL) /* Huge page */
124 #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */
125 #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
126 #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
127 #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */
128 #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
129 #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */
130 #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */
131 #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */
132 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */
133 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */
134 #define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */
135 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
136 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */
137 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */
138 #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */
139 #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */
140 #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
141 #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
142 #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */
143 #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */
144 #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */
146 /* SUN4V pte bits... */
147 #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */
148 #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
149 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */
150 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */
151 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */
152 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */
153 #define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */
154 #define _PAGE_PMD_HUGE_4V _AC(0x0100000000000000,UL) /* Huge page */
155 #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */
156 #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */
157 #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */
158 #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
159 #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
160 #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */
161 #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */
162 #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */
163 #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */
164 #define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */
165 #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */
166 #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */
167 #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */
168 #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */
169 #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */
170 #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */
171 #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */
172 #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */
173 #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */
174 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */
175 #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */
177 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
178 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
180 #if REAL_HPAGE_SHIFT != 22
181 #error REAL_HPAGE_SHIFT and _PAGE_SZHUGE_foo must match up
184 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
185 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
187 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
188 #define __P000 __pgprot(0)
189 #define __P001 __pgprot(0)
190 #define __P010 __pgprot(0)
191 #define __P011 __pgprot(0)
192 #define __P100 __pgprot(0)
193 #define __P101 __pgprot(0)
194 #define __P110 __pgprot(0)
195 #define __P111 __pgprot(0)
197 #define __S000 __pgprot(0)
198 #define __S001 __pgprot(0)
199 #define __S010 __pgprot(0)
200 #define __S011 __pgprot(0)
201 #define __S100 __pgprot(0)
202 #define __S101 __pgprot(0)
203 #define __S110 __pgprot(0)
204 #define __S111 __pgprot(0)
208 extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
210 extern unsigned long pte_sz_bits(unsigned long size);
212 extern pgprot_t PAGE_KERNEL;
213 extern pgprot_t PAGE_KERNEL_LOCKED;
214 extern pgprot_t PAGE_COPY;
215 extern pgprot_t PAGE_SHARED;
217 /* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */
218 extern unsigned long _PAGE_IE;
219 extern unsigned long _PAGE_E;
220 extern unsigned long _PAGE_CACHE;
222 extern unsigned long pg_iobits;
223 extern unsigned long _PAGE_ALL_SZ_BITS;
225 extern struct page *mem_map_zero;
226 #define ZERO_PAGE(vaddr) (mem_map_zero)
228 /* PFNs are real physical page numbers. However, mem_map only begins to record
229 * per-page information starting at pfn_base. This is to handle systems where
230 * the first physical page in the machine is at some huge physical address,
231 * such as 4GB. This is common on a partitioned E10000, for example.
233 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
235 unsigned long paddr = pfn << PAGE_SHIFT;
237 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL);
238 return __pte(paddr | pgprot_val(prot));
240 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
242 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
243 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
245 pte_t pte = pfn_pte(page_nr, pgprot);
247 return __pmd(pte_val(pte));
249 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
252 /* This one can be done with two shifts. */
253 static inline unsigned long pte_pfn(pte_t pte)
257 __asm__ __volatile__(
258 "\n661: sllx %1, %2, %0\n"
260 " .section .sun4v_2insn_patch, \"ax\"\n"
266 : "r" (pte_val(pte)),
267 "i" (21), "i" (21 + PAGE_SHIFT),
268 "i" (8), "i" (8 + PAGE_SHIFT));
272 #define pte_page(x) pfn_to_page(pte_pfn(x))
274 static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
276 unsigned long mask, tmp;
278 /* SUN4U: 0x630107ffffffec38 (negated == 0x9cfef800000013c7)
279 * SUN4V: 0x33ffffffffffee07 (negated == 0xcc000000000011f8)
281 * Even if we use negation tricks the result is still a 6
282 * instruction sequence, so don't try to play fancy and just
283 * do the most straightforward implementation.
285 * Note: We encode this into 3 sun4v 2-insn patch sequences.
288 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL);
289 __asm__ __volatile__(
290 "\n661: sethi %%uhi(%2), %1\n"
291 " sethi %%hi(%2), %0\n"
292 "\n662: or %1, %%ulo(%2), %1\n"
293 " or %0, %%lo(%2), %0\n"
294 "\n663: sllx %1, 32, %1\n"
296 " .section .sun4v_2insn_patch, \"ax\"\n"
298 " sethi %%uhi(%3), %1\n"
299 " sethi %%hi(%3), %0\n"
301 " or %1, %%ulo(%3), %1\n"
302 " or %0, %%lo(%3), %0\n"
307 : "=r" (mask), "=r" (tmp)
308 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U |
309 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U |
310 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4U),
311 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
312 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V |
313 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V));
315 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
318 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
319 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
321 pte_t pte = __pte(pmd_val(pmd));
323 pte = pte_modify(pte, newprot);
325 return __pmd(pte_val(pte));
329 static inline pte_t pgoff_to_pte(unsigned long off)
333 __asm__ __volatile__(
334 "\n661: or %0, %2, %0\n"
335 " .section .sun4v_1insn_patch, \"ax\"\n"
340 : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
345 static inline pgprot_t pgprot_noncached(pgprot_t prot)
347 unsigned long val = pgprot_val(prot);
349 __asm__ __volatile__(
350 "\n661: andn %0, %2, %0\n"
352 " .section .sun4v_2insn_patch, \"ax\"\n"
358 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U),
359 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V));
361 return __pgprot(val);
363 /* Various pieces of code check for platform support by ifdef testing
364 * on "pgprot_noncached". That's broken and should be fixed, but for
367 #define pgprot_noncached pgprot_noncached
369 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
370 static inline pte_t pte_mkhuge(pte_t pte)
374 __asm__ __volatile__(
375 "\n661: sethi %%uhi(%1), %0\n"
377 " .section .sun4v_2insn_patch, \"ax\"\n"
383 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V));
385 return __pte(pte_val(pte) | mask);
387 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
388 static inline pmd_t pmd_mkhuge(pmd_t pmd)
390 pte_t pte = __pte(pmd_val(pmd));
392 pte = pte_mkhuge(pte);
393 pte_val(pte) |= _PAGE_PMD_HUGE;
395 return __pmd(pte_val(pte));
400 static inline pte_t pte_mkdirty(pte_t pte)
402 unsigned long val = pte_val(pte), tmp;
404 __asm__ __volatile__(
405 "\n661: or %0, %3, %0\n"
409 " .section .sun4v_2insn_patch, \"ax\"\n"
411 " sethi %%uhi(%4), %1\n"
414 " or %1, %%lo(%4), %1\n"
417 : "=r" (val), "=r" (tmp)
418 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
419 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
424 static inline pte_t pte_mkclean(pte_t pte)
426 unsigned long val = pte_val(pte), tmp;
428 __asm__ __volatile__(
429 "\n661: andn %0, %3, %0\n"
433 " .section .sun4v_2insn_patch, \"ax\"\n"
435 " sethi %%uhi(%4), %1\n"
438 " or %1, %%lo(%4), %1\n"
441 : "=r" (val), "=r" (tmp)
442 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
443 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
448 static inline pte_t pte_mkwrite(pte_t pte)
450 unsigned long val = pte_val(pte), mask;
452 __asm__ __volatile__(
453 "\n661: mov %1, %0\n"
455 " .section .sun4v_2insn_patch, \"ax\"\n"
457 " sethi %%uhi(%2), %0\n"
461 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
463 return __pte(val | mask);
466 static inline pte_t pte_wrprotect(pte_t pte)
468 unsigned long val = pte_val(pte), tmp;
470 __asm__ __volatile__(
471 "\n661: andn %0, %3, %0\n"
475 " .section .sun4v_2insn_patch, \"ax\"\n"
477 " sethi %%uhi(%4), %1\n"
480 " or %1, %%lo(%4), %1\n"
483 : "=r" (val), "=r" (tmp)
484 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U),
485 "i" (_PAGE_WRITE_4V | _PAGE_W_4V));
490 static inline pte_t pte_mkold(pte_t pte)
494 __asm__ __volatile__(
495 "\n661: mov %1, %0\n"
497 " .section .sun4v_2insn_patch, \"ax\"\n"
499 " sethi %%uhi(%2), %0\n"
503 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
507 return __pte(pte_val(pte) & ~mask);
510 static inline pte_t pte_mkyoung(pte_t pte)
514 __asm__ __volatile__(
515 "\n661: mov %1, %0\n"
517 " .section .sun4v_2insn_patch, \"ax\"\n"
519 " sethi %%uhi(%2), %0\n"
523 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
527 return __pte(pte_val(pte) | mask);
530 static inline pte_t pte_mkspecial(pte_t pte)
532 pte_val(pte) |= _PAGE_SPECIAL;
536 static inline unsigned long pte_young(pte_t pte)
540 __asm__ __volatile__(
541 "\n661: mov %1, %0\n"
543 " .section .sun4v_2insn_patch, \"ax\"\n"
545 " sethi %%uhi(%2), %0\n"
549 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
551 return (pte_val(pte) & mask);
554 static inline unsigned long pte_dirty(pte_t pte)
558 __asm__ __volatile__(
559 "\n661: mov %1, %0\n"
561 " .section .sun4v_2insn_patch, \"ax\"\n"
563 " sethi %%uhi(%2), %0\n"
567 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V));
569 return (pte_val(pte) & mask);
572 static inline unsigned long pte_write(pte_t pte)
576 __asm__ __volatile__(
577 "\n661: mov %1, %0\n"
579 " .section .sun4v_2insn_patch, \"ax\"\n"
581 " sethi %%uhi(%2), %0\n"
585 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
587 return (pte_val(pte) & mask);
590 static inline unsigned long pte_exec(pte_t pte)
594 __asm__ __volatile__(
595 "\n661: sethi %%hi(%1), %0\n"
596 " .section .sun4v_1insn_patch, \"ax\"\n"
601 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V));
603 return (pte_val(pte) & mask);
606 static inline unsigned long pte_file(pte_t pte)
608 unsigned long val = pte_val(pte);
610 __asm__ __volatile__(
611 "\n661: and %0, %2, %0\n"
612 " .section .sun4v_1insn_patch, \"ax\"\n"
617 : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
622 static inline unsigned long pte_present(pte_t pte)
624 unsigned long val = pte_val(pte);
626 __asm__ __volatile__(
627 "\n661: and %0, %2, %0\n"
628 " .section .sun4v_1insn_patch, \"ax\"\n"
633 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V));
638 #define pte_accessible pte_accessible
639 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a)
641 return pte_val(a) & _PAGE_VALID;
644 static inline unsigned long pte_special(pte_t pte)
646 return pte_val(pte) & _PAGE_SPECIAL;
649 static inline unsigned long pmd_large(pmd_t pmd)
651 pte_t pte = __pte(pmd_val(pmd));
653 return pte_val(pte) & _PAGE_PMD_HUGE;
656 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
657 static inline unsigned long pmd_young(pmd_t pmd)
659 pte_t pte = __pte(pmd_val(pmd));
661 return pte_young(pte);
664 static inline unsigned long pmd_write(pmd_t pmd)
666 pte_t pte = __pte(pmd_val(pmd));
668 return pte_write(pte);
671 static inline unsigned long pmd_pfn(pmd_t pmd)
673 pte_t pte = __pte(pmd_val(pmd));
678 static inline unsigned long pmd_trans_huge(pmd_t pmd)
680 pte_t pte = __pte(pmd_val(pmd));
682 return pte_val(pte) & _PAGE_PMD_HUGE;
685 static inline unsigned long pmd_trans_splitting(pmd_t pmd)
687 pte_t pte = __pte(pmd_val(pmd));
689 return pmd_trans_huge(pmd) && pte_special(pte);
692 #define has_transparent_hugepage() 1
694 static inline pmd_t pmd_mkold(pmd_t pmd)
696 pte_t pte = __pte(pmd_val(pmd));
698 pte = pte_mkold(pte);
700 return __pmd(pte_val(pte));
703 static inline pmd_t pmd_wrprotect(pmd_t pmd)
705 pte_t pte = __pte(pmd_val(pmd));
707 pte = pte_wrprotect(pte);
709 return __pmd(pte_val(pte));
712 static inline pmd_t pmd_mkdirty(pmd_t pmd)
714 pte_t pte = __pte(pmd_val(pmd));
716 pte = pte_mkdirty(pte);
718 return __pmd(pte_val(pte));
721 static inline pmd_t pmd_mkyoung(pmd_t pmd)
723 pte_t pte = __pte(pmd_val(pmd));
725 pte = pte_mkyoung(pte);
727 return __pmd(pte_val(pte));
730 static inline pmd_t pmd_mkwrite(pmd_t pmd)
732 pte_t pte = __pte(pmd_val(pmd));
734 pte = pte_mkwrite(pte);
736 return __pmd(pte_val(pte));
739 static inline pmd_t pmd_mksplitting(pmd_t pmd)
741 pte_t pte = __pte(pmd_val(pmd));
743 pte = pte_mkspecial(pte);
745 return __pmd(pte_val(pte));
748 static inline pgprot_t pmd_pgprot(pmd_t entry)
750 unsigned long val = pmd_val(entry);
752 return __pgprot(val);
756 static inline int pmd_present(pmd_t pmd)
758 return pmd_val(pmd) != 0UL;
761 #define pmd_none(pmd) (!pmd_val(pmd))
763 /* pmd_bad() is only called on non-trans-huge PMDs. Our encoding is
764 * very simple, it's just the physical address. PTE tables are of
765 * size PAGE_SIZE so make sure the sub-PAGE_SIZE bits are clear and
766 * the top bits outside of the range of any physical address size we
767 * support are clear as well. We also validate the physical itself.
769 #define pmd_bad(pmd) ((pmd_val(pmd) & ~PAGE_MASK) || \
770 !__kern_addr_valid(pmd_val(pmd)))
772 #define pud_none(pud) (!pud_val(pud))
774 #define pud_bad(pud) ((pud_val(pud) & ~PAGE_MASK) || \
775 !__kern_addr_valid(pud_val(pud)))
777 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
778 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
779 pmd_t *pmdp, pmd_t pmd);
781 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
782 pmd_t *pmdp, pmd_t pmd)
788 static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
790 unsigned long val = __pa((unsigned long) (ptep));
792 pmd_val(*pmdp) = val;
795 #define pud_set(pudp, pmdp) \
796 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp))))
797 static inline unsigned long __pmd_page(pmd_t pmd)
799 pte_t pte = __pte(pmd_val(pmd));
804 return ((unsigned long) __va(pfn << PAGE_SHIFT));
806 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
807 #define pud_page_vaddr(pud) \
808 ((unsigned long) __va(pud_val(pud)))
809 #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud))
810 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
811 #define pud_present(pud) (pud_val(pud) != 0U)
812 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL)
814 /* Same in both SUN4V and SUN4U. */
815 #define pte_none(pte) (!pte_val(pte))
817 /* to find an entry in a page-table-directory. */
818 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
819 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
821 /* to find an entry in a kernel page-table-directory */
822 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
824 /* Find an entry in the second-level page table.. */
825 #define pmd_offset(pudp, address) \
826 ((pmd_t *) pud_page_vaddr(*(pudp)) + \
827 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
829 /* Find an entry in the third-level page table.. */
830 #define pte_index(dir, address) \
831 ((pte_t *) __pmd_page(*(dir)) + \
832 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
833 #define pte_offset_kernel pte_index
834 #define pte_offset_map pte_index
835 #define pte_unmap(pte) do { } while (0)
837 /* Actual page table PTE updates. */
838 extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr,
839 pte_t *ptep, pte_t orig, int fullmm);
841 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR
842 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
847 set_pmd_at(mm, addr, pmdp, __pmd(0UL));
851 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
852 pte_t *ptep, pte_t pte, int fullmm)
858 /* It is more efficient to let flush_tlb_kernel_range()
859 * handle init_mm tlb flushes.
861 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
862 * and SUN4V pte layout, so this inline test is fine.
864 if (likely(mm != &init_mm) && pte_accessible(mm, orig))
865 tlb_batch_add(mm, addr, ptep, orig, fullmm);
868 #define set_pte_at(mm,addr,ptep,pte) \
869 __set_pte_at((mm), (addr), (ptep), (pte), 0)
871 #define pte_clear(mm,addr,ptep) \
872 set_pte_at((mm), (addr), (ptep), __pte(0UL))
874 #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
875 #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \
876 __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm))
878 #ifdef DCACHE_ALIASING_POSSIBLE
879 #define __HAVE_ARCH_MOVE_PTE
880 #define move_pte(pte, prot, old_addr, new_addr) \
882 pte_t newpte = (pte); \
883 if (tlb_type != hypervisor && pte_present(pte)) { \
884 unsigned long this_pfn = pte_pfn(pte); \
886 if (pfn_valid(this_pfn) && \
887 (((old_addr) ^ (new_addr)) & (1 << 13))) \
888 flush_dcache_page_all(current->mm, \
889 pfn_to_page(this_pfn)); \
895 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
896 extern pmd_t swapper_low_pmd_dir[PTRS_PER_PMD];
898 extern void paging_init(void);
899 extern unsigned long find_ecache_flush_span(unsigned long size);
902 extern void mmu_info(struct seq_file *);
904 struct vm_area_struct;
905 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
906 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
907 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
910 #define __HAVE_ARCH_PMDP_INVALIDATE
911 extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
914 #define __HAVE_ARCH_PGTABLE_DEPOSIT
915 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
918 #define __HAVE_ARCH_PGTABLE_WITHDRAW
919 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
922 /* Encode and de-code a swap entry */
923 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
924 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
925 #define __swp_entry(type, offset) \
928 (((long)(type) << PAGE_SHIFT) | \
929 ((long)(offset) << (PAGE_SHIFT + 8UL))) \
931 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
932 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
934 /* File offset in PTE support. */
935 extern unsigned long pte_file(pte_t);
936 #define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT)
937 extern pte_t pgoff_to_pte(unsigned long);
938 #define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL)
940 extern int page_in_phys_avail(unsigned long paddr);
943 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
944 * its high 4 bits. These macros/functions put it there or get it from there.
946 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
947 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
948 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL)
950 extern int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long,
951 unsigned long, pgprot_t);
953 static inline int io_remap_pfn_range(struct vm_area_struct *vma,
954 unsigned long from, unsigned long pfn,
955 unsigned long size, pgprot_t prot)
957 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT;
958 int space = GET_IOSPACE(pfn);
959 unsigned long phys_base;
961 phys_base = offset | (((unsigned long) space) << 32UL);
963 return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot);
965 #define io_remap_pfn_range io_remap_pfn_range
967 #include <asm/tlbflush.h>
968 #include <asm-generic/pgtable.h>
970 /* We provide our own get_unmapped_area to cope with VA holes and
971 * SHM area cache aliasing for userland.
973 #define HAVE_ARCH_UNMAPPED_AREA
974 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
976 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use
977 * the largest alignment possible such that larget PTEs can be used.
979 extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
980 unsigned long, unsigned long,
982 #define HAVE_ARCH_FB_UNMAPPED_AREA
984 extern void pgtable_cache_init(void);
985 extern void sun4v_register_fault_status(void);
986 extern void sun4v_ktsb_register(void);
987 extern void __init cheetah_ecache_flush_init(void);
988 extern void sun4v_patch_tlb_handlers(void);
990 extern unsigned long cmdline_memory_size;
992 extern asmlinkage void do_sparc64_fault(struct pt_regs *regs);
994 #endif /* !(__ASSEMBLY__) */
996 #endif /* !(_SPARC64_PGTABLE_H) */