2 * pgtable.h: SpitFire page table operations.
4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #ifndef _SPARC64_PGTABLE_H
9 #define _SPARC64_PGTABLE_H
11 /* This file contains the functions and defines necessary to modify and use
12 * the SpitFire page tables.
15 #include <linux/compiler.h>
16 #include <linux/const.h>
17 #include <asm/types.h>
18 #include <asm/spitfire.h>
21 #include <asm/processor.h>
23 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB).
24 * The page copy blockops can use 0x6000000 to 0x8000000.
25 * The 8K TSB is mapped in the 0x8000000 to 0x8400000 range.
26 * The 4M TSB is mapped in the 0x8400000 to 0x8800000 range.
27 * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
28 * The vmalloc area spans 0x100000000 to 0x200000000.
29 * Since modules need to be in the lowest 32-bits of the address space,
30 * we place them right before the OBP area from 0x10000000 to 0xf0000000.
31 * There is a single static kernel PMD which maps from 0x0 to address
34 #define TLBTEMP_BASE _AC(0x0000000006000000,UL)
35 #define TSBMAP_8K_BASE _AC(0x0000000008000000,UL)
36 #define TSBMAP_4M_BASE _AC(0x0000000008400000,UL)
37 #define MODULES_VADDR _AC(0x0000000010000000,UL)
38 #define MODULES_LEN _AC(0x00000000e0000000,UL)
39 #define MODULES_END _AC(0x00000000f0000000,UL)
40 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
41 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
42 #define VMALLOC_START _AC(0x0000000100000000,UL)
43 #define VMEMMAP_BASE VMALLOC_END
45 /* PMD_SHIFT determines the size of the area a second-level page
48 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
49 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
50 #define PMD_MASK (~(PMD_SIZE-1))
51 #define PMD_BITS (PAGE_SHIFT - 3)
53 /* PUD_SHIFT determines the size of the area a third-level page
56 #define PUD_SHIFT (PMD_SHIFT + PMD_BITS)
57 #define PUD_SIZE (_AC(1,UL) << PUD_SHIFT)
58 #define PUD_MASK (~(PUD_SIZE-1))
59 #define PUD_BITS (PAGE_SHIFT - 3)
61 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */
62 #define PGDIR_SHIFT (PUD_SHIFT + PUD_BITS)
63 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
64 #define PGDIR_MASK (~(PGDIR_SIZE-1))
65 #define PGDIR_BITS (PAGE_SHIFT - 3)
67 #if (MAX_PHYS_ADDRESS_BITS > PGDIR_SHIFT + PGDIR_BITS)
68 #error MAX_PHYS_ADDRESS_BITS exceeds what kernel page tables can support
71 #if (PGDIR_SHIFT + PGDIR_BITS) != 53
72 #error Page table parameters do not cover virtual address space properly.
75 #if (PMD_SHIFT != HPAGE_SHIFT)
76 #error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages.
81 extern unsigned long VMALLOC_END;
83 #define vmemmap ((struct page *)VMEMMAP_BASE)
85 #include <linux/sched.h>
87 bool kern_addr_valid(unsigned long addr);
89 /* Entries per page directory level. */
90 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
91 #define PTRS_PER_PMD (1UL << PMD_BITS)
92 #define PTRS_PER_PUD (1UL << PUD_BITS)
93 #define PTRS_PER_PGD (1UL << PGDIR_BITS)
95 /* Kernel has a separate 44bit address space. */
96 #define FIRST_USER_ADDRESS 0UL
98 #define pmd_ERROR(e) \
99 pr_err("%s:%d: bad pmd %p(%016lx) seen at (%pS)\n", \
100 __FILE__, __LINE__, &(e), pmd_val(e), __builtin_return_address(0))
101 #define pud_ERROR(e) \
102 pr_err("%s:%d: bad pud %p(%016lx) seen at (%pS)\n", \
103 __FILE__, __LINE__, &(e), pud_val(e), __builtin_return_address(0))
104 #define pgd_ERROR(e) \
105 pr_err("%s:%d: bad pgd %p(%016lx) seen at (%pS)\n", \
106 __FILE__, __LINE__, &(e), pgd_val(e), __builtin_return_address(0))
108 #endif /* !(__ASSEMBLY__) */
110 /* PTE bits which are the same in SUN4U and SUN4V format. */
111 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
112 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
113 #define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */
114 #define _PAGE_PMD_HUGE _AC(0x0100000000000000,UL) /* Huge page */
115 #define _PAGE_PUD_HUGE _PAGE_PMD_HUGE
117 /* Advertise support for _PAGE_SPECIAL */
118 #define __HAVE_ARCH_PTE_SPECIAL
120 /* SUN4U pte bits... */
121 #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */
122 #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */
123 #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */
124 #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */
125 #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */
126 #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */
127 #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
128 #define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */
129 #define _PAGE_PMD_HUGE_4U _AC(0x0100000000000000,UL) /* Huge page */
130 #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */
131 #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
132 #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
133 #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */
134 #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
135 #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */
136 #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */
137 #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */
138 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */
139 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */
140 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
141 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */
142 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */
143 #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */
144 #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */
145 #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
146 #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
147 #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */
148 #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */
149 #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */
151 /* SUN4V pte bits... */
152 #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */
153 #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
154 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */
155 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */
156 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */
157 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */
158 #define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */
159 #define _PAGE_PMD_HUGE_4V _AC(0x0100000000000000,UL) /* Huge page */
160 #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */
161 #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */
162 #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */
163 #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
164 #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
165 #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */
166 #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */
167 #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */
168 #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */
169 #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */
170 #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */
171 #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */
172 #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */
173 #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */
174 #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */
175 #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */
176 #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */
177 #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */
178 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */
179 #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */
181 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
182 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
184 #if REAL_HPAGE_SHIFT != 22
185 #error REAL_HPAGE_SHIFT and _PAGE_SZHUGE_foo must match up
188 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
189 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
191 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
192 #define __P000 __pgprot(0)
193 #define __P001 __pgprot(0)
194 #define __P010 __pgprot(0)
195 #define __P011 __pgprot(0)
196 #define __P100 __pgprot(0)
197 #define __P101 __pgprot(0)
198 #define __P110 __pgprot(0)
199 #define __P111 __pgprot(0)
201 #define __S000 __pgprot(0)
202 #define __S001 __pgprot(0)
203 #define __S010 __pgprot(0)
204 #define __S011 __pgprot(0)
205 #define __S100 __pgprot(0)
206 #define __S101 __pgprot(0)
207 #define __S110 __pgprot(0)
208 #define __S111 __pgprot(0)
212 pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
214 unsigned long pte_sz_bits(unsigned long size);
216 extern pgprot_t PAGE_KERNEL;
217 extern pgprot_t PAGE_KERNEL_LOCKED;
218 extern pgprot_t PAGE_COPY;
219 extern pgprot_t PAGE_SHARED;
221 /* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */
222 extern unsigned long _PAGE_IE;
223 extern unsigned long _PAGE_E;
224 extern unsigned long _PAGE_CACHE;
226 extern unsigned long pg_iobits;
227 extern unsigned long _PAGE_ALL_SZ_BITS;
229 extern struct page *mem_map_zero;
230 #define ZERO_PAGE(vaddr) (mem_map_zero)
232 /* PFNs are real physical page numbers. However, mem_map only begins to record
233 * per-page information starting at pfn_base. This is to handle systems where
234 * the first physical page in the machine is at some huge physical address,
235 * such as 4GB. This is common on a partitioned E10000, for example.
237 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
239 unsigned long paddr = pfn << PAGE_SHIFT;
241 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL);
242 return __pte(paddr | pgprot_val(prot));
244 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
246 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
247 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
249 pte_t pte = pfn_pte(page_nr, pgprot);
251 return __pmd(pte_val(pte));
253 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
256 /* This one can be done with two shifts. */
257 static inline unsigned long pte_pfn(pte_t pte)
261 __asm__ __volatile__(
262 "\n661: sllx %1, %2, %0\n"
264 " .section .sun4v_2insn_patch, \"ax\"\n"
270 : "r" (pte_val(pte)),
271 "i" (21), "i" (21 + PAGE_SHIFT),
272 "i" (8), "i" (8 + PAGE_SHIFT));
276 #define pte_page(x) pfn_to_page(pte_pfn(x))
278 static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
280 unsigned long mask, tmp;
282 /* SUN4U: 0x630107ffffffec38 (negated == 0x9cfef800000013c7)
283 * SUN4V: 0x33ffffffffffee07 (negated == 0xcc000000000011f8)
285 * Even if we use negation tricks the result is still a 6
286 * instruction sequence, so don't try to play fancy and just
287 * do the most straightforward implementation.
289 * Note: We encode this into 3 sun4v 2-insn patch sequences.
292 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL);
293 __asm__ __volatile__(
294 "\n661: sethi %%uhi(%2), %1\n"
295 " sethi %%hi(%2), %0\n"
296 "\n662: or %1, %%ulo(%2), %1\n"
297 " or %0, %%lo(%2), %0\n"
298 "\n663: sllx %1, 32, %1\n"
300 " .section .sun4v_2insn_patch, \"ax\"\n"
302 " sethi %%uhi(%3), %1\n"
303 " sethi %%hi(%3), %0\n"
305 " or %1, %%ulo(%3), %1\n"
306 " or %0, %%lo(%3), %0\n"
311 : "=r" (mask), "=r" (tmp)
312 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U |
313 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U |
314 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4U),
315 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
316 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V |
317 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V));
319 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
322 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
323 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
325 pte_t pte = __pte(pmd_val(pmd));
327 pte = pte_modify(pte, newprot);
329 return __pmd(pte_val(pte));
333 static inline pgprot_t pgprot_noncached(pgprot_t prot)
335 unsigned long val = pgprot_val(prot);
337 __asm__ __volatile__(
338 "\n661: andn %0, %2, %0\n"
340 " .section .sun4v_2insn_patch, \"ax\"\n"
346 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U),
347 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V));
349 return __pgprot(val);
351 /* Various pieces of code check for platform support by ifdef testing
352 * on "pgprot_noncached". That's broken and should be fixed, but for
355 #define pgprot_noncached pgprot_noncached
357 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
358 static inline pte_t pte_mkhuge(pte_t pte)
362 __asm__ __volatile__(
363 "\n661: sethi %%uhi(%1), %0\n"
365 " .section .sun4v_2insn_patch, \"ax\"\n"
371 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V));
373 return __pte(pte_val(pte) | mask);
375 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
376 static inline pmd_t pmd_mkhuge(pmd_t pmd)
378 pte_t pte = __pte(pmd_val(pmd));
380 pte = pte_mkhuge(pte);
381 pte_val(pte) |= _PAGE_PMD_HUGE;
383 return __pmd(pte_val(pte));
388 static inline pte_t pte_mkdirty(pte_t pte)
390 unsigned long val = pte_val(pte), tmp;
392 __asm__ __volatile__(
393 "\n661: or %0, %3, %0\n"
397 " .section .sun4v_2insn_patch, \"ax\"\n"
399 " sethi %%uhi(%4), %1\n"
402 " or %1, %%lo(%4), %1\n"
405 : "=r" (val), "=r" (tmp)
406 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
407 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
412 static inline pte_t pte_mkclean(pte_t pte)
414 unsigned long val = pte_val(pte), tmp;
416 __asm__ __volatile__(
417 "\n661: andn %0, %3, %0\n"
421 " .section .sun4v_2insn_patch, \"ax\"\n"
423 " sethi %%uhi(%4), %1\n"
426 " or %1, %%lo(%4), %1\n"
429 : "=r" (val), "=r" (tmp)
430 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
431 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
436 static inline pte_t pte_mkwrite(pte_t pte)
438 unsigned long val = pte_val(pte), mask;
440 __asm__ __volatile__(
441 "\n661: mov %1, %0\n"
443 " .section .sun4v_2insn_patch, \"ax\"\n"
445 " sethi %%uhi(%2), %0\n"
449 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
451 return __pte(val | mask);
454 static inline pte_t pte_wrprotect(pte_t pte)
456 unsigned long val = pte_val(pte), tmp;
458 __asm__ __volatile__(
459 "\n661: andn %0, %3, %0\n"
463 " .section .sun4v_2insn_patch, \"ax\"\n"
465 " sethi %%uhi(%4), %1\n"
468 " or %1, %%lo(%4), %1\n"
471 : "=r" (val), "=r" (tmp)
472 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U),
473 "i" (_PAGE_WRITE_4V | _PAGE_W_4V));
478 static inline pte_t pte_mkold(pte_t pte)
482 __asm__ __volatile__(
483 "\n661: mov %1, %0\n"
485 " .section .sun4v_2insn_patch, \"ax\"\n"
487 " sethi %%uhi(%2), %0\n"
491 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
495 return __pte(pte_val(pte) & ~mask);
498 static inline pte_t pte_mkyoung(pte_t pte)
502 __asm__ __volatile__(
503 "\n661: mov %1, %0\n"
505 " .section .sun4v_2insn_patch, \"ax\"\n"
507 " sethi %%uhi(%2), %0\n"
511 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
515 return __pte(pte_val(pte) | mask);
518 static inline pte_t pte_mkspecial(pte_t pte)
520 pte_val(pte) |= _PAGE_SPECIAL;
524 static inline unsigned long pte_young(pte_t pte)
528 __asm__ __volatile__(
529 "\n661: mov %1, %0\n"
531 " .section .sun4v_2insn_patch, \"ax\"\n"
533 " sethi %%uhi(%2), %0\n"
537 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
539 return (pte_val(pte) & mask);
542 static inline unsigned long pte_dirty(pte_t pte)
546 __asm__ __volatile__(
547 "\n661: mov %1, %0\n"
549 " .section .sun4v_2insn_patch, \"ax\"\n"
551 " sethi %%uhi(%2), %0\n"
555 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V));
557 return (pte_val(pte) & mask);
560 static inline unsigned long pte_write(pte_t pte)
564 __asm__ __volatile__(
565 "\n661: mov %1, %0\n"
567 " .section .sun4v_2insn_patch, \"ax\"\n"
569 " sethi %%uhi(%2), %0\n"
573 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
575 return (pte_val(pte) & mask);
578 static inline unsigned long pte_exec(pte_t pte)
582 __asm__ __volatile__(
583 "\n661: sethi %%hi(%1), %0\n"
584 " .section .sun4v_1insn_patch, \"ax\"\n"
589 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V));
591 return (pte_val(pte) & mask);
594 static inline unsigned long pte_present(pte_t pte)
596 unsigned long val = pte_val(pte);
598 __asm__ __volatile__(
599 "\n661: and %0, %2, %0\n"
600 " .section .sun4v_1insn_patch, \"ax\"\n"
605 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V));
610 #define pte_accessible pte_accessible
611 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a)
613 return pte_val(a) & _PAGE_VALID;
616 static inline unsigned long pte_special(pte_t pte)
618 return pte_val(pte) & _PAGE_SPECIAL;
621 static inline unsigned long pmd_large(pmd_t pmd)
623 pte_t pte = __pte(pmd_val(pmd));
625 return pte_val(pte) & _PAGE_PMD_HUGE;
628 static inline unsigned long pmd_pfn(pmd_t pmd)
630 pte_t pte = __pte(pmd_val(pmd));
635 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
636 static inline unsigned long pmd_dirty(pmd_t pmd)
638 pte_t pte = __pte(pmd_val(pmd));
640 return pte_dirty(pte);
643 static inline unsigned long pmd_young(pmd_t pmd)
645 pte_t pte = __pte(pmd_val(pmd));
647 return pte_young(pte);
650 static inline unsigned long pmd_write(pmd_t pmd)
652 pte_t pte = __pte(pmd_val(pmd));
654 return pte_write(pte);
657 static inline unsigned long pmd_trans_huge(pmd_t pmd)
659 pte_t pte = __pte(pmd_val(pmd));
661 return pte_val(pte) & _PAGE_PMD_HUGE;
664 static inline unsigned long pmd_trans_splitting(pmd_t pmd)
666 pte_t pte = __pte(pmd_val(pmd));
668 return pmd_trans_huge(pmd) && pte_special(pte);
671 #define has_transparent_hugepage() 1
673 static inline pmd_t pmd_mkold(pmd_t pmd)
675 pte_t pte = __pte(pmd_val(pmd));
677 pte = pte_mkold(pte);
679 return __pmd(pte_val(pte));
682 static inline pmd_t pmd_wrprotect(pmd_t pmd)
684 pte_t pte = __pte(pmd_val(pmd));
686 pte = pte_wrprotect(pte);
688 return __pmd(pte_val(pte));
691 static inline pmd_t pmd_mkdirty(pmd_t pmd)
693 pte_t pte = __pte(pmd_val(pmd));
695 pte = pte_mkdirty(pte);
697 return __pmd(pte_val(pte));
700 static inline pmd_t pmd_mkyoung(pmd_t pmd)
702 pte_t pte = __pte(pmd_val(pmd));
704 pte = pte_mkyoung(pte);
706 return __pmd(pte_val(pte));
709 static inline pmd_t pmd_mkwrite(pmd_t pmd)
711 pte_t pte = __pte(pmd_val(pmd));
713 pte = pte_mkwrite(pte);
715 return __pmd(pte_val(pte));
718 static inline pmd_t pmd_mksplitting(pmd_t pmd)
720 pte_t pte = __pte(pmd_val(pmd));
722 pte = pte_mkspecial(pte);
724 return __pmd(pte_val(pte));
727 static inline pgprot_t pmd_pgprot(pmd_t entry)
729 unsigned long val = pmd_val(entry);
731 return __pgprot(val);
735 static inline int pmd_present(pmd_t pmd)
737 return pmd_val(pmd) != 0UL;
740 #define pmd_none(pmd) (!pmd_val(pmd))
742 /* pmd_bad() is only called on non-trans-huge PMDs. Our encoding is
743 * very simple, it's just the physical address. PTE tables are of
744 * size PAGE_SIZE so make sure the sub-PAGE_SIZE bits are clear and
745 * the top bits outside of the range of any physical address size we
746 * support are clear as well. We also validate the physical itself.
748 #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
750 #define pud_none(pud) (!pud_val(pud))
752 #define pud_bad(pud) (pud_val(pud) & ~PAGE_MASK)
754 #define pgd_none(pgd) (!pgd_val(pgd))
756 #define pgd_bad(pgd) (pgd_val(pgd) & ~PAGE_MASK)
758 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
759 void set_pmd_at(struct mm_struct *mm, unsigned long addr,
760 pmd_t *pmdp, pmd_t pmd);
762 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
763 pmd_t *pmdp, pmd_t pmd)
769 static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
771 unsigned long val = __pa((unsigned long) (ptep));
773 pmd_val(*pmdp) = val;
776 #define pud_set(pudp, pmdp) \
777 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp))))
778 static inline unsigned long __pmd_page(pmd_t pmd)
780 pte_t pte = __pte(pmd_val(pmd));
785 return ((unsigned long) __va(pfn << PAGE_SHIFT));
787 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
788 #define pud_page_vaddr(pud) \
789 ((unsigned long) __va(pud_val(pud)))
790 #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud))
791 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
792 #define pud_present(pud) (pud_val(pud) != 0U)
793 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL)
794 #define pgd_page_vaddr(pgd) \
795 ((unsigned long) __va(pgd_val(pgd)))
796 #define pgd_present(pgd) (pgd_val(pgd) != 0U)
797 #define pgd_clear(pgdp) (pgd_val(*(pgd)) = 0UL)
799 static inline unsigned long pud_large(pud_t pud)
801 pte_t pte = __pte(pud_val(pud));
803 return pte_val(pte) & _PAGE_PMD_HUGE;
806 static inline unsigned long pud_pfn(pud_t pud)
808 pte_t pte = __pte(pud_val(pud));
813 /* Same in both SUN4V and SUN4U. */
814 #define pte_none(pte) (!pte_val(pte))
816 #define pgd_set(pgdp, pudp) \
817 (pgd_val(*(pgdp)) = (__pa((unsigned long) (pudp))))
819 /* to find an entry in a page-table-directory. */
820 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
821 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
823 /* to find an entry in a kernel page-table-directory */
824 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
826 /* Find an entry in the third-level page table.. */
827 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
828 #define pud_offset(pgdp, address) \
829 ((pud_t *) pgd_page_vaddr(*(pgdp)) + pud_index(address))
831 /* Find an entry in the second-level page table.. */
832 #define pmd_offset(pudp, address) \
833 ((pmd_t *) pud_page_vaddr(*(pudp)) + \
834 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
836 /* Find an entry in the third-level page table.. */
837 #define pte_index(dir, address) \
838 ((pte_t *) __pmd_page(*(dir)) + \
839 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
840 #define pte_offset_kernel pte_index
841 #define pte_offset_map pte_index
842 #define pte_unmap(pte) do { } while (0)
844 /* Actual page table PTE updates. */
845 void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr,
846 pte_t *ptep, pte_t orig, int fullmm);
848 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR
849 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
854 set_pmd_at(mm, addr, pmdp, __pmd(0UL));
858 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
859 pte_t *ptep, pte_t pte, int fullmm)
865 /* It is more efficient to let flush_tlb_kernel_range()
866 * handle init_mm tlb flushes.
868 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
869 * and SUN4V pte layout, so this inline test is fine.
871 if (likely(mm != &init_mm) && pte_accessible(mm, orig))
872 tlb_batch_add(mm, addr, ptep, orig, fullmm);
875 #define set_pte_at(mm,addr,ptep,pte) \
876 __set_pte_at((mm), (addr), (ptep), (pte), 0)
878 #define pte_clear(mm,addr,ptep) \
879 set_pte_at((mm), (addr), (ptep), __pte(0UL))
881 #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
882 #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \
883 __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm))
885 #ifdef DCACHE_ALIASING_POSSIBLE
886 #define __HAVE_ARCH_MOVE_PTE
887 #define move_pte(pte, prot, old_addr, new_addr) \
889 pte_t newpte = (pte); \
890 if (tlb_type != hypervisor && pte_present(pte)) { \
891 unsigned long this_pfn = pte_pfn(pte); \
893 if (pfn_valid(this_pfn) && \
894 (((old_addr) ^ (new_addr)) & (1 << 13))) \
895 flush_dcache_page_all(current->mm, \
896 pfn_to_page(this_pfn)); \
902 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
904 void paging_init(void);
905 unsigned long find_ecache_flush_span(unsigned long size);
908 void mmu_info(struct seq_file *);
910 struct vm_area_struct;
911 void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
912 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
913 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
916 #define __HAVE_ARCH_PMDP_INVALIDATE
917 extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
920 #define __HAVE_ARCH_PGTABLE_DEPOSIT
921 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
924 #define __HAVE_ARCH_PGTABLE_WITHDRAW
925 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
928 /* Encode and de-code a swap entry */
929 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
930 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
931 #define __swp_entry(type, offset) \
934 (((long)(type) << PAGE_SHIFT) | \
935 ((long)(offset) << (PAGE_SHIFT + 8UL))) \
937 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
938 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
940 int page_in_phys_avail(unsigned long paddr);
943 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
944 * its high 4 bits. These macros/functions put it there or get it from there.
946 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
947 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
948 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL)
950 int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long,
951 unsigned long, pgprot_t);
953 static inline int io_remap_pfn_range(struct vm_area_struct *vma,
954 unsigned long from, unsigned long pfn,
955 unsigned long size, pgprot_t prot)
957 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT;
958 int space = GET_IOSPACE(pfn);
959 unsigned long phys_base;
961 phys_base = offset | (((unsigned long) space) << 32UL);
963 return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot);
965 #define io_remap_pfn_range io_remap_pfn_range
967 #include <asm/tlbflush.h>
968 #include <asm-generic/pgtable.h>
970 /* We provide our own get_unmapped_area to cope with VA holes and
971 * SHM area cache aliasing for userland.
973 #define HAVE_ARCH_UNMAPPED_AREA
974 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
976 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use
977 * the largest alignment possible such that larget PTEs can be used.
979 unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
980 unsigned long, unsigned long,
982 #define HAVE_ARCH_FB_UNMAPPED_AREA
984 void pgtable_cache_init(void);
985 void sun4v_register_fault_status(void);
986 void sun4v_ktsb_register(void);
987 void __init cheetah_ecache_flush_init(void);
988 void sun4v_patch_tlb_handlers(void);
990 extern unsigned long cmdline_memory_size;
992 asmlinkage void do_sparc64_fault(struct pt_regs *regs);
994 #endif /* !(__ASSEMBLY__) */
996 #endif /* !(_SPARC64_PGTABLE_H) */