1 /* head.S: Initial boot code for the Sparc64 port of Linux.
3 * Copyright (C) 1996, 1997, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
5 * Copyright (C) 1997, 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
9 #include <linux/version.h>
10 #include <linux/errno.h>
11 #include <linux/threads.h>
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/thread_info.h>
16 #include <asm/pstate.h>
17 #include <asm/ptrace.h>
18 #include <asm/spitfire.h>
20 #include <asm/pgtable.h>
21 #include <asm/errno.h>
22 #include <asm/signal.h>
23 #include <asm/processor.h>
28 #include <asm/ttable.h>
30 #include <asm/cpudata.h>
32 #include <asm/estate.h>
33 #include <asm/sfafsr.h>
34 #include <asm/unistd.h>
35 #include <asm/export.h>
37 /* This section from from _start to sparc64_boot_end should fit into
38 * 0x0000000000404000 to 0x0000000000408000.
41 .globl start, _start, stext, _stext
48 flushw /* Flush register file. */
50 /* This stuff has to be in sync with SILO and other potential boot loaders
51 * Fields should be kept upward compatible and whenever any change is made,
52 * HdrS version should be incremented.
54 .global root_flags, ram_flags, root_dev
55 .global sparc_ramdisk_image, sparc_ramdisk_size
56 .global sparc_ramdisk_image64
59 .word LINUX_VERSION_CODE
63 * 0x0300 : Supports being located at other than 0x4000
64 * 0x0202 : Supports kernel params string
65 * 0x0201 : Supports reboot_command
67 .half 0x0301 /* HdrS version */
81 sparc_ramdisk_image64:
85 /* PROM cif handler code address is in %o4. */
89 /* We need to remap the kernel. Use position independent
90 * code to remap us to KERNBASE.
92 * SILO can invoke us with 32-bit address masking enabled,
93 * so make sure that's clear.
96 andn %g1, PSTATE_AM, %g1
97 wrpr %g1, 0x0, %pstate
100 .globl prom_finddev_name, prom_chosen_path, prom_root_node
101 .globl prom_getprop_name, prom_mmu_name, prom_peer_name
102 .globl prom_callmethod_name, prom_translate_name, prom_root_compatible
103 .globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
104 .globl prom_boot_mapped_pc, prom_boot_mapping_mode
105 .globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
106 .globl prom_compatible_name, prom_cpu_path, prom_cpu_compatible
107 .globl is_sun4v, sun4v_chip_type, prom_set_trap_table_name
110 prom_compatible_name:
122 prom_callmethod_name:
130 prom_set_trap_table_name:
131 .asciz "SUNW,set-trap-table"
135 .asciz "SUNW,UltraSPARC-T"
138 prom_sparc64x_prefix:
141 prom_root_compatible:
147 EXPORT_SYMBOL(prom_root_node)
148 prom_mmu_ihandle_cache:
152 prom_boot_mapping_mode:
155 prom_boot_mapping_phys_high:
157 prom_boot_mapping_phys_low:
162 .word SUN4V_CHIP_INVALID
163 EXPORT_SYMBOL(sun4v_chip_type)
167 mov (1b - prom_peer_name), %l1
171 /* prom_root_node = prom_peer(0) */
172 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer"
174 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
175 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
176 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, 0
177 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
179 add %sp, (2047 + 128), %o0 ! argument array
181 ldx [%sp + 2047 + 128 + 0x20], %l4 ! prom root node
182 mov (1b - prom_root_node), %l1
186 mov (1b - prom_getprop_name), %l1
187 mov (1b - prom_compatible_name), %l2
188 mov (1b - prom_root_compatible), %l5
193 /* prom_getproperty(prom_root_node, "compatible",
194 * &prom_root_compatible, 64)
196 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
198 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
200 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
201 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, prom_root_node
202 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
203 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_root_compatible
205 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
206 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
208 add %sp, (2047 + 128), %o0 ! argument array
210 mov (1b - prom_finddev_name), %l1
211 mov (1b - prom_chosen_path), %l2
212 mov (1b - prom_boot_mapped_pc), %l3
217 sub %sp, (192 + 128), %sp
219 /* chosen_node = prom_finddevice("/chosen") */
220 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
222 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
223 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
224 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
225 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
227 add %sp, (2047 + 128), %o0 ! argument array
229 ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
231 mov (1b - prom_getprop_name), %l1
232 mov (1b - prom_mmu_name), %l2
233 mov (1b - prom_mmu_ihandle_cache), %l5
238 /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
239 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
241 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
243 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
244 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
245 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
246 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
248 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
249 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
251 add %sp, (2047 + 128), %o0 ! argument array
253 mov (1b - prom_callmethod_name), %l1
254 mov (1b - prom_translate_name), %l2
257 lduw [%l5], %l5 ! prom_mmu_ihandle_cache
259 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
261 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
263 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
264 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
265 stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
269 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
270 stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
271 stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
272 stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
273 stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
274 stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
276 add %sp, (2047 + 128), %o0 ! argument array
278 ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
279 mov (1b - prom_boot_mapping_mode), %l4
282 mov (1b - prom_boot_mapping_phys_high), %l4
284 ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
286 ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
288 srlx %l3, ILOG2_4MB, %l3
289 sllx %l3, ILOG2_4MB, %l3
292 /* Leave service as-is, "call-method" */
294 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
296 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
297 mov (1b - prom_map_name), %l3
299 stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
300 /* Leave arg2 as-is, prom_mmu_ihandle_cache */
302 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
303 /* 4MB align the kernel image size. */
304 set (_end - KERNBASE), %l3
305 set ((4 * 1024 * 1024) - 1), %l4
308 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: roundup(ksize, 4MB)
309 sethi %hi(KERNBASE), %l3
310 stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
311 stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
312 mov (1b - prom_boot_mapping_phys_low), %l3
315 stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
317 add %sp, (2047 + 128), %o0 ! argument array
319 add %sp, (192 + 128), %sp
321 sethi %hi(prom_root_compatible), %g1
322 or %g1, %lo(prom_root_compatible), %g1
323 sethi %hi(prom_sun4v_name), %g7
324 or %g7, %lo(prom_sun4v_name), %g7
335 sethi %hi(is_sun4v), %g1
336 or %g1, %lo(is_sun4v), %g1
340 /* cpu_node = prom_finddevice("/cpu") */
341 mov (1b - prom_finddev_name), %l1
342 mov (1b - prom_cpu_path), %l2
345 sub %sp, (192 + 128), %sp
347 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
349 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
350 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
351 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/cpu"
352 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
354 add %sp, (2047 + 128), %o0 ! argument array
356 ldx [%sp + 2047 + 128 + 0x20], %l4 ! cpu device node
358 mov (1b - prom_getprop_name), %l1
359 mov (1b - prom_compatible_name), %l2
360 mov (1b - prom_cpu_compatible), %l5
365 /* prom_getproperty(cpu_node, "compatible",
366 * &prom_cpu_compatible, 64)
368 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
370 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
372 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
373 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, cpu_node
374 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
375 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_cpu_compatible
377 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
378 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
380 add %sp, (2047 + 128), %o0 ! argument array
382 add %sp, (192 + 128), %sp
384 sethi %hi(prom_cpu_compatible), %g1
385 or %g1, %lo(prom_cpu_compatible), %g1
386 sethi %hi(prom_niagara_prefix), %g7
387 or %g7, %lo(prom_niagara_prefix), %g7
400 89: sethi %hi(prom_cpu_compatible), %g1
401 or %g1, %lo(prom_cpu_compatible), %g1
402 sethi %hi(prom_sparc_prefix), %g7
403 or %g7, %lo(prom_sparc_prefix), %g7
414 sethi %hi(prom_cpu_compatible), %g1
415 or %g1, %lo(prom_cpu_compatible), %g1
425 70: ldub [%g1 + 7], %g2
428 mov SUN4V_CHIP_NIAGARA3, %g4
431 mov SUN4V_CHIP_NIAGARA4, %g4
434 mov SUN4V_CHIP_NIAGARA5, %g4
437 mov SUN4V_CHIP_SPARC_M6, %g4
440 mov SUN4V_CHIP_SPARC_M7, %g4
443 mov SUN4V_CHIP_SPARC_SN, %g4
447 91: sethi %hi(prom_cpu_compatible), %g1
448 or %g1, %lo(prom_cpu_compatible), %g1
452 mov SUN4V_CHIP_NIAGARA1, %g4
455 mov SUN4V_CHIP_NIAGARA2, %g4
459 sethi %hi(prom_cpu_compatible), %g1
460 or %g1, %lo(prom_cpu_compatible), %g1
461 sethi %hi(prom_sparc64x_prefix), %g7
462 or %g7, %lo(prom_sparc64x_prefix), %g7
473 mov SUN4V_CHIP_SPARC64X, %g4
476 mov SUN4V_CHIP_UNKNOWN, %g4
477 5: sethi %hi(sun4v_chip_type), %g2
478 or %g2, %lo(sun4v_chip_type), %g2
482 BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
483 BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
484 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
485 ba,pt %xcc, spitfire_boot
489 /* Preserve OBP chosen DCU and DCR register settings. */
490 ba,pt %xcc, cheetah_generic_boot
494 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
497 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
498 or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
500 or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
501 stxa %g7, [%g0] ASI_DCU_CONTROL_REG
504 cheetah_generic_boot:
505 mov TSB_EXTENSION_P, %g3
506 stxa %g0, [%g3] ASI_DMMU
507 stxa %g0, [%g3] ASI_IMMU
510 mov TSB_EXTENSION_S, %g3
511 stxa %g0, [%g3] ASI_DMMU
514 mov TSB_EXTENSION_N, %g3
515 stxa %g0, [%g3] ASI_DMMU
516 stxa %g0, [%g3] ASI_IMMU
519 ba,a,pt %xcc, jump_to_sun4u_init
522 /* Typically PROM has already enabled both MMU's and both on-chip
523 * caches, but we do it here anyway just to be paranoid.
525 mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
526 stxa %g1, [%g0] ASI_LSU_CONTROL
531 * Make sure we are in privileged mode, have address masking,
532 * using the ordinary globals and have enabled floating
535 * Again, typically PROM has left %pil at 13 or similar, and
536 * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
538 wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
547 BRANCH_IF_SUN4V(g1, sun4v_init)
550 mov PRIMARY_CONTEXT, %g7
551 stxa %g0, [%g7] ASI_DMMU
554 mov SECONDARY_CONTEXT, %g7
555 stxa %g0, [%g7] ASI_DMMU
558 ba,a,pt %xcc, sun4u_continue
562 mov PRIMARY_CONTEXT, %g7
563 stxa %g0, [%g7] ASI_MMU
566 mov SECONDARY_CONTEXT, %g7
567 stxa %g0, [%g7] ASI_MMU
569 ba,a,pt %xcc, niagara_tlb_fixup
572 BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
574 ba,a,pt %xcc, spitfire_tlb_fixup
577 mov 3, %g2 /* Set TLB type to hypervisor. */
578 sethi %hi(tlb_type), %g1
579 stw %g2, [%g1 + %lo(tlb_type)]
581 /* Patch copy/clear ops. */
582 sethi %hi(sun4v_chip_type), %g1
583 lduw [%g1 + %lo(sun4v_chip_type)], %g1
584 cmp %g1, SUN4V_CHIP_NIAGARA1
585 be,pt %xcc, niagara_patch
586 cmp %g1, SUN4V_CHIP_NIAGARA2
587 be,pt %xcc, niagara2_patch
589 cmp %g1, SUN4V_CHIP_NIAGARA3
590 be,pt %xcc, niagara2_patch
592 cmp %g1, SUN4V_CHIP_NIAGARA4
593 be,pt %xcc, niagara4_patch
595 cmp %g1, SUN4V_CHIP_NIAGARA5
596 be,pt %xcc, niagara4_patch
598 cmp %g1, SUN4V_CHIP_SPARC_M6
599 be,pt %xcc, niagara4_patch
601 cmp %g1, SUN4V_CHIP_SPARC_M7
602 be,pt %xcc, niagara4_patch
604 cmp %g1, SUN4V_CHIP_SPARC_SN
605 be,pt %xcc, niagara4_patch
608 call generic_patch_copyops
610 call generic_patch_bzero
612 call generic_patch_pageops
617 call niagara4_patch_copyops
619 call niagara4_patch_bzero
621 call niagara4_patch_pageops
627 call niagara2_patch_copyops
629 call niagara_patch_bzero
631 call niagara_patch_pageops
637 call niagara_patch_copyops
639 call niagara_patch_bzero
641 call niagara_patch_pageops
645 /* Patch TLB/cache ops. */
646 call hypervisor_patch_cachetlbops
649 ba,a,pt %xcc, tlb_fixup_done
652 mov 2, %g2 /* Set TLB type to cheetah+. */
653 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
655 mov 1, %g2 /* Set TLB type to cheetah. */
657 1: sethi %hi(tlb_type), %g1
658 stw %g2, [%g1 + %lo(tlb_type)]
660 /* Patch copy/page operations to cheetah optimized versions. */
661 call cheetah_patch_copyops
663 call cheetah_patch_copy_page
665 call cheetah_patch_cachetlbops
668 ba,a,pt %xcc, tlb_fixup_done
671 /* Set TLB type to spitfire. */
673 sethi %hi(tlb_type), %g1
674 stw %g2, [%g1 + %lo(tlb_type)]
677 sethi %hi(init_thread_union), %g6
678 or %g6, %lo(init_thread_union), %g6
679 ldx [%g6 + TI_TASK], %g4
683 sllx %g1, THREAD_SHIFT, %g1
684 sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
687 /* Set per-cpu pointer initially to zero, this makes
688 * the boot-cpu use the in-kernel-image per-cpu areas
689 * before setup_per_cpu_area() is invoked.
697 sethi %hi(__bss_start), %o0
698 or %o0, %lo(__bss_start), %o0
700 or %o1, %lo(_end), %o1
705 mov %l7, %o0 ! OpenPROM cif handler
707 /* To create a one-register-window buffer between the kernel's
708 * initial stack and the last stack frame we use from the firmware,
709 * do the rest of the boot from a C helper function.
711 call start_early_boot
717 /* This is meant to allow the sharing of this code between
718 * boot processor invocation (via setup_tba() below) and
719 * secondary processor startup (via trampoline.S). The
720 * former does use this code, the latter does not yet due
721 * to some complexities. That should be fixed up at some
724 * There used to be enormous complexity wrt. transferring
725 * over from the firmware's trap table to the Linux kernel's.
726 * For example, there was a chicken & egg problem wrt. building
727 * the OBP page tables, yet needing to be on the Linux kernel
728 * trap table (to translate PAGE_OFFSET addresses) in order to
731 * We now handle OBP tlb misses differently, via linear lookups
732 * into the prom_trans[] array. So that specific problem no
733 * longer exists. Yet, unfortunately there are still some issues
734 * preventing trampoline.S from using this code... ho hum.
736 .globl setup_trap_table
740 /* Force interrupts to be disabled. */
742 andn %l0, PSTATE_IE, %o1
743 wrpr %o1, 0x0, %pstate
745 wrpr %g0, PIL_NORMAL_MAX, %pil
747 /* Make the firmware call to jump over to the Linux trap table. */
748 sethi %hi(is_sun4v), %o0
749 lduw [%o0 + %lo(is_sun4v)], %o0
753 TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
754 add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
755 stxa %g2, [%g0] ASI_SCRATCHPAD
757 /* Compute physical address:
759 * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
761 sethi %hi(KERNBASE), %g3
763 sethi %hi(kern_base), %g3
764 ldx [%g3 + %lo(kern_base)], %g3
766 sethi %hi(sparc64_ttable_tl0), %o0
768 set prom_set_trap_table_name, %g2
769 stx %g2, [%sp + 2047 + 128 + 0x00]
771 stx %g2, [%sp + 2047 + 128 + 0x08]
773 stx %g2, [%sp + 2047 + 128 + 0x10]
774 stx %o0, [%sp + 2047 + 128 + 0x18]
775 stx %o1, [%sp + 2047 + 128 + 0x20]
776 sethi %hi(p1275buf), %g2
777 or %g2, %lo(p1275buf), %g2
778 ldx [%g2 + 0x08], %o1
780 add %sp, (2047 + 128), %o0
784 1: sethi %hi(sparc64_ttable_tl0), %o0
785 set prom_set_trap_table_name, %g2
786 stx %g2, [%sp + 2047 + 128 + 0x00]
788 stx %g2, [%sp + 2047 + 128 + 0x08]
790 stx %g2, [%sp + 2047 + 128 + 0x10]
791 stx %o0, [%sp + 2047 + 128 + 0x18]
792 sethi %hi(p1275buf), %g2
793 or %g2, %lo(p1275buf), %g2
794 ldx [%g2 + 0x08], %o1
796 add %sp, (2047 + 128), %o0
798 /* Start using proper page size encodings in ctx register. */
799 2: sethi %hi(sparc64_kern_pri_context), %g3
800 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
802 mov PRIMARY_CONTEXT, %g1
804 661: stxa %g2, [%g1] ASI_DMMU
805 .section .sun4v_1insn_patch, "ax"
807 stxa %g2, [%g1] ASI_MMU
812 BRANCH_IF_SUN4V(o2, 1f)
814 /* Kill PROM timer */
815 sethi %hi(0x80000000), %o2
817 wr %o2, 0, %tick_cmpr
819 BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
823 /* Disable STICK_INT interrupts. */
825 sethi %hi(0x80000000), %o2
830 wrpr %g0, %g0, %wstate
832 call init_irqwork_curcpu
835 /* Now we can restore interrupt state. */
846 /* The boot processor is the only cpu which invokes this
847 * routine, the other cpus set things up via trampoline.S.
848 * So save the OBP trap table address here.
851 sethi %hi(prom_tba), %o1
852 or %o1, %lo(prom_tba), %o1
855 call setup_trap_table
862 #include "etrap_64.S"
863 #include "rtrap_64.S"
864 #include "winfixup.S"
865 #include "fpu_traps.S"
867 #include "getsetcc.S"
869 #include "spiterrs.S"
871 #include "misctrap.S"
872 #include "syscalls.S"
875 #include "sun4v_tlb_miss.S"
876 #include "sun4v_ivec.S"
881 * The following skip makes sure the trap table in ttable.S is aligned
882 * on a 32K boundary as required by the v9 specs for TBA register.
884 * We align to a 32K boundary, then we have the 32K kernel TSB,
885 * the 64K kernel 4MB TSB, and then the 32K aligned trap table.
888 .skip 0x4000 + _start - 1b
896 .globl swapper_4m_tsb
902 /* Some care needs to be exercised if you try to move the
903 * location of the trap table relative to other things. For
904 * one thing there are br* instructions in some of the
905 * trap table entires which branch back to code in ktlb.S
906 * Those instructions can only handle a signed 16-bit
909 * There is a binutils bug (bugzilla #4558) which causes
910 * the relocation overflow checks for such instructions to
911 * not be done correctly. So bintuils will not notice the
912 * error and will instead write junk into the relocation and
913 * you'll have an unbootable kernel.
915 #include "ttable_64.S"
919 #include "systbls_64.S"
923 .globl prom_tba, tlb_type
925 tlb_type: .word 0 /* Must NOT end up in BSS */
926 EXPORT_SYMBOL(tlb_type)
927 .section ".fixup",#alloc,#execinstr
932 ENDPROC(__retl_efault)