1 /* pci.c: UltraSparc PCI controller support.
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
11 #include <linux/export.h>
12 #include <linux/kernel.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/capability.h>
16 #include <linux/errno.h>
17 #include <linux/pci.h>
18 #include <linux/msi.h>
19 #include <linux/irq.h>
20 #include <linux/init.h>
22 #include <linux/of_device.h>
24 #include <asm/uaccess.h>
25 #include <asm/pgtable.h>
32 /* List of all PCI controllers found in the system. */
33 struct pci_pbm_info *pci_pbm_root = NULL;
35 /* Each PBM found gets a unique index. */
38 volatile int pci_poke_in_progress;
39 volatile int pci_poke_cpu = -1;
40 volatile int pci_poke_faulted;
42 static DEFINE_SPINLOCK(pci_poke_lock);
44 void pci_config_read8(u8 *addr, u8 *ret)
49 spin_lock_irqsave(&pci_poke_lock, flags);
50 pci_poke_cpu = smp_processor_id();
51 pci_poke_in_progress = 1;
53 __asm__ __volatile__("membar #Sync\n\t"
54 "lduba [%1] %2, %0\n\t"
57 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
59 pci_poke_in_progress = 0;
61 if (!pci_poke_faulted)
63 spin_unlock_irqrestore(&pci_poke_lock, flags);
66 void pci_config_read16(u16 *addr, u16 *ret)
71 spin_lock_irqsave(&pci_poke_lock, flags);
72 pci_poke_cpu = smp_processor_id();
73 pci_poke_in_progress = 1;
75 __asm__ __volatile__("membar #Sync\n\t"
76 "lduha [%1] %2, %0\n\t"
79 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
81 pci_poke_in_progress = 0;
83 if (!pci_poke_faulted)
85 spin_unlock_irqrestore(&pci_poke_lock, flags);
88 void pci_config_read32(u32 *addr, u32 *ret)
93 spin_lock_irqsave(&pci_poke_lock, flags);
94 pci_poke_cpu = smp_processor_id();
95 pci_poke_in_progress = 1;
97 __asm__ __volatile__("membar #Sync\n\t"
98 "lduwa [%1] %2, %0\n\t"
101 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
103 pci_poke_in_progress = 0;
105 if (!pci_poke_faulted)
107 spin_unlock_irqrestore(&pci_poke_lock, flags);
110 void pci_config_write8(u8 *addr, u8 val)
114 spin_lock_irqsave(&pci_poke_lock, flags);
115 pci_poke_cpu = smp_processor_id();
116 pci_poke_in_progress = 1;
117 pci_poke_faulted = 0;
118 __asm__ __volatile__("membar #Sync\n\t"
119 "stba %0, [%1] %2\n\t"
122 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
124 pci_poke_in_progress = 0;
126 spin_unlock_irqrestore(&pci_poke_lock, flags);
129 void pci_config_write16(u16 *addr, u16 val)
133 spin_lock_irqsave(&pci_poke_lock, flags);
134 pci_poke_cpu = smp_processor_id();
135 pci_poke_in_progress = 1;
136 pci_poke_faulted = 0;
137 __asm__ __volatile__("membar #Sync\n\t"
138 "stha %0, [%1] %2\n\t"
141 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
143 pci_poke_in_progress = 0;
145 spin_unlock_irqrestore(&pci_poke_lock, flags);
148 void pci_config_write32(u32 *addr, u32 val)
152 spin_lock_irqsave(&pci_poke_lock, flags);
153 pci_poke_cpu = smp_processor_id();
154 pci_poke_in_progress = 1;
155 pci_poke_faulted = 0;
156 __asm__ __volatile__("membar #Sync\n\t"
157 "stwa %0, [%1] %2\n\t"
160 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
162 pci_poke_in_progress = 0;
164 spin_unlock_irqrestore(&pci_poke_lock, flags);
167 static int ofpci_verbose;
169 static int __init ofpci_debug(char *str)
173 get_option(&str, &val);
179 __setup("ofpci_debug=", ofpci_debug);
181 static unsigned long pci_parse_of_flags(u32 addr0)
183 unsigned long flags = 0;
185 if (addr0 & 0x02000000) {
186 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
187 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
188 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
189 if (addr0 & 0x40000000)
190 flags |= IORESOURCE_PREFETCH
191 | PCI_BASE_ADDRESS_MEM_PREFETCH;
192 } else if (addr0 & 0x01000000)
193 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
197 /* The of_device layer has translated all of the assigned-address properties
198 * into physical address resources, we only have to figure out the register
201 static void pci_parse_of_addrs(struct platform_device *op,
202 struct device_node *node,
205 struct resource *op_res;
209 addrs = of_get_property(node, "assigned-addresses", &proplen);
213 printk(" parse addresses (%d bytes) @ %p\n",
215 op_res = &op->resource[0];
216 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
217 struct resource *res;
221 flags = pci_parse_of_flags(addrs[0]);
226 printk(" start: %llx, end: %llx, i: %x\n",
227 op_res->start, op_res->end, i);
229 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
230 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
231 } else if (i == dev->rom_base_reg) {
232 res = &dev->resource[PCI_ROM_RESOURCE];
233 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE
234 | IORESOURCE_SIZEALIGN;
236 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
239 res->start = op_res->start;
240 res->end = op_res->end;
242 res->name = pci_name(dev);
246 static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
247 struct device_node *node,
248 struct pci_bus *bus, int devfn)
250 struct dev_archdata *sd;
251 struct pci_slot *slot;
252 struct platform_device *op;
257 dev = pci_alloc_dev(bus);
261 sd = &dev->dev.archdata;
262 sd->iommu = pbm->iommu;
264 sd->host_controller = pbm;
265 sd->op = op = of_find_device_by_node(node);
266 sd->numa_node = pbm->numa_node;
268 sd = &op->dev.archdata;
269 sd->iommu = pbm->iommu;
271 sd->numa_node = pbm->numa_node;
273 if (!strcmp(node->name, "ebus"))
274 of_propagate_archdata(op);
276 type = of_get_property(node, "device_type", NULL);
281 printk(" create device, devfn: %x, type: %s\n",
285 dev->dev.parent = bus->bridge;
286 dev->dev.bus = &pci_bus_type;
287 dev->dev.of_node = of_node_get(node);
289 dev->multifunction = 0; /* maybe a lie? */
290 set_pcie_port_type(dev);
292 list_for_each_entry(slot, &dev->bus->slots, list)
293 if (PCI_SLOT(dev->devfn) == slot->number)
296 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
297 dev->device = of_getintprop_default(node, "device-id", 0xffff);
298 dev->subsystem_vendor =
299 of_getintprop_default(node, "subsystem-vendor-id", 0);
300 dev->subsystem_device =
301 of_getintprop_default(node, "subsystem-id", 0);
303 dev->cfg_size = pci_cfg_space_size(dev);
305 /* We can't actually use the firmware value, we have
306 * to read what is in the register right now. One
307 * reason is that in the case of IDE interfaces the
308 * firmware can sample the value before the the IDE
309 * interface is programmed into native mode.
311 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
312 dev->class = class >> 8;
313 dev->revision = class & 0xff;
315 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
316 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
319 printk(" class: 0x%x device name: %s\n",
320 dev->class, pci_name(dev));
322 /* I have seen IDE devices which will not respond to
323 * the bmdma simplex check reads if bus mastering is
326 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
329 dev->current_state = PCI_UNKNOWN; /* unknown power state */
330 dev->error_state = pci_channel_io_normal;
331 dev->dma_mask = 0xffffffff;
333 if (!strcmp(node->name, "pci")) {
334 /* a PCI-PCI bridge */
335 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
336 dev->rom_base_reg = PCI_ROM_ADDRESS1;
337 } else if (!strcmp(type, "cardbus")) {
338 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
340 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
341 dev->rom_base_reg = PCI_ROM_ADDRESS;
343 dev->irq = sd->op->archdata.irqs[0];
344 if (dev->irq == 0xffffffff)
345 dev->irq = PCI_IRQ_NONE;
348 pci_parse_of_addrs(sd->op, node, dev);
351 printk(" adding to system ...\n");
353 pci_device_add(dev, bus);
358 static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
360 u32 idx, first, last;
364 for (idx = 0; idx < 8; idx++) {
365 if ((map & (1 << idx)) != 0) {
377 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
378 * a proper 'ranges' property.
380 static void apb_fake_ranges(struct pci_dev *dev,
382 struct pci_pbm_info *pbm)
384 struct pci_bus_region region;
385 struct resource *res;
389 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
390 apb_calc_first_last(map, &first, &last);
391 res = bus->resource[0];
392 res->flags = IORESOURCE_IO;
393 region.start = (first << 21);
394 region.end = (last << 21) + ((1 << 21) - 1);
395 pcibios_bus_to_resource(dev->bus, res, ®ion);
397 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
398 apb_calc_first_last(map, &first, &last);
399 res = bus->resource[1];
400 res->flags = IORESOURCE_MEM;
401 region.start = (first << 29);
402 region.end = (last << 29) + ((1 << 29) - 1);
403 pcibios_bus_to_resource(dev->bus, res, ®ion);
406 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
407 struct device_node *node,
408 struct pci_bus *bus);
410 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
412 static void of_scan_pci_bridge(struct pci_pbm_info *pbm,
413 struct device_node *node,
417 const u32 *busrange, *ranges;
419 struct pci_bus_region region;
420 struct resource *res;
425 printk("of_scan_pci_bridge(%s)\n", node->full_name);
427 /* parse bus-range property */
428 busrange = of_get_property(node, "bus-range", &len);
429 if (busrange == NULL || len != 8) {
430 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
434 ranges = of_get_property(node, "ranges", &len);
436 if (ranges == NULL) {
437 const char *model = of_get_property(node, "model", NULL);
438 if (model && !strcmp(model, "SUNW,simba"))
442 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
444 printk(KERN_ERR "Failed to create pci bus for %s\n",
449 bus->primary = dev->bus->number;
450 pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
453 /* parse ranges property, or cook one up by hand for Simba */
454 /* PCI #address-cells == 3 and #size-cells == 2 always */
455 res = &dev->resource[PCI_BRIDGE_RESOURCES];
456 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
458 bus->resource[i] = res;
462 apb_fake_ranges(dev, bus, pbm);
464 } else if (ranges == NULL) {
465 pci_read_bridge_bases(bus);
469 for (; len >= 32; len -= 32, ranges += 8) {
470 flags = pci_parse_of_flags(ranges[0]);
471 size = GET_64BIT(ranges, 6);
472 if (flags == 0 || size == 0)
474 if (flags & IORESOURCE_IO) {
475 res = bus->resource[0];
477 printk(KERN_ERR "PCI: ignoring extra I/O range"
478 " for bridge %s\n", node->full_name);
482 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
483 printk(KERN_ERR "PCI: too many memory ranges"
484 " for bridge %s\n", node->full_name);
487 res = bus->resource[i];
492 region.start = GET_64BIT(ranges, 1);
493 region.end = region.start + size - 1;
494 pcibios_bus_to_resource(dev->bus, res, ®ion);
497 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
500 printk(" bus name: %s\n", bus->name);
502 pci_of_scan_bus(pbm, node, bus);
505 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
506 struct device_node *node,
509 struct device_node *child;
511 int reglen, devfn, prev_devfn;
515 printk("PCI: scan_bus[%s] bus no %d\n",
516 node->full_name, bus->number);
520 while ((child = of_get_next_child(node, child)) != NULL) {
522 printk(" * %s\n", child->full_name);
523 reg = of_get_property(child, "reg", ®len);
524 if (reg == NULL || reglen < 20)
527 devfn = (reg[0] >> 8) & 0xff;
529 /* This is a workaround for some device trees
530 * which list PCI devices twice. On the V100
531 * for example, device number 3 is listed twice.
532 * Once as "pm" and once again as "lomp".
534 if (devfn == prev_devfn)
538 /* create a new pci_dev for this device */
539 dev = of_create_pci_dev(pbm, child, bus, devfn);
543 printk("PCI: dev header type: %x\n",
546 if (pci_is_bridge(dev))
547 of_scan_pci_bridge(pbm, child, dev);
552 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
554 struct pci_dev *pdev;
555 struct device_node *dp;
557 pdev = to_pci_dev(dev);
558 dp = pdev->dev.of_node;
560 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
563 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
565 static void pci_bus_register_of_sysfs(struct pci_bus *bus)
568 struct pci_bus *child_bus;
571 list_for_each_entry(dev, &bus->devices, bus_list) {
572 /* we don't really care if we can create this file or
573 * not, but we need to assign the result of the call
574 * or the world will fall under alien invasion and
575 * everybody will be frozen on a spaceship ready to be
576 * eaten on alpha centauri by some green and jelly
579 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
582 list_for_each_entry(child_bus, &bus->children, node)
583 pci_bus_register_of_sysfs(child_bus);
586 struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
587 struct device *parent)
589 LIST_HEAD(resources);
590 struct device_node *node = pbm->op->dev.of_node;
593 printk("PCI: Scanning PBM %s\n", node->full_name);
595 pci_add_resource_offset(&resources, &pbm->io_space,
596 pbm->io_space.start);
597 pci_add_resource_offset(&resources, &pbm->mem_space,
598 pbm->mem_space.start);
599 pbm->busn.start = pbm->pci_first_busno;
600 pbm->busn.end = pbm->pci_last_busno;
601 pbm->busn.flags = IORESOURCE_BUS;
602 pci_add_resource(&resources, &pbm->busn);
603 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
606 printk(KERN_ERR "Failed to create bus for %s\n",
608 pci_free_resource_list(&resources);
612 pci_of_scan_bus(pbm, node, bus);
613 pci_bus_add_devices(bus);
614 pci_bus_register_of_sysfs(bus);
619 void pcibios_fixup_bus(struct pci_bus *pbus)
623 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
624 resource_size_t size, resource_size_t align)
629 int pcibios_enable_device(struct pci_dev *dev, int mask)
634 pci_read_config_word(dev, PCI_COMMAND, &cmd);
637 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
638 struct resource *res = &dev->resource[i];
640 /* Only set up the requested stuff */
641 if (!(mask & (1<<i)))
644 if (res->flags & IORESOURCE_IO)
645 cmd |= PCI_COMMAND_IO;
646 if (res->flags & IORESOURCE_MEM)
647 cmd |= PCI_COMMAND_MEMORY;
651 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
653 /* Enable the appropriate bits in the PCI command register. */
654 pci_write_config_word(dev, PCI_COMMAND, cmd);
659 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
661 /* If the user uses a host-bridge as the PCI device, he may use
662 * this to perform a raw mmap() of the I/O or MEM space behind
665 * This can be useful for execution of x86 PCI bios initialization code
666 * on a PCI card, like the xfree86 int10 stuff does.
668 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
669 enum pci_mmap_state mmap_state)
671 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
672 unsigned long space_size, user_offset, user_size;
674 if (mmap_state == pci_mmap_io) {
675 space_size = resource_size(&pbm->io_space);
677 space_size = resource_size(&pbm->mem_space);
680 /* Make sure the request is in range. */
681 user_offset = vma->vm_pgoff << PAGE_SHIFT;
682 user_size = vma->vm_end - vma->vm_start;
684 if (user_offset >= space_size ||
685 (user_offset + user_size) > space_size)
688 if (mmap_state == pci_mmap_io) {
689 vma->vm_pgoff = (pbm->io_space.start +
690 user_offset) >> PAGE_SHIFT;
692 vma->vm_pgoff = (pbm->mem_space.start +
693 user_offset) >> PAGE_SHIFT;
699 /* Adjust vm_pgoff of VMA such that it is the physical page offset
700 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
702 * Basically, the user finds the base address for his device which he wishes
703 * to mmap. They read the 32-bit value from the config space base register,
704 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
705 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
707 * Returns negative error code on failure, zero on success.
709 static int __pci_mmap_make_offset(struct pci_dev *pdev,
710 struct vm_area_struct *vma,
711 enum pci_mmap_state mmap_state)
713 unsigned long user_paddr, user_size;
716 /* First compute the physical address in vma->vm_pgoff,
717 * making sure the user offset is within range in the
718 * appropriate PCI space.
720 err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
724 /* If this is a mapping on a host bridge, any address
727 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
730 /* Otherwise make sure it's in the range for one of the
731 * device's resources.
733 user_paddr = vma->vm_pgoff << PAGE_SHIFT;
734 user_size = vma->vm_end - vma->vm_start;
736 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
737 struct resource *rp = &pdev->resource[i];
738 resource_size_t aligned_end;
745 if (i == PCI_ROM_RESOURCE) {
746 if (mmap_state != pci_mmap_mem)
749 if ((mmap_state == pci_mmap_io &&
750 (rp->flags & IORESOURCE_IO) == 0) ||
751 (mmap_state == pci_mmap_mem &&
752 (rp->flags & IORESOURCE_MEM) == 0))
756 /* Align the resource end to the next page address.
757 * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1),
758 * because actually we need the address of the next byte
761 aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK;
763 if ((rp->start <= user_paddr) &&
764 (user_paddr + user_size) <= aligned_end)
768 if (i > PCI_ROM_RESOURCE)
774 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
777 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
778 enum pci_mmap_state mmap_state)
780 /* Our io_remap_pfn_range takes care of this, do nothing. */
783 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
784 * for this architecture. The region in the process to map is described by vm_start
785 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
786 * The pci device structure is provided so that architectures may make mapping
787 * decisions on a per-device or per-bus basis.
789 * Returns a negative error code on failure, zero on success.
791 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
792 enum pci_mmap_state mmap_state,
797 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
801 __pci_mmap_set_pgprot(dev, vma, mmap_state);
803 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
804 ret = io_remap_pfn_range(vma, vma->vm_start,
806 vma->vm_end - vma->vm_start,
815 int pcibus_to_node(struct pci_bus *pbus)
817 struct pci_pbm_info *pbm = pbus->sysdata;
819 return pbm->numa_node;
821 EXPORT_SYMBOL(pcibus_to_node);
824 /* Return the domain number for this pci bus */
826 int pci_domain_nr(struct pci_bus *pbus)
828 struct pci_pbm_info *pbm = pbus->sysdata;
839 EXPORT_SYMBOL(pci_domain_nr);
841 #ifdef CONFIG_PCI_MSI
842 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
844 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
847 if (!pbm->setup_msi_irq)
850 return pbm->setup_msi_irq(&irq, pdev, desc);
853 void arch_teardown_msi_irq(unsigned int irq)
855 struct msi_desc *entry = irq_get_msi_desc(irq);
856 struct pci_dev *pdev = entry->dev;
857 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
859 if (pbm->teardown_msi_irq)
860 pbm->teardown_msi_irq(irq, pdev);
862 #endif /* !(CONFIG_PCI_MSI) */
864 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
866 struct pci_dev *ali_isa_bridge;
869 /* ALI sound chips generate 31-bits of DMA, a special register
870 * determines what bit 31 is emitted as.
872 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
873 PCI_DEVICE_ID_AL_M1533,
876 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
881 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
882 pci_dev_put(ali_isa_bridge);
885 int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask)
890 dma_addr_mask = 0xffffffff;
892 struct iommu *iommu = pdev->dev.archdata.iommu;
894 dma_addr_mask = iommu->dma_addr_mask;
896 if (pdev->vendor == PCI_VENDOR_ID_AL &&
897 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
898 device_mask == 0x7fffffff) {
899 ali_sound_dma_hack(pdev,
900 (dma_addr_mask & 0x80000000) != 0);
905 if (device_mask >= (1UL << 32UL))
908 return (device_mask & dma_addr_mask) == dma_addr_mask;
911 void pci_resource_to_user(const struct pci_dev *pdev, int bar,
912 const struct resource *rp, resource_size_t *start,
913 resource_size_t *end)
915 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
916 unsigned long offset;
918 if (rp->flags & IORESOURCE_IO)
919 offset = pbm->io_space.start;
921 offset = pbm->mem_space.start;
923 *start = rp->start - offset;
924 *end = rp->end - offset;
927 void pcibios_set_master(struct pci_dev *dev)
929 /* No special bus mastering setup handling */
932 static int __init pcibios_init(void)
934 pci_dfl_cache_line_size = 64 >> 2;
937 subsys_initcall(pcibios_init);
940 static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus)
942 const struct pci_slot_names {
950 prop = of_get_property(node, "slot-names", &len);
954 mask = prop->slot_mask;
958 printk("PCI: Making slots for [%s] mask[0x%02x]\n",
959 node->full_name, mask);
963 struct pci_slot *pci_slot;
964 u32 this_bit = 1 << i;
966 if (!(mask & this_bit)) {
972 printk("PCI: Making slot [%s]\n", sp);
974 pci_slot = pci_create_slot(bus, i, sp, NULL);
975 if (IS_ERR(pci_slot))
976 printk(KERN_ERR "PCI: pci_create_slot returned %ld\n",
979 sp += strlen(sp) + 1;
985 static int __init of_pci_slot_init(void)
987 struct pci_bus *pbus = NULL;
989 while ((pbus = pci_find_next_bus(pbus)) != NULL) {
990 struct device_node *node;
993 /* PCI->PCI bridge */
994 node = pbus->self->dev.of_node;
996 struct pci_pbm_info *pbm = pbus->sysdata;
998 /* Host PCI controller */
999 node = pbm->op->dev.of_node;
1002 pci_bus_slot_names(node, pbus);
1007 device_initcall(of_pci_slot_init);