1 /* pci_sun4v.c: SUN4V specific PCI controller support.
3 * Copyright (C) 2006, 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/kernel.h>
7 #include <linux/types.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/percpu.h>
13 #include <linux/irq.h>
14 #include <linux/msi.h>
15 #include <linux/export.h>
16 #include <linux/log2.h>
17 #include <linux/of_device.h>
18 #include <linux/iommu-common.h>
20 #include <asm/iommu.h>
22 #include <asm/hypervisor.h>
26 #include "iommu_common.h"
28 #include "pci_sun4v.h"
30 #define DRIVER_NAME "pci_sun4v"
31 #define PFX DRIVER_NAME ": "
33 static unsigned long vpci_major;
34 static unsigned long vpci_minor;
41 /* Ordered from largest major to lowest */
42 static struct vpci_version vpci_versions[] = {
43 { .major = 2, .minor = 0 },
44 { .major = 1, .minor = 1 },
47 static unsigned long vatu_major = 1;
48 static unsigned long vatu_minor = 1;
50 #define PGLIST_NENTS (PAGE_SIZE / sizeof(u64))
53 struct device *dev; /* Device mapping is for. */
54 unsigned long prot; /* IOMMU page protections */
55 unsigned long entry; /* Index into IOTSB. */
56 u64 *pglist; /* List of physical pages */
57 unsigned long npages; /* Number of pages in list. */
60 static DEFINE_PER_CPU(struct iommu_batch, iommu_batch);
61 static int iommu_batch_initialized;
63 /* Interrupts must be disabled. */
64 static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry)
66 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
74 /* Interrupts must be disabled. */
75 static long iommu_batch_flush(struct iommu_batch *p, u64 mask)
77 struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
78 u64 *pglist = p->pglist;
80 unsigned long devhandle = pbm->devhandle;
81 unsigned long prot = p->prot;
82 unsigned long entry = p->entry;
83 unsigned long npages = p->npages;
84 unsigned long iotsb_num;
88 /* VPCI maj=1, min=[0,1] only supports read and write */
90 prot &= (HV_PCI_MAP_ATTR_READ | HV_PCI_MAP_ATTR_WRITE);
93 if (mask <= DMA_BIT_MASK(32)) {
94 num = pci_sun4v_iommu_map(devhandle,
95 HV_PCI_TSBID(0, entry),
99 if (unlikely(num < 0)) {
100 pr_err_ratelimited("%s: IOMMU map of [%08lx:%08llx:%lx:%lx:%lx] failed with status %ld\n",
103 HV_PCI_TSBID(0, entry),
104 npages, prot, __pa(pglist),
109 index_count = HV_PCI_IOTSB_INDEX_COUNT(npages, entry),
110 iotsb_num = pbm->iommu->atu->iotsb->iotsb_num;
111 ret = pci_sun4v_iotsb_map(devhandle,
117 if (unlikely(ret != HV_EOK)) {
118 pr_err_ratelimited("%s: ATU map of [%08lx:%lx:%llx:%lx:%lx] failed with status %ld\n",
120 devhandle, iotsb_num,
137 static inline void iommu_batch_new_entry(unsigned long entry, u64 mask)
139 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
141 if (p->entry + p->npages == entry)
143 if (p->entry != ~0UL)
144 iommu_batch_flush(p, mask);
148 /* Interrupts must be disabled. */
149 static inline long iommu_batch_add(u64 phys_page, u64 mask)
151 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
153 BUG_ON(p->npages >= PGLIST_NENTS);
155 p->pglist[p->npages++] = phys_page;
156 if (p->npages == PGLIST_NENTS)
157 return iommu_batch_flush(p, mask);
162 /* Interrupts must be disabled. */
163 static inline long iommu_batch_end(u64 mask)
165 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
167 BUG_ON(p->npages >= PGLIST_NENTS);
169 return iommu_batch_flush(p, mask);
172 static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
173 dma_addr_t *dma_addrp, gfp_t gfp,
177 unsigned long flags, order, first_page, npages, n;
178 unsigned long prot = 0;
181 struct iommu_map_table *tbl;
187 size = IO_PAGE_ALIGN(size);
188 order = get_order(size);
189 if (unlikely(order >= MAX_ORDER))
192 npages = size >> IO_PAGE_SHIFT;
194 if (attrs & DMA_ATTR_WEAK_ORDERING)
195 prot = HV_PCI_MAP_ATTR_RELAXED_ORDER;
197 nid = dev->archdata.numa_node;
198 page = alloc_pages_node(nid, gfp, order);
202 first_page = (unsigned long) page_address(page);
203 memset((char *)first_page, 0, PAGE_SIZE << order);
205 iommu = dev->archdata.iommu;
208 mask = dev->coherent_dma_mask;
209 if (mask <= DMA_BIT_MASK(32))
214 entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
215 (unsigned long)(-1), 0);
217 if (unlikely(entry == IOMMU_ERROR_CODE))
218 goto range_alloc_fail;
220 *dma_addrp = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
221 ret = (void *) first_page;
222 first_page = __pa(first_page);
224 local_irq_save(flags);
226 iommu_batch_start(dev,
227 (HV_PCI_MAP_ATTR_READ | prot |
228 HV_PCI_MAP_ATTR_WRITE),
231 for (n = 0; n < npages; n++) {
232 long err = iommu_batch_add(first_page + (n * PAGE_SIZE), mask);
233 if (unlikely(err < 0L))
237 if (unlikely(iommu_batch_end(mask) < 0L))
240 local_irq_restore(flags);
245 local_irq_restore(flags);
246 iommu_tbl_range_free(tbl, *dma_addrp, npages, IOMMU_ERROR_CODE);
249 free_pages(first_page, order);
253 unsigned long dma_4v_iotsb_bind(unsigned long devhandle,
254 unsigned long iotsb_num,
255 struct pci_bus *bus_dev)
257 struct pci_dev *pdev;
263 list_for_each_entry(pdev, &bus_dev->devices, bus_list) {
264 if (pdev->subordinate) {
265 /* No need to bind pci bridge */
266 dma_4v_iotsb_bind(devhandle, iotsb_num,
269 bus = bus_dev->number;
270 device = PCI_SLOT(pdev->devfn);
271 fun = PCI_FUNC(pdev->devfn);
272 err = pci_sun4v_iotsb_bind(devhandle, iotsb_num,
273 HV_PCI_DEVICE_BUILD(bus,
277 /* If bind fails for one device it is going to fail
278 * for rest of the devices because we are sharing
279 * IOTSB. So in case of failure simply return with
290 static void dma_4v_iommu_demap(struct device *dev, unsigned long devhandle,
291 dma_addr_t dvma, unsigned long iotsb_num,
292 unsigned long entry, unsigned long npages)
294 unsigned long num, flags;
297 local_irq_save(flags);
299 if (dvma <= DMA_BIT_MASK(32)) {
300 num = pci_sun4v_iommu_demap(devhandle,
301 HV_PCI_TSBID(0, entry),
304 ret = pci_sun4v_iotsb_demap(devhandle, iotsb_num,
305 entry, npages, &num);
306 if (unlikely(ret != HV_EOK)) {
307 pr_err_ratelimited("pci_iotsb_demap() failed with error: %ld\n",
313 } while (npages != 0);
314 local_irq_restore(flags);
317 static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
318 dma_addr_t dvma, unsigned long attrs)
320 struct pci_pbm_info *pbm;
323 struct iommu_map_table *tbl;
324 unsigned long order, npages, entry;
325 unsigned long iotsb_num;
328 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
329 iommu = dev->archdata.iommu;
330 pbm = dev->archdata.host_controller;
332 devhandle = pbm->devhandle;
334 if (dvma <= DMA_BIT_MASK(32)) {
336 iotsb_num = 0; /* we don't care for legacy iommu */
339 iotsb_num = atu->iotsb->iotsb_num;
341 entry = ((dvma - tbl->table_map_base) >> IO_PAGE_SHIFT);
342 dma_4v_iommu_demap(dev, devhandle, dvma, iotsb_num, entry, npages);
343 iommu_tbl_range_free(tbl, dvma, npages, IOMMU_ERROR_CODE);
344 order = get_order(size);
346 free_pages((unsigned long)cpu, order);
349 static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
350 unsigned long offset, size_t sz,
351 enum dma_data_direction direction,
356 struct iommu_map_table *tbl;
358 unsigned long flags, npages, oaddr;
359 unsigned long i, base_paddr;
361 dma_addr_t bus_addr, ret;
364 iommu = dev->archdata.iommu;
367 if (unlikely(direction == DMA_NONE))
370 oaddr = (unsigned long)(page_address(page) + offset);
371 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
372 npages >>= IO_PAGE_SHIFT;
374 mask = *dev->dma_mask;
375 if (mask <= DMA_BIT_MASK(32))
380 entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
381 (unsigned long)(-1), 0);
383 if (unlikely(entry == IOMMU_ERROR_CODE))
386 bus_addr = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
387 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
388 base_paddr = __pa(oaddr & IO_PAGE_MASK);
389 prot = HV_PCI_MAP_ATTR_READ;
390 if (direction != DMA_TO_DEVICE)
391 prot |= HV_PCI_MAP_ATTR_WRITE;
393 if (attrs & DMA_ATTR_WEAK_ORDERING)
394 prot |= HV_PCI_MAP_ATTR_RELAXED_ORDER;
396 local_irq_save(flags);
398 iommu_batch_start(dev, prot, entry);
400 for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
401 long err = iommu_batch_add(base_paddr, mask);
402 if (unlikely(err < 0L))
405 if (unlikely(iommu_batch_end(mask) < 0L))
408 local_irq_restore(flags);
413 if (printk_ratelimit())
415 return DMA_ERROR_CODE;
418 local_irq_restore(flags);
419 iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
420 return DMA_ERROR_CODE;
423 static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
424 size_t sz, enum dma_data_direction direction,
427 struct pci_pbm_info *pbm;
430 struct iommu_map_table *tbl;
431 unsigned long npages;
432 unsigned long iotsb_num;
436 if (unlikely(direction == DMA_NONE)) {
437 if (printk_ratelimit())
442 iommu = dev->archdata.iommu;
443 pbm = dev->archdata.host_controller;
445 devhandle = pbm->devhandle;
447 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
448 npages >>= IO_PAGE_SHIFT;
449 bus_addr &= IO_PAGE_MASK;
451 if (bus_addr <= DMA_BIT_MASK(32)) {
452 iotsb_num = 0; /* we don't care for legacy iommu */
455 iotsb_num = atu->iotsb->iotsb_num;
458 entry = (bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT;
459 dma_4v_iommu_demap(dev, devhandle, bus_addr, iotsb_num, entry, npages);
460 iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
463 static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
464 int nelems, enum dma_data_direction direction,
467 struct scatterlist *s, *outs, *segstart;
468 unsigned long flags, handle, prot;
469 dma_addr_t dma_next = 0, dma_addr;
470 unsigned int max_seg_size;
471 unsigned long seg_boundary_size;
472 int outcount, incount, i;
475 struct iommu_map_table *tbl;
477 unsigned long base_shift;
480 BUG_ON(direction == DMA_NONE);
482 iommu = dev->archdata.iommu;
483 if (nelems == 0 || !iommu)
487 prot = HV_PCI_MAP_ATTR_READ;
488 if (direction != DMA_TO_DEVICE)
489 prot |= HV_PCI_MAP_ATTR_WRITE;
491 if (attrs & DMA_ATTR_WEAK_ORDERING)
492 prot |= HV_PCI_MAP_ATTR_RELAXED_ORDER;
494 outs = s = segstart = &sglist[0];
499 /* Init first segment length for backout at failure */
500 outs->dma_length = 0;
502 local_irq_save(flags);
504 iommu_batch_start(dev, prot, ~0UL);
506 max_seg_size = dma_get_max_seg_size(dev);
507 seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
508 IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
510 mask = *dev->dma_mask;
511 if (mask <= DMA_BIT_MASK(32))
516 base_shift = tbl->table_map_base >> IO_PAGE_SHIFT;
518 for_each_sg(sglist, s, nelems, i) {
519 unsigned long paddr, npages, entry, out_entry = 0, slen;
527 /* Allocate iommu entries for that segment */
528 paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
529 npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
530 entry = iommu_tbl_range_alloc(dev, tbl, npages,
531 &handle, (unsigned long)(-1), 0);
534 if (unlikely(entry == IOMMU_ERROR_CODE)) {
535 pr_err_ratelimited("iommu_alloc failed, iommu %p paddr %lx npages %lx\n",
537 goto iommu_map_failed;
540 iommu_batch_new_entry(entry, mask);
542 /* Convert entry to a dma_addr_t */
543 dma_addr = tbl->table_map_base + (entry << IO_PAGE_SHIFT);
544 dma_addr |= (s->offset & ~IO_PAGE_MASK);
546 /* Insert into HW table */
547 paddr &= IO_PAGE_MASK;
549 err = iommu_batch_add(paddr, mask);
550 if (unlikely(err < 0L))
551 goto iommu_map_failed;
552 paddr += IO_PAGE_SIZE;
555 /* If we are in an open segment, try merging */
557 /* We cannot merge if:
558 * - allocated dma_addr isn't contiguous to previous allocation
560 if ((dma_addr != dma_next) ||
561 (outs->dma_length + s->length > max_seg_size) ||
562 (is_span_boundary(out_entry, base_shift,
563 seg_boundary_size, outs, s))) {
564 /* Can't merge: create a new segment */
567 outs = sg_next(outs);
569 outs->dma_length += s->length;
574 /* This is a new segment, fill entries */
575 outs->dma_address = dma_addr;
576 outs->dma_length = slen;
580 /* Calculate next page pointer for contiguous check */
581 dma_next = dma_addr + slen;
584 err = iommu_batch_end(mask);
586 if (unlikely(err < 0L))
587 goto iommu_map_failed;
589 local_irq_restore(flags);
591 if (outcount < incount) {
592 outs = sg_next(outs);
593 outs->dma_address = DMA_ERROR_CODE;
594 outs->dma_length = 0;
600 for_each_sg(sglist, s, nelems, i) {
601 if (s->dma_length != 0) {
602 unsigned long vaddr, npages;
604 vaddr = s->dma_address & IO_PAGE_MASK;
605 npages = iommu_num_pages(s->dma_address, s->dma_length,
607 iommu_tbl_range_free(tbl, vaddr, npages,
610 s->dma_address = DMA_ERROR_CODE;
616 local_irq_restore(flags);
621 static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
622 int nelems, enum dma_data_direction direction,
625 struct pci_pbm_info *pbm;
626 struct scatterlist *sg;
629 unsigned long flags, entry;
630 unsigned long iotsb_num;
633 BUG_ON(direction == DMA_NONE);
635 iommu = dev->archdata.iommu;
636 pbm = dev->archdata.host_controller;
638 devhandle = pbm->devhandle;
640 local_irq_save(flags);
644 dma_addr_t dma_handle = sg->dma_address;
645 unsigned int len = sg->dma_length;
646 unsigned long npages;
647 struct iommu_map_table *tbl;
648 unsigned long shift = IO_PAGE_SHIFT;
652 npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
654 if (dma_handle <= DMA_BIT_MASK(32)) {
655 iotsb_num = 0; /* we don't care for legacy iommu */
658 iotsb_num = atu->iotsb->iotsb_num;
661 entry = ((dma_handle - tbl->table_map_base) >> shift);
662 dma_4v_iommu_demap(dev, devhandle, dma_handle, iotsb_num,
664 iommu_tbl_range_free(tbl, dma_handle, npages,
669 local_irq_restore(flags);
672 static struct dma_map_ops sun4v_dma_ops = {
673 .alloc = dma_4v_alloc_coherent,
674 .free = dma_4v_free_coherent,
675 .map_page = dma_4v_map_page,
676 .unmap_page = dma_4v_unmap_page,
677 .map_sg = dma_4v_map_sg,
678 .unmap_sg = dma_4v_unmap_sg,
681 static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
683 struct property *prop;
684 struct device_node *dp;
686 dp = pbm->op->dev.of_node;
687 prop = of_find_property(dp, "66mhz-capable", NULL);
688 pbm->is_66mhz_capable = (prop != NULL);
689 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
691 /* XXX register error interrupt handlers XXX */
694 static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
695 struct iommu_map_table *iommu)
697 struct iommu_pool *pool;
698 unsigned long i, pool_nr, cnt = 0;
701 devhandle = pbm->devhandle;
702 for (pool_nr = 0; pool_nr < iommu->nr_pools; pool_nr++) {
703 pool = &(iommu->pools[pool_nr]);
704 for (i = pool->start; i <= pool->end; i++) {
705 unsigned long ret, io_attrs, ra;
707 ret = pci_sun4v_iommu_getmap(devhandle,
711 if (page_in_phys_avail(ra)) {
712 pci_sun4v_iommu_demap(devhandle,
717 __set_bit(i, iommu->map);
725 static int pci_sun4v_atu_alloc_iotsb(struct pci_pbm_info *pbm)
727 struct atu *atu = pbm->iommu->atu;
728 struct atu_iotsb *iotsb;
735 iotsb = kzalloc(sizeof(*iotsb), GFP_KERNEL);
742 /* calculate size of IOTSB */
743 table_size = (atu->size / IO_PAGE_SIZE) * 8;
744 order = get_order(table_size);
745 table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
750 iotsb->table = table;
751 iotsb->ra = __pa(table);
752 iotsb->dvma_size = atu->size;
753 iotsb->dvma_base = atu->base;
754 iotsb->table_size = table_size;
755 iotsb->page_size = IO_PAGE_SIZE;
757 /* configure and register IOTSB with HV */
758 err = pci_sun4v_iotsb_conf(pbm->devhandle,
765 pr_err(PFX "pci_iotsb_conf failed error: %ld\n", err);
766 goto iotsb_conf_failed;
768 iotsb->iotsb_num = iotsb_num;
770 err = dma_4v_iotsb_bind(pbm->devhandle, iotsb_num, pbm->pci_bus);
772 pr_err(PFX "pci_iotsb_bind failed error: %ld\n", err);
773 goto iotsb_conf_failed;
779 free_pages((unsigned long)table, order);
786 static int pci_sun4v_atu_init(struct pci_pbm_info *pbm)
788 struct atu *atu = pbm->iommu->atu;
791 u64 map_size, num_iotte;
793 const u32 *page_size;
796 ranges = of_get_property(pbm->op->dev.of_node, "iommu-address-ranges",
799 pr_err(PFX "No iommu-address-ranges\n");
803 page_size = of_get_property(pbm->op->dev.of_node, "iommu-pagesizes",
806 pr_err(PFX "No iommu-pagesizes\n");
810 /* There are 4 iommu-address-ranges supported. Each range is pair of
811 * {base, size}. The ranges[0] and ranges[1] are 32bit address space
812 * while ranges[2] and ranges[3] are 64bit space. We want to use 64bit
813 * address ranges to support 64bit addressing. Because 'size' for
814 * address ranges[2] and ranges[3] are same we can select either of
815 * ranges[2] or ranges[3] for mapping. However due to 'size' is too
816 * large for OS to allocate IOTSB we are using fix size 32G
817 * (ATU_64_SPACE_SIZE) which is more than enough for all PCIe devices
820 atu->ranges = (struct atu_ranges *)ranges;
821 atu->base = atu->ranges[3].base;
822 atu->size = ATU_64_SPACE_SIZE;
825 err = pci_sun4v_atu_alloc_iotsb(pbm);
827 pr_err(PFX "Error creating ATU IOTSB\n");
831 /* Create ATU iommu map.
832 * One bit represents one iotte in IOTSB table.
834 dma_mask = (roundup_pow_of_two(atu->size) - 1UL);
835 num_iotte = atu->size / IO_PAGE_SIZE;
836 map_size = num_iotte / 8;
837 atu->tbl.table_map_base = atu->base;
838 atu->dma_addr_mask = dma_mask;
839 atu->tbl.map = kzalloc(map_size, GFP_KERNEL);
843 iommu_tbl_pool_init(&atu->tbl, num_iotte, IO_PAGE_SHIFT,
844 NULL, false /* no large_pool */,
845 0 /* default npools */,
846 false /* want span boundary checking */);
851 static int pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
853 static const u32 vdma_default[] = { 0x80000000, 0x80000000 };
854 struct iommu *iommu = pbm->iommu;
855 unsigned long num_tsb_entries, sz;
856 u32 dma_mask, dma_offset;
859 vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
863 if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
864 printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n",
869 dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
870 num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
872 dma_offset = vdma[0];
874 /* Setup initial software IOMMU state. */
875 spin_lock_init(&iommu->lock);
876 iommu->ctx_lowest_free = 1;
877 iommu->tbl.table_map_base = dma_offset;
878 iommu->dma_addr_mask = dma_mask;
880 /* Allocate and initialize the free area map. */
881 sz = (num_tsb_entries + 7) / 8;
882 sz = (sz + 7UL) & ~7UL;
883 iommu->tbl.map = kzalloc(sz, GFP_KERNEL);
884 if (!iommu->tbl.map) {
885 printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n");
888 iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT,
889 NULL, false /* no large_pool */,
890 0 /* default npools */,
891 false /* want span boundary checking */);
892 sz = probe_existing_entries(pbm, &iommu->tbl);
894 printk("%s: Imported %lu TSB entries from OBP\n",
900 #ifdef CONFIG_PCI_MSI
901 struct pci_sun4v_msiq_entry {
903 #define MSIQ_VERSION_MASK 0xffffffff00000000UL
904 #define MSIQ_VERSION_SHIFT 32
905 #define MSIQ_TYPE_MASK 0x00000000000000ffUL
906 #define MSIQ_TYPE_SHIFT 0
907 #define MSIQ_TYPE_NONE 0x00
908 #define MSIQ_TYPE_MSG 0x01
909 #define MSIQ_TYPE_MSI32 0x02
910 #define MSIQ_TYPE_MSI64 0x03
911 #define MSIQ_TYPE_INTX 0x08
912 #define MSIQ_TYPE_NONE2 0xff
917 u64 req_id; /* bus/device/func */
918 #define MSIQ_REQID_BUS_MASK 0xff00UL
919 #define MSIQ_REQID_BUS_SHIFT 8
920 #define MSIQ_REQID_DEVICE_MASK 0x00f8UL
921 #define MSIQ_REQID_DEVICE_SHIFT 3
922 #define MSIQ_REQID_FUNC_MASK 0x0007UL
923 #define MSIQ_REQID_FUNC_SHIFT 0
927 /* The format of this value is message type dependent.
928 * For MSI bits 15:0 are the data from the MSI packet.
929 * For MSI-X bits 31:0 are the data from the MSI packet.
930 * For MSG, the message code and message routing code where:
931 * bits 39:32 is the bus/device/fn of the msg target-id
932 * bits 18:16 is the message routing code
933 * bits 7:0 is the message code
934 * For INTx the low order 2-bits are:
945 static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
948 unsigned long err, limit;
950 err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head);
954 limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
955 if (unlikely(*head >= limit))
961 static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm,
962 unsigned long msiqid, unsigned long *head,
965 struct pci_sun4v_msiq_entry *ep;
966 unsigned long err, type;
968 /* Note: void pointer arithmetic, 'head' is a byte offset */
969 ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
970 (pbm->msiq_ent_count *
971 sizeof(struct pci_sun4v_msiq_entry))) +
974 if ((ep->version_type & MSIQ_TYPE_MASK) == 0)
977 type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
978 if (unlikely(type != MSIQ_TYPE_MSI32 &&
979 type != MSIQ_TYPE_MSI64))
984 err = pci_sun4v_msi_setstate(pbm->devhandle,
985 ep->msi_data /* msi_num */,
990 /* Clear the entry. */
991 ep->version_type &= ~MSIQ_TYPE_MASK;
993 (*head) += sizeof(struct pci_sun4v_msiq_entry);
995 (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry)))
1001 static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
1006 err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
1013 static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
1014 unsigned long msi, int is_msi64)
1016 if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid,
1018 HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
1020 if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE))
1022 if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID))
1027 static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
1029 unsigned long err, msiqid;
1031 err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid);
1035 pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID);
1040 static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm)
1042 unsigned long q_size, alloc_size, pages, order;
1045 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
1046 alloc_size = (pbm->msiq_num * q_size);
1047 order = get_order(alloc_size);
1048 pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
1050 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
1054 memset((char *)pages, 0, PAGE_SIZE << order);
1055 pbm->msi_queues = (void *) pages;
1057 for (i = 0; i < pbm->msiq_num; i++) {
1058 unsigned long err, base = __pa(pages + (i * q_size));
1059 unsigned long ret1, ret2;
1061 err = pci_sun4v_msiq_conf(pbm->devhandle,
1062 pbm->msiq_first + i,
1063 base, pbm->msiq_ent_count);
1065 printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
1070 err = pci_sun4v_msiq_info(pbm->devhandle,
1071 pbm->msiq_first + i,
1074 printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
1078 if (ret1 != base || ret2 != pbm->msiq_ent_count) {
1079 printk(KERN_ERR "MSI: Bogus qconf "
1080 "expected[%lx:%x] got[%lx:%lx]\n",
1081 base, pbm->msiq_ent_count,
1090 free_pages(pages, order);
1094 static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm)
1096 unsigned long q_size, alloc_size, pages, order;
1099 for (i = 0; i < pbm->msiq_num; i++) {
1100 unsigned long msiqid = pbm->msiq_first + i;
1102 (void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0);
1105 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
1106 alloc_size = (pbm->msiq_num * q_size);
1107 order = get_order(alloc_size);
1109 pages = (unsigned long) pbm->msi_queues;
1111 free_pages(pages, order);
1113 pbm->msi_queues = NULL;
1116 static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm,
1117 unsigned long msiqid,
1118 unsigned long devino)
1120 unsigned int irq = sun4v_build_irq(pbm->devhandle, devino);
1125 if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
1127 if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
1133 static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = {
1134 .get_head = pci_sun4v_get_head,
1135 .dequeue_msi = pci_sun4v_dequeue_msi,
1136 .set_head = pci_sun4v_set_head,
1137 .msi_setup = pci_sun4v_msi_setup,
1138 .msi_teardown = pci_sun4v_msi_teardown,
1139 .msiq_alloc = pci_sun4v_msiq_alloc,
1140 .msiq_free = pci_sun4v_msiq_free,
1141 .msiq_build_irq = pci_sun4v_msiq_build_irq,
1144 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1146 sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops);
1148 #else /* CONFIG_PCI_MSI */
1149 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1152 #endif /* !(CONFIG_PCI_MSI) */
1154 static int pci_sun4v_pbm_init(struct pci_pbm_info *pbm,
1155 struct platform_device *op, u32 devhandle)
1157 struct device_node *dp = op->dev.of_node;
1160 pbm->numa_node = of_node_to_nid(dp);
1162 pbm->pci_ops = &sun4v_pci_ops;
1163 pbm->config_space_reg_bits = 12;
1165 pbm->index = pci_num_pbms++;
1169 pbm->devhandle = devhandle;
1171 pbm->name = dp->full_name;
1173 printk("%s: SUN4V PCI Bus Module\n", pbm->name);
1174 printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node);
1176 pci_determine_mem_io_space(pbm);
1178 pci_get_pbm_props(pbm);
1180 err = pci_sun4v_iommu_init(pbm);
1184 pci_sun4v_msi_init(pbm);
1186 pci_sun4v_scan_bus(pbm, &op->dev);
1188 /* if atu_init fails its not complete failure.
1189 * we can still continue using legacy iommu.
1191 if (pbm->iommu->atu) {
1192 err = pci_sun4v_atu_init(pbm);
1194 kfree(pbm->iommu->atu);
1195 pbm->iommu->atu = NULL;
1196 pr_err(PFX "ATU init failed, err=%d\n", err);
1200 pbm->next = pci_pbm_root;
1206 static int pci_sun4v_probe(struct platform_device *op)
1208 const struct linux_prom64_registers *regs;
1209 static int hvapi_negotiated = 0;
1210 struct pci_pbm_info *pbm;
1211 struct device_node *dp;
1212 struct iommu *iommu;
1215 int i, err = -ENODEV;
1216 static bool hv_atu = true;
1218 dp = op->dev.of_node;
1220 if (!hvapi_negotiated++) {
1221 for (i = 0; i < ARRAY_SIZE(vpci_versions); i++) {
1222 vpci_major = vpci_versions[i].major;
1223 vpci_minor = vpci_versions[i].minor;
1225 err = sun4v_hvapi_register(HV_GRP_PCI, vpci_major,
1232 pr_err(PFX "Could not register hvapi, err=%d\n", err);
1235 pr_info(PFX "Registered hvapi major[%lu] minor[%lu]\n",
1236 vpci_major, vpci_minor);
1238 err = sun4v_hvapi_register(HV_GRP_ATU, vatu_major, &vatu_minor);
1240 /* don't return an error if we fail to register the
1241 * ATU group, but ATU hcalls won't be available.
1244 pr_err(PFX "Could not register hvapi ATU err=%d\n",
1247 pr_info(PFX "Registered hvapi ATU major[%lu] minor[%lu]\n",
1248 vatu_major, vatu_minor);
1251 dma_ops = &sun4v_dma_ops;
1254 regs = of_get_property(dp, "reg", NULL);
1257 printk(KERN_ERR PFX "Could not find config registers\n");
1260 devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1263 if (!iommu_batch_initialized) {
1264 for_each_possible_cpu(i) {
1265 unsigned long page = get_zeroed_page(GFP_KERNEL);
1270 per_cpu(iommu_batch, i).pglist = (u64 *) page;
1272 iommu_batch_initialized = 1;
1275 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
1277 printk(KERN_ERR PFX "Could not allocate pci_pbm_info\n");
1281 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
1283 printk(KERN_ERR PFX "Could not allocate pbm iommu\n");
1284 goto out_free_controller;
1290 atu = kzalloc(sizeof(*atu), GFP_KERNEL);
1292 pr_err(PFX "Could not allocate atu\n");
1297 err = pci_sun4v_pbm_init(pbm, op, devhandle);
1299 goto out_free_iommu;
1301 dev_set_drvdata(&op->dev, pbm);
1309 out_free_controller:
1316 static const struct of_device_id pci_sun4v_match[] = {
1319 .compatible = "SUNW,sun4v-pci",
1324 static struct platform_driver pci_sun4v_driver = {
1326 .name = DRIVER_NAME,
1327 .of_match_table = pci_sun4v_match,
1329 .probe = pci_sun4v_probe,
1332 static int __init pci_sun4v_init(void)
1334 return platform_driver_register(&pci_sun4v_driver);
1337 subsys_initcall(pci_sun4v_init);