arch/sparc/kernel/perf_event.c

   1 /* Performance event support for sparc64.
   2  *
   3  * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net>
   4  *
   5  * This code is based almost entirely upon the x86 perf event
   6  * code, which is:
   7  *
   8  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   9  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
  10  *  Copyright (C) 2009 Jaswinder Singh Rajput
  11  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
  12  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/kprobes.h>
  17 #include <linux/ftrace.h>
  18 #include <linux/kernel.h>
  19 #include <linux/kdebug.h>
  20 #include <linux/mutex.h>
  21
  22 #include <asm/stacktrace.h>
  23 #include <asm/cpudata.h>
  24 #include <asm/uaccess.h>
  25 #include <linux/atomic.h>
  26 #include <asm/nmi.h>
  27 #include <asm/pcr.h>
  28
  29 #include "kernel.h"
  30 #include "kstack.h"
  31
  32 /* Sparc64 chips have two performance counters, 32-bits each, with
  33  * overflow interrupts generated on transition from 0xffffffff to 0.
  34  * The counters are accessed in one go using a 64-bit register.
  35  *
  36  * Both counters are controlled using a single control register.  The
  37  * only way to stop all sampling is to clear all of the context (user,
  38  * supervisor, hypervisor) sampling enable bits.  But these bits apply
  39  * to both counters, thus the two counters can't be enabled/disabled
  40  * individually.
  41  *
  42  * The control register has two event fields, one for each of the two
  43  * counters.  It's thus nearly impossible to have one counter going
  44  * while keeping the other one stopped.  Therefore it is possible to
  45  * get overflow interrupts for counters not currently "in use" and
  46  * that condition must be checked in the overflow interrupt handler.
  47  *
  48  * So we use a hack, in that we program inactive counters with the
  49  * "sw_count0" and "sw_count1" events.  These count how many times
  50  * the instruction "sethi %hi(0xfc000), %g0" is executed.  It's an
  51  * unusual way to encode a NOP and therefore will not trigger in
  52  * normal code.
  53  */
  54
  55 #define MAX_HWEVENTS                    2
  56 #define MAX_PERIOD                      ((1UL << 32) - 1)
  57
  58 #define PIC_UPPER_INDEX                 0
  59 #define PIC_LOWER_INDEX                 1
  60 #define PIC_NO_INDEX                    -1
  61
  62 struct cpu_hw_events {
  63         /* Number of events currently scheduled onto this cpu.
  64          * This tells how many entries in the arrays below
  65          * are valid.
  66          */
  67         int                     n_events;
  68
  69         /* Number of new events added since the last hw_perf_disable().
  70          * This works because the perf event layer always adds new
  71          * events inside of a perf_{disable,enable}() sequence.
  72          */
  73         int                     n_added;
  74
  75         /* Array of events current scheduled on this cpu.  */
  76         struct perf_event       *event[MAX_HWEVENTS];
  77
  78         /* Array of encoded longs, specifying the %pcr register
  79          * encoding and the mask of PIC counters this even can
  80          * be scheduled on.  See perf_event_encode() et al.
  81          */
  82         unsigned long           events[MAX_HWEVENTS];
  83
  84         /* The current counter index assigned to an event.  When the
  85          * event hasn't been programmed into the cpu yet, this will
  86          * hold PIC_NO_INDEX.  The event->hw.idx value tells us where
  87          * we ought to schedule the event.
  88          */
  89         int                     current_idx[MAX_HWEVENTS];
  90
  91         /* Software copy of %pcr register on this cpu.  */
  92         u64                     pcr;
  93
  94         /* Enabled/disable state.  */
  95         int                     enabled;
  96
  97         unsigned int            group_flag;
  98 };
  99 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
 100
 101 /* An event map describes the characteristics of a performance
 102  * counter event.  In particular it gives the encoding as well as
 103  * a mask telling which counters the event can be measured on.
 104  */
 105 struct perf_event_map {
 106         u16     encoding;
 107         u8      pic_mask;
 108 #define PIC_NONE        0x00
 109 #define PIC_UPPER       0x01
 110 #define PIC_LOWER       0x02
 111 };
 112
 113 /* Encode a perf_event_map entry into a long.  */
 114 static unsigned long perf_event_encode(const struct perf_event_map *pmap)
 115 {
 116         return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask;
 117 }
 118
 119 static u8 perf_event_get_msk(unsigned long val)
 120 {
 121         return val & 0xff;
 122 }
 123
 124 static u64 perf_event_get_enc(unsigned long val)
 125 {
 126         return val >> 16;
 127 }
 128
 129 #define C(x) PERF_COUNT_HW_CACHE_##x
 130
 131 #define CACHE_OP_UNSUPPORTED    0xfffe
 132 #define CACHE_OP_NONSENSE       0xffff
 133
 134 typedef struct perf_event_map cache_map_t
 135                                 [PERF_COUNT_HW_CACHE_MAX]
 136                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 137                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 138
 139 struct sparc_pmu {
 140         const struct perf_event_map     *(*event_map)(int);
 141         const cache_map_t               *cache_map;
 142         int                             max_events;
 143         int                             upper_shift;
 144         int                             lower_shift;
 145         int                             event_mask;
 146         int                             hv_bit;
 147         int                             irq_bit;
 148         int                             upper_nop;
 149         int                             lower_nop;
 150 };
 151
 152 static const struct perf_event_map ultra3_perfmon_event_map[] = {
 153         [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER },
 154         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER },
 155         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER },
 156         [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER },
 157 };
 158
 159 static const struct perf_event_map *ultra3_event_map(int event_id)
 160 {
 161         return &ultra3_perfmon_event_map[event_id];
 162 }
 163
 164 static const cache_map_t ultra3_cache_map = {
 165 [C(L1D)] = {
 166         [C(OP_READ)] = {
 167                 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
 168                 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
 169         },
 170         [C(OP_WRITE)] = {
 171                 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
 172                 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
 173         },
 174         [C(OP_PREFETCH)] = {
 175                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 176                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 177         },
 178 },
 179 [C(L1I)] = {
 180         [C(OP_READ)] = {
 181                 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
 182                 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
 183         },
 184         [ C(OP_WRITE) ] = {
 185                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
 186                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
 187         },
 188         [ C(OP_PREFETCH) ] = {
 189                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 190                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 191         },
 192 },
 193 [C(LL)] = {
 194         [C(OP_READ)] = {
 195                 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, },
 196                 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, },
 197         },
 198         [C(OP_WRITE)] = {
 199                 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER },
 200                 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER },
 201         },
 202         [C(OP_PREFETCH)] = {
 203                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 204                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 205         },
 206 },
 207 [C(DTLB)] = {
 208         [C(OP_READ)] = {
 209                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 210                 [C(RESULT_MISS)] = { 0x12, PIC_UPPER, },
 211         },
 212         [ C(OP_WRITE) ] = {
 213                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 214                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 215         },
 216         [ C(OP_PREFETCH) ] = {
 217                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 218                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 219         },
 220 },
 221 [C(ITLB)] = {
 222         [C(OP_READ)] = {
 223                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 224                 [C(RESULT_MISS)] = { 0x11, PIC_UPPER, },
 225         },
 226         [ C(OP_WRITE) ] = {
 227                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 228                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 229         },
 230         [ C(OP_PREFETCH) ] = {
 231                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 232                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 233         },
 234 },
 235 [C(BPU)] = {
 236         [C(OP_READ)] = {
 237                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 238                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 239         },
 240         [ C(OP_WRITE) ] = {
 241                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 242                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 243         },
 244         [ C(OP_PREFETCH) ] = {
 245                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 246                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 247         },
 248 },
 249 [C(NODE)] = {
 250         [C(OP_READ)] = {
 251                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 252                 [C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
 253         },
 254         [ C(OP_WRITE) ] = {
 255                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 256                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 257         },
 258         [ C(OP_PREFETCH) ] = {
 259                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 260                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 261         },
 262 },
 263 };
 264
 265 static const struct sparc_pmu ultra3_pmu = {
 266         .event_map      = ultra3_event_map,
 267         .cache_map      = &ultra3_cache_map,
 268         .max_events     = ARRAY_SIZE(ultra3_perfmon_event_map),
 269         .upper_shift    = 11,
 270         .lower_shift    = 4,
 271         .event_mask     = 0x3f,
 272         .upper_nop      = 0x1c,
 273         .lower_nop      = 0x14,
 274 };
 275
 276 /* Niagara1 is very limited.  The upper PIC is hard-locked to count
 277  * only instructions, so it is free running which creates all kinds of
 278  * problems.  Some hardware designs make one wonder if the creator
 279  * even looked at how this stuff gets used by software.
 280  */
 281 static const struct perf_event_map niagara1_perfmon_event_map[] = {
 282         [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER },
 283         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER },
 284         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE },
 285         [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER },
 286 };
 287
 288 static const struct perf_event_map *niagara1_event_map(int event_id)
 289 {
 290         return &niagara1_perfmon_event_map[event_id];
 291 }
 292
 293 static const cache_map_t niagara1_cache_map = {
 294 [C(L1D)] = {
 295         [C(OP_READ)] = {
 296                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 297                 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
 298         },
 299         [C(OP_WRITE)] = {
 300                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 301                 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
 302         },
 303         [C(OP_PREFETCH)] = {
 304                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 305                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 306         },
 307 },
 308 [C(L1I)] = {
 309         [C(OP_READ)] = {
 310                 [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER },
 311                 [C(RESULT_MISS)] = { 0x02, PIC_LOWER, },
 312         },
 313         [ C(OP_WRITE) ] = {
 314                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
 315                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
 316         },
 317         [ C(OP_PREFETCH) ] = {
 318                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 319                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 320         },
 321 },
 322 [C(LL)] = {
 323         [C(OP_READ)] = {
 324                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 325                 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
 326         },
 327         [C(OP_WRITE)] = {
 328                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 329                 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
 330         },
 331         [C(OP_PREFETCH)] = {
 332                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 333                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 334         },
 335 },
 336 [C(DTLB)] = {
 337         [C(OP_READ)] = {
 338                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 339                 [C(RESULT_MISS)] = { 0x05, PIC_LOWER, },
 340         },
 341         [ C(OP_WRITE) ] = {
 342                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 343                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 344         },
 345         [ C(OP_PREFETCH) ] = {
 346                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 347                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 348         },
 349 },
 350 [C(ITLB)] = {
 351         [C(OP_READ)] = {
 352                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 353                 [C(RESULT_MISS)] = { 0x04, PIC_LOWER, },
 354         },
 355         [ C(OP_WRITE) ] = {
 356                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 357                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 358         },
 359         [ C(OP_PREFETCH) ] = {
 360                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 361                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 362         },
 363 },
 364 [C(BPU)] = {
 365         [C(OP_READ)] = {
 366                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 367                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 368         },
 369         [ C(OP_WRITE) ] = {
 370                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 371                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 372         },
 373         [ C(OP_PREFETCH) ] = {
 374                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 375                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 376         },
 377 },
 378 [C(NODE)] = {
 379         [C(OP_READ)] = {
 380                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 381                 [C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
 382         },
 383         [ C(OP_WRITE) ] = {
 384                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 385                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 386         },
 387         [ C(OP_PREFETCH) ] = {
 388                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 389                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 390         },
 391 },
 392 };
 393
 394 static const struct sparc_pmu niagara1_pmu = {
 395         .event_map      = niagara1_event_map,
 396         .cache_map      = &niagara1_cache_map,
 397         .max_events     = ARRAY_SIZE(niagara1_perfmon_event_map),
 398         .upper_shift    = 0,
 399         .lower_shift    = 4,
 400         .event_mask     = 0x7,
 401         .upper_nop      = 0x0,
 402         .lower_nop      = 0x0,
 403 };
 404
 405 static const struct perf_event_map niagara2_perfmon_event_map[] = {
 406         [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER },
 407         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER },
 408         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER },
 409         [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER },
 410         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER },
 411         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER },
 412 };
 413
 414 static const struct perf_event_map *niagara2_event_map(int event_id)
 415 {
 416         return &niagara2_perfmon_event_map[event_id];
 417 }
 418
 419 static const cache_map_t niagara2_cache_map = {
 420 [C(L1D)] = {
 421         [C(OP_READ)] = {
 422                 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
 423                 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
 424         },
 425         [C(OP_WRITE)] = {
 426                 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
 427                 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
 428         },
 429         [C(OP_PREFETCH)] = {
 430                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 431                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 432         },
 433 },
 434 [C(L1I)] = {
 435         [C(OP_READ)] = {
 436                 [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, },
 437                 [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, },
 438         },
 439         [ C(OP_WRITE) ] = {
 440                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
 441                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
 442         },
 443         [ C(OP_PREFETCH) ] = {
 444                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 445                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 446         },
 447 },
 448 [C(LL)] = {
 449         [C(OP_READ)] = {
 450                 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
 451                 [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, },
 452         },
 453         [C(OP_WRITE)] = {
 454                 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
 455                 [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, },
 456         },
 457         [C(OP_PREFETCH)] = {
 458                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 459                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 460         },
 461 },
 462 [C(DTLB)] = {
 463         [C(OP_READ)] = {
 464                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 465                 [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, },
 466         },
 467         [ C(OP_WRITE) ] = {
 468                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 469                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 470         },
 471         [ C(OP_PREFETCH) ] = {
 472                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 473                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 474         },
 475 },
 476 [C(ITLB)] = {
 477         [C(OP_READ)] = {
 478                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 479                 [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, },
 480         },
 481         [ C(OP_WRITE) ] = {
 482                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 483                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 484         },
 485         [ C(OP_PREFETCH) ] = {
 486                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 487                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 488         },
 489 },
 490 [C(BPU)] = {
 491         [C(OP_READ)] = {
 492                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 493                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 494         },
 495         [ C(OP_WRITE) ] = {
 496                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 497                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 498         },
 499         [ C(OP_PREFETCH) ] = {
 500                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 501                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 502         },
 503 },
 504 [C(NODE)] = {
 505         [C(OP_READ)] = {
 506                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 507                 [C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
 508         },
 509         [ C(OP_WRITE) ] = {
 510                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 511                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 512         },
 513         [ C(OP_PREFETCH) ] = {
 514                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 515                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 516         },
 517 },
 518 };
 519
 520 static const struct sparc_pmu niagara2_pmu = {
 521         .event_map      = niagara2_event_map,
 522         .cache_map      = &niagara2_cache_map,
 523         .max_events     = ARRAY_SIZE(niagara2_perfmon_event_map),
 524         .upper_shift    = 19,
 525         .lower_shift    = 6,
 526         .event_mask     = 0xfff,
 527         .hv_bit         = 0x8,
 528         .irq_bit        = 0x30,
 529         .upper_nop      = 0x220,
 530         .lower_nop      = 0x220,
 531 };
 532
 533 static const struct sparc_pmu *sparc_pmu __read_mostly;
 534
 535 static u64 event_encoding(u64 event_id, int idx)
 536 {
 537         if (idx == PIC_UPPER_INDEX)
 538                 event_id <<= sparc_pmu->upper_shift;
 539         else
 540                 event_id <<= sparc_pmu->lower_shift;
 541         return event_id;
 542 }
 543
 544 static u64 mask_for_index(int idx)
 545 {
 546         return event_encoding(sparc_pmu->event_mask, idx);
 547 }
 548
 549 static u64 nop_for_index(int idx)
 550 {
 551         return event_encoding(idx == PIC_UPPER_INDEX ?
 552                               sparc_pmu->upper_nop :
 553                               sparc_pmu->lower_nop, idx);
 554 }
 555
 556 static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
 557 {
 558         u64 enc, val, mask = mask_for_index(idx);
 559
 560         enc = perf_event_get_enc(cpuc->events[idx]);
 561
 562         val = cpuc->pcr;
 563         val &= ~mask;
 564         val |= event_encoding(enc, idx);
 565         cpuc->pcr = val;
 566
 567         pcr_ops->write(cpuc->pcr);
 568 }
 569
 570 static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
 571 {
 572         u64 mask = mask_for_index(idx);
 573         u64 nop = nop_for_index(idx);
 574         u64 val;
 575
 576         val = cpuc->pcr;
 577         val &= ~mask;
 578         val |= nop;
 579         cpuc->pcr = val;
 580
 581         pcr_ops->write(cpuc->pcr);
 582 }
 583
 584 static u32 read_pmc(int idx)
 585 {
 586         u64 val;
 587
 588         read_pic(val);
 589         if (idx == PIC_UPPER_INDEX)
 590                 val >>= 32;
 591
 592         return val & 0xffffffff;
 593 }
 594
 595 static void write_pmc(int idx, u64 val)
 596 {
 597         u64 shift, mask, pic;
 598
 599         shift = 0;
 600         if (idx == PIC_UPPER_INDEX)
 601                 shift = 32;
 602
 603         mask = ((u64) 0xffffffff) << shift;
 604         val <<= shift;
 605
 606         read_pic(pic);
 607         pic &= ~mask;
 608         pic |= val;
 609         write_pic(pic);
 610 }
 611
 612 static u64 sparc_perf_event_update(struct perf_event *event,
 613                                    struct hw_perf_event *hwc, int idx)
 614 {
 615         int shift = 64 - 32;
 616         u64 prev_raw_count, new_raw_count;
 617         s64 delta;
 618
 619 again:
 620         prev_raw_count = local64_read(&hwc->prev_count);
 621         new_raw_count = read_pmc(idx);
 622
 623         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 624                              new_raw_count) != prev_raw_count)
 625                 goto again;
 626
 627         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 628         delta >>= shift;
 629
 630         local64_add(delta, &event->count);
 631         local64_sub(delta, &hwc->period_left);
 632
 633         return new_raw_count;
 634 }
 635
 636 static int sparc_perf_event_set_period(struct perf_event *event,
 637                                        struct hw_perf_event *hwc, int idx)
 638 {
 639         s64 left = local64_read(&hwc->period_left);
 640         s64 period = hwc->sample_period;
 641         int ret = 0;
 642
 643         if (unlikely(left <= -period)) {
 644                 left = period;
 645                 local64_set(&hwc->period_left, left);
 646                 hwc->last_period = period;
 647                 ret = 1;
 648         }
 649
 650         if (unlikely(left <= 0)) {
 651                 left += period;
 652                 local64_set(&hwc->period_left, left);
 653                 hwc->last_period = period;
 654                 ret = 1;
 655         }
 656         if (left > MAX_PERIOD)
 657                 left = MAX_PERIOD;
 658
 659         local64_set(&hwc->prev_count, (u64)-left);
 660
 661         write_pmc(idx, (u64)(-left) & 0xffffffff);
 662
 663         perf_event_update_userpage(event);
 664
 665         return ret;
 666 }
 667
 668 /* If performance event entries have been added, move existing
 669  * events around (if necessary) and then assign new entries to
 670  * counters.
 671  */
 672 static u64 maybe_change_configuration(struct cpu_hw_events *cpuc, u64 pcr)
 673 {
 674         int i;
 675
 676         if (!cpuc->n_added)
 677                 goto out;
 678
 679         /* Read in the counters which are moving.  */
 680         for (i = 0; i < cpuc->n_events; i++) {
 681                 struct perf_event *cp = cpuc->event[i];
 682
 683                 if (cpuc->current_idx[i] != PIC_NO_INDEX &&
 684                     cpuc->current_idx[i] != cp->hw.idx) {
 685                         sparc_perf_event_update(cp, &cp->hw,
 686                                                 cpuc->current_idx[i]);
 687                         cpuc->current_idx[i] = PIC_NO_INDEX;
 688                 }
 689         }
 690
 691         /* Assign to counters all unassigned events.  */
 692         for (i = 0; i < cpuc->n_events; i++) {
 693                 struct perf_event *cp = cpuc->event[i];
 694                 struct hw_perf_event *hwc = &cp->hw;
 695                 int idx = hwc->idx;
 696                 u64 enc;
 697
 698                 if (cpuc->current_idx[i] != PIC_NO_INDEX)
 699                         continue;
 700
 701                 sparc_perf_event_set_period(cp, hwc, idx);
 702                 cpuc->current_idx[i] = idx;
 703
 704                 enc = perf_event_get_enc(cpuc->events[i]);
 705                 pcr &= ~mask_for_index(idx);
 706                 if (hwc->state & PERF_HES_STOPPED)
 707                         pcr |= nop_for_index(idx);
 708                 else
 709                         pcr |= event_encoding(enc, idx);
 710         }
 711 out:
 712         return pcr;
 713 }
 714
 715 static void sparc_pmu_enable(struct pmu *pmu)
 716 {
 717         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 718         u64 pcr;
 719
 720         if (cpuc->enabled)
 721                 return;
 722
 723         cpuc->enabled = 1;
 724         barrier();
 725
 726         pcr = cpuc->pcr;
 727         if (!cpuc->n_events) {
 728                 pcr = 0;
 729         } else {
 730                 pcr = maybe_change_configuration(cpuc, pcr);
 731
 732                 /* We require that all of the events have the same
 733                  * configuration, so just fetch the settings from the
 734                  * first entry.
 735                  */
 736                 cpuc->pcr = pcr | cpuc->event[0]->hw.config_base;
 737         }
 738
 739         pcr_ops->write(cpuc->pcr);
 740 }
 741
 742 static void sparc_pmu_disable(struct pmu *pmu)
 743 {
 744         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 745         u64 val;
 746
 747         if (!cpuc->enabled)
 748                 return;
 749
 750         cpuc->enabled = 0;
 751         cpuc->n_added = 0;
 752
 753         val = cpuc->pcr;
 754         val &= ~(PCR_UTRACE | PCR_STRACE |
 755                  sparc_pmu->hv_bit | sparc_pmu->irq_bit);
 756         cpuc->pcr = val;
 757
 758         pcr_ops->write(cpuc->pcr);
 759 }
 760
 761 static int active_event_index(struct cpu_hw_events *cpuc,
 762                               struct perf_event *event)
 763 {
 764         int i;
 765
 766         for (i = 0; i < cpuc->n_events; i++) {
 767                 if (cpuc->event[i] == event)
 768                         break;
 769         }
 770         BUG_ON(i == cpuc->n_events);
 771         return cpuc->current_idx[i];
 772 }
 773
 774 static void sparc_pmu_start(struct perf_event *event, int flags)
 775 {
 776         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 777         int idx = active_event_index(cpuc, event);
 778
 779         if (flags & PERF_EF_RELOAD) {
 780                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
 781                 sparc_perf_event_set_period(event, &event->hw, idx);
 782         }
 783
 784         event->hw.state = 0;
 785
 786         sparc_pmu_enable_event(cpuc, &event->hw, idx);
 787 }
 788
 789 static void sparc_pmu_stop(struct perf_event *event, int flags)
 790 {
 791         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 792         int idx = active_event_index(cpuc, event);
 793
 794         if (!(event->hw.state & PERF_HES_STOPPED)) {
 795                 sparc_pmu_disable_event(cpuc, &event->hw, idx);
 796                 event->hw.state |= PERF_HES_STOPPED;
 797         }
 798
 799         if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) {
 800                 sparc_perf_event_update(event, &event->hw, idx);
 801                 event->hw.state |= PERF_HES_UPTODATE;
 802         }
 803 }
 804
 805 static void sparc_pmu_del(struct perf_event *event, int _flags)
 806 {
 807         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 808         unsigned long flags;
 809         int i;
 810
 811         local_irq_save(flags);
 812         perf_pmu_disable(event->pmu);
 813
 814         for (i = 0; i < cpuc->n_events; i++) {
 815                 if (event == cpuc->event[i]) {
 816                         /* Absorb the final count and turn off the
 817                          * event.
 818                          */
 819                         sparc_pmu_stop(event, PERF_EF_UPDATE);
 820
 821                         /* Shift remaining entries down into
 822                          * the existing slot.
 823                          */
 824                         while (++i < cpuc->n_events) {
 825                                 cpuc->event[i - 1] = cpuc->event[i];
 826                                 cpuc->events[i - 1] = cpuc->events[i];
 827                                 cpuc->current_idx[i - 1] =
 828                                         cpuc->current_idx[i];
 829                         }
 830
 831                         perf_event_update_userpage(event);
 832
 833                         cpuc->n_events--;
 834                         break;
 835                 }
 836         }
 837
 838         perf_pmu_enable(event->pmu);
 839         local_irq_restore(flags);
 840 }
 841
 842 static void sparc_pmu_read(struct perf_event *event)
 843 {
 844         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 845         int idx = active_event_index(cpuc, event);
 846         struct hw_perf_event *hwc = &event->hw;
 847
 848         sparc_perf_event_update(event, hwc, idx);
 849 }
 850
 851 static atomic_t active_events = ATOMIC_INIT(0);
 852 static DEFINE_MUTEX(pmc_grab_mutex);
 853
 854 static void perf_stop_nmi_watchdog(void *unused)
 855 {
 856         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 857
 858         stop_nmi_watchdog(NULL);
 859         cpuc->pcr = pcr_ops->read();
 860 }
 861
 862 void perf_event_grab_pmc(void)
 863 {
 864         if (atomic_inc_not_zero(&active_events))
 865                 return;
 866
 867         mutex_lock(&pmc_grab_mutex);
 868         if (atomic_read(&active_events) == 0) {
 869                 if (atomic_read(&nmi_active) > 0) {
 870                         on_each_cpu(perf_stop_nmi_watchdog, NULL, 1);
 871                         BUG_ON(atomic_read(&nmi_active) != 0);
 872                 }
 873                 atomic_inc(&active_events);
 874         }
 875         mutex_unlock(&pmc_grab_mutex);
 876 }
 877
 878 void perf_event_release_pmc(void)
 879 {
 880         if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) {
 881                 if (atomic_read(&nmi_active) == 0)
 882                         on_each_cpu(start_nmi_watchdog, NULL, 1);
 883                 mutex_unlock(&pmc_grab_mutex);
 884         }
 885 }
 886
 887 static const struct perf_event_map *sparc_map_cache_event(u64 config)
 888 {
 889         unsigned int cache_type, cache_op, cache_result;
 890         const struct perf_event_map *pmap;
 891
 892         if (!sparc_pmu->cache_map)
 893                 return ERR_PTR(-ENOENT);
 894
 895         cache_type = (config >>  0) & 0xff;
 896         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 897                 return ERR_PTR(-EINVAL);
 898
 899         cache_op = (config >>  8) & 0xff;
 900         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 901                 return ERR_PTR(-EINVAL);
 902
 903         cache_result = (config >> 16) & 0xff;
 904         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 905                 return ERR_PTR(-EINVAL);
 906
 907         pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]);
 908
 909         if (pmap->encoding == CACHE_OP_UNSUPPORTED)
 910                 return ERR_PTR(-ENOENT);
 911
 912         if (pmap->encoding == CACHE_OP_NONSENSE)
 913                 return ERR_PTR(-EINVAL);
 914
 915         return pmap;
 916 }
 917
 918 static void hw_perf_event_destroy(struct perf_event *event)
 919 {
 920         perf_event_release_pmc();
 921 }
 922
 923 /* Make sure all events can be scheduled into the hardware at
 924  * the same time.  This is simplified by the fact that we only
 925  * need to support 2 simultaneous HW events.
 926  *
 927  * As a side effect, the evts[]->hw.idx values will be assigned
 928  * on success.  These are pending indexes.  When the events are
 929  * actually programmed into the chip, these values will propagate
 930  * to the per-cpu cpuc->current_idx[] slots, see the code in
 931  * maybe_change_configuration() for details.
 932  */
 933 static int sparc_check_constraints(struct perf_event **evts,
 934                                    unsigned long *events, int n_ev)
 935 {
 936         u8 msk0 = 0, msk1 = 0;
 937         int idx0 = 0;
 938
 939         /* This case is possible when we are invoked from
 940          * hw_perf_group_sched_in().
 941          */
 942         if (!n_ev)
 943                 return 0;
 944
 945         if (n_ev > MAX_HWEVENTS)
 946                 return -1;
 947
 948         msk0 = perf_event_get_msk(events[0]);
 949         if (n_ev == 1) {
 950                 if (msk0 & PIC_LOWER)
 951                         idx0 = 1;
 952                 goto success;
 953         }
 954         BUG_ON(n_ev != 2);
 955         msk1 = perf_event_get_msk(events[1]);
 956
 957         /* If both events can go on any counter, OK.  */
 958         if (msk0 == (PIC_UPPER | PIC_LOWER) &&
 959             msk1 == (PIC_UPPER | PIC_LOWER))
 960                 goto success;
 961
 962         /* If one event is limited to a specific counter,
 963          * and the other can go on both, OK.
 964          */
 965         if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&
 966             msk1 == (PIC_UPPER | PIC_LOWER)) {
 967                 if (msk0 & PIC_LOWER)
 968                         idx0 = 1;
 969                 goto success;
 970         }
 971
 972         if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
 973             msk0 == (PIC_UPPER | PIC_LOWER)) {
 974                 if (msk1 & PIC_UPPER)
 975                         idx0 = 1;
 976                 goto success;
 977         }
 978
 979         /* If the events are fixed to different counters, OK.  */
 980         if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||
 981             (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) {
 982                 if (msk0 & PIC_LOWER)
 983                         idx0 = 1;
 984                 goto success;
 985         }
 986
 987         /* Otherwise, there is a conflict.  */
 988         return -1;
 989
 990 success:
 991         evts[0]->hw.idx = idx0;
 992         if (n_ev == 2)
 993                 evts[1]->hw.idx = idx0 ^ 1;
 994         return 0;
 995 }
 996
 997 static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
 998 {
 999         int eu = 0, ek = 0, eh = 0;
1000         struct perf_event *event;
1001         int i, n, first;
1002
1003         n = n_prev + n_new;
1004         if (n <= 1)
1005                 return 0;
1006
1007         first = 1;
1008         for (i = 0; i < n; i++) {
1009                 event = evts[i];
1010                 if (first) {
1011                         eu = event->attr.exclude_user;
1012                         ek = event->attr.exclude_kernel;
1013                         eh = event->attr.exclude_hv;
1014                         first = 0;
1015                 } else if (event->attr.exclude_user != eu ||
1016                            event->attr.exclude_kernel != ek ||
1017                            event->attr.exclude_hv != eh) {
1018                         return -EAGAIN;
1019                 }
1020         }
1021
1022         return 0;
1023 }
1024
1025 static int collect_events(struct perf_event *group, int max_count,
1026                           struct perf_event *evts[], unsigned long *events,
1027                           int *current_idx)
1028 {
1029         struct perf_event *event;
1030         int n = 0;
1031
1032         if (!is_software_event(group)) {
1033                 if (n >= max_count)
1034                         return -1;
1035                 evts[n] = group;
1036                 events[n] = group->hw.event_base;
1037                 current_idx[n++] = PIC_NO_INDEX;
1038         }
1039         list_for_each_entry(event, &group->sibling_list, group_entry) {
1040                 if (!is_software_event(event) &&
1041                     event->state != PERF_EVENT_STATE_OFF) {
1042                         if (n >= max_count)
1043                                 return -1;
1044                         evts[n] = event;
1045                         events[n] = event->hw.event_base;
1046                         current_idx[n++] = PIC_NO_INDEX;
1047                 }
1048         }
1049         return n;
1050 }
1051
1052 static int sparc_pmu_add(struct perf_event *event, int ef_flags)
1053 {
1054         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1055         int n0, ret = -EAGAIN;
1056         unsigned long flags;
1057
1058         local_irq_save(flags);
1059         perf_pmu_disable(event->pmu);
1060
1061         n0 = cpuc->n_events;
1062         if (n0 >= MAX_HWEVENTS)
1063                 goto out;
1064
1065         cpuc->event[n0] = event;
1066         cpuc->events[n0] = event->hw.event_base;
1067         cpuc->current_idx[n0] = PIC_NO_INDEX;
1068
1069         event->hw.state = PERF_HES_UPTODATE;
1070         if (!(ef_flags & PERF_EF_START))
1071                 event->hw.state |= PERF_HES_STOPPED;
1072
1073         /*
1074          * If group events scheduling transaction was started,
1075          * skip the schedulability test here, it will be performed
1076          * at commit time(->commit_txn) as a whole
1077          */
1078         if (cpuc->group_flag & PERF_EVENT_TXN)
1079                 goto nocheck;
1080
1081         if (check_excludes(cpuc->event, n0, 1))
1082                 goto out;
1083         if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1))
1084                 goto out;
1085
1086 nocheck:
1087         cpuc->n_events++;
1088         cpuc->n_added++;
1089
1090         ret = 0;
1091 out:
1092         perf_pmu_enable(event->pmu);
1093         local_irq_restore(flags);
1094         return ret;
1095 }
1096
1097 static int sparc_pmu_event_init(struct perf_event *event)
1098 {
1099         struct perf_event_attr *attr = &event->attr;
1100         struct perf_event *evts[MAX_HWEVENTS];
1101         struct hw_perf_event *hwc = &event->hw;
1102         unsigned long events[MAX_HWEVENTS];
1103         int current_idx_dmy[MAX_HWEVENTS];
1104         const struct perf_event_map *pmap;
1105         int n;
1106
1107         if (atomic_read(&nmi_active) < 0)
1108                 return -ENODEV;
1109
1110         switch (attr->type) {
1111         case PERF_TYPE_HARDWARE:
1112                 if (attr->config >= sparc_pmu->max_events)
1113                         return -EINVAL;
1114                 pmap = sparc_pmu->event_map(attr->config);
1115                 break;
1116
1117         case PERF_TYPE_HW_CACHE:
1118                 pmap = sparc_map_cache_event(attr->config);
1119                 if (IS_ERR(pmap))
1120                         return PTR_ERR(pmap);
1121                 break;
1122
1123         case PERF_TYPE_RAW:
1124                 pmap = NULL;
1125                 break;
1126
1127         default:
1128                 return -ENOENT;
1129
1130         }
1131
1132         if (pmap) {
1133                 hwc->event_base = perf_event_encode(pmap);
1134         } else {
1135                 /*
1136                  * User gives us "(encoding << 16) | pic_mask" for
1137                  * PERF_TYPE_RAW events.
1138                  */
1139                 hwc->event_base = attr->config;
1140         }
1141
1142         /* We save the enable bits in the config_base.  */
1143         hwc->config_base = sparc_pmu->irq_bit;
1144         if (!attr->exclude_user)
1145                 hwc->config_base |= PCR_UTRACE;
1146         if (!attr->exclude_kernel)
1147                 hwc->config_base |= PCR_STRACE;
1148         if (!attr->exclude_hv)
1149                 hwc->config_base |= sparc_pmu->hv_bit;
1150
1151         n = 0;
1152         if (event->group_leader != event) {
1153                 n = collect_events(event->group_leader,
1154                                    MAX_HWEVENTS - 1,
1155                                    evts, events, current_idx_dmy);
1156                 if (n < 0)
1157                         return -EINVAL;
1158         }
1159         events[n] = hwc->event_base;
1160         evts[n] = event;
1161
1162         if (check_excludes(evts, n, 1))
1163                 return -EINVAL;
1164
1165         if (sparc_check_constraints(evts, events, n + 1))
1166                 return -EINVAL;
1167
1168         hwc->idx = PIC_NO_INDEX;
1169
1170         /* Try to do all error checking before this point, as unwinding
1171          * state after grabbing the PMC is difficult.
1172          */
1173         perf_event_grab_pmc();
1174         event->destroy = hw_perf_event_destroy;
1175
1176         if (!hwc->sample_period) {
1177                 hwc->sample_period = MAX_PERIOD;
1178                 hwc->last_period = hwc->sample_period;
1179                 local64_set(&hwc->period_left, hwc->sample_period);
1180         }
1181
1182         return 0;
1183 }
1184
1185 /*
1186  * Start group events scheduling transaction
1187  * Set the flag to make pmu::enable() not perform the
1188  * schedulability test, it will be performed at commit time
1189  */
1190 static void sparc_pmu_start_txn(struct pmu *pmu)
1191 {
1192         struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1193
1194         perf_pmu_disable(pmu);
1195         cpuhw->group_flag |= PERF_EVENT_TXN;
1196 }
1197
1198 /*
1199  * Stop group events scheduling transaction
1200  * Clear the flag and pmu::enable() will perform the
1201  * schedulability test.
1202  */
1203 static void sparc_pmu_cancel_txn(struct pmu *pmu)
1204 {
1205         struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1206
1207         cpuhw->group_flag &= ~PERF_EVENT_TXN;
1208         perf_pmu_enable(pmu);
1209 }
1210
1211 /*
1212  * Commit group events scheduling transaction
1213  * Perform the group schedulability test as a whole
1214  * Return 0 if success
1215  */
1216 static int sparc_pmu_commit_txn(struct pmu *pmu)
1217 {
1218         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1219         int n;
1220
1221         if (!sparc_pmu)
1222                 return -EINVAL;
1223
1224         cpuc = &__get_cpu_var(cpu_hw_events);
1225         n = cpuc->n_events;
1226         if (check_excludes(cpuc->event, 0, n))
1227                 return -EINVAL;
1228         if (sparc_check_constraints(cpuc->event, cpuc->events, n))
1229                 return -EAGAIN;
1230
1231         cpuc->group_flag &= ~PERF_EVENT_TXN;
1232         perf_pmu_enable(pmu);
1233         return 0;
1234 }
1235
1236 static struct pmu pmu = {
1237         .pmu_enable     = sparc_pmu_enable,
1238         .pmu_disable    = sparc_pmu_disable,
1239         .event_init     = sparc_pmu_event_init,
1240         .add            = sparc_pmu_add,
1241         .del            = sparc_pmu_del,
1242         .start          = sparc_pmu_start,
1243         .stop           = sparc_pmu_stop,
1244         .read           = sparc_pmu_read,
1245         .start_txn      = sparc_pmu_start_txn,
1246         .cancel_txn     = sparc_pmu_cancel_txn,
1247         .commit_txn     = sparc_pmu_commit_txn,
1248 };
1249
1250 void perf_event_print_debug(void)
1251 {
1252         unsigned long flags;
1253         u64 pcr, pic;
1254         int cpu;
1255
1256         if (!sparc_pmu)
1257                 return;
1258
1259         local_irq_save(flags);
1260
1261         cpu = smp_processor_id();
1262
1263         pcr = pcr_ops->read();
1264         read_pic(pic);
1265
1266         pr_info("\n");
1267         pr_info("CPU#%d: PCR[%016llx] PIC[%016llx]\n",
1268                 cpu, pcr, pic);
1269
1270         local_irq_restore(flags);
1271 }
1272
1273 static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
1274                                             unsigned long cmd, void *__args)
1275 {
1276         struct die_args *args = __args;
1277         struct perf_sample_data data;
1278         struct cpu_hw_events *cpuc;
1279         struct pt_regs *regs;
1280         int i;
1281
1282         if (!atomic_read(&active_events))
1283                 return NOTIFY_DONE;
1284
1285         switch (cmd) {
1286         case DIE_NMI:
1287                 break;
1288
1289         default:
1290                 return NOTIFY_DONE;
1291         }
1292
1293         regs = args->regs;
1294
1295         perf_sample_data_init(&data, 0);
1296
1297         cpuc = &__get_cpu_var(cpu_hw_events);
1298
1299         /* If the PMU has the TOE IRQ enable bits, we need to do a
1300          * dummy write to the %pcr to clear the overflow bits and thus
1301          * the interrupt.
1302          *
1303          * Do this before we peek at the counters to determine
1304          * overflow so we don't lose any events.
1305          */
1306         if (sparc_pmu->irq_bit)
1307                 pcr_ops->write(cpuc->pcr);
1308
1309         for (i = 0; i < cpuc->n_events; i++) {
1310                 struct perf_event *event = cpuc->event[i];
1311                 int idx = cpuc->current_idx[i];
1312                 struct hw_perf_event *hwc;
1313                 u64 val;
1314
1315                 hwc = &event->hw;
1316                 val = sparc_perf_event_update(event, hwc, idx);
1317                 if (val & (1ULL << 31))
1318                         continue;
1319
1320                 data.period = event->hw.last_period;
1321                 if (!sparc_perf_event_set_period(event, hwc, idx))
1322                         continue;
1323
1324                 if (perf_event_overflow(event, &data, regs))
1325                         sparc_pmu_stop(event, 0);
1326         }
1327
1328         return NOTIFY_STOP;
1329 }
1330
1331 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1332         .notifier_call          = perf_event_nmi_handler,
1333 };
1334
1335 static bool __init supported_pmu(void)
1336 {
1337         if (!strcmp(sparc_pmu_type, "ultra3") ||
1338             !strcmp(sparc_pmu_type, "ultra3+") ||
1339             !strcmp(sparc_pmu_type, "ultra3i") ||
1340             !strcmp(sparc_pmu_type, "ultra4+")) {
1341                 sparc_pmu = &ultra3_pmu;
1342                 return true;
1343         }
1344         if (!strcmp(sparc_pmu_type, "niagara")) {
1345                 sparc_pmu = &niagara1_pmu;
1346                 return true;
1347         }
1348         if (!strcmp(sparc_pmu_type, "niagara2") ||
1349             !strcmp(sparc_pmu_type, "niagara3")) {
1350                 sparc_pmu = &niagara2_pmu;
1351                 return true;
1352         }
1353         return false;
1354 }
1355
1356 int __init init_hw_perf_events(void)
1357 {
1358         pr_info("Performance events: ");
1359
1360         if (!supported_pmu()) {
1361                 pr_cont("No support for PMU type '%s'\n", sparc_pmu_type);
1362                 return 0;
1363         }
1364
1365         pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
1366
1367         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1368         register_die_notifier(&perf_event_nmi_notifier);
1369
1370         return 0;
1371 }
1372 early_initcall(init_hw_perf_events);
1373
1374 void perf_callchain_kernel(struct perf_callchain_entry *entry,
1375                            struct pt_regs *regs)
1376 {
1377         unsigned long ksp, fp;
1378 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1379         int graph = 0;
1380 #endif
1381
1382         stack_trace_flush();
1383
1384         perf_callchain_store(entry, regs->tpc);
1385
1386         ksp = regs->u_regs[UREG_I6];
1387         fp = ksp + STACK_BIAS;
1388         do {
1389                 struct sparc_stackf *sf;
1390                 struct pt_regs *regs;
1391                 unsigned long pc;
1392
1393                 if (!kstack_valid(current_thread_info(), fp))
1394                         break;
1395
1396                 sf = (struct sparc_stackf *) fp;
1397                 regs = (struct pt_regs *) (sf + 1);
1398
1399                 if (kstack_is_trap_frame(current_thread_info(), regs)) {
1400                         if (user_mode(regs))
1401                                 break;
1402                         pc = regs->tpc;
1403                         fp = regs->u_regs[UREG_I6] + STACK_BIAS;
1404                 } else {
1405                         pc = sf->callers_pc;
1406                         fp = (unsigned long)sf->fp + STACK_BIAS;
1407                 }
1408                 perf_callchain_store(entry, pc);
1409 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1410                 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
1411                         int index = current->curr_ret_stack;
1412                         if (current->ret_stack && index >= graph) {
1413                                 pc = current->ret_stack[index - graph].ret;
1414                                 perf_callchain_store(entry, pc);
1415                                 graph++;
1416                         }
1417                 }
1418 #endif
1419         } while (entry->nr < PERF_MAX_STACK_DEPTH);
1420 }
1421
1422 static void perf_callchain_user_64(struct perf_callchain_entry *entry,
1423                                    struct pt_regs *regs)
1424 {
1425         unsigned long ufp;
1426
1427         ufp = regs->u_regs[UREG_I6] + STACK_BIAS;
1428         do {
1429                 struct sparc_stackf *usf, sf;
1430                 unsigned long pc;
1431
1432                 usf = (struct sparc_stackf *) ufp;
1433                 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1434                         break;
1435
1436                 pc = sf.callers_pc;
1437                 ufp = (unsigned long)sf.fp + STACK_BIAS;
1438                 perf_callchain_store(entry, pc);
1439         } while (entry->nr < PERF_MAX_STACK_DEPTH);
1440 }
1441
1442 static void perf_callchain_user_32(struct perf_callchain_entry *entry,
1443                                    struct pt_regs *regs)
1444 {
1445         unsigned long ufp;
1446
1447         ufp = regs->u_regs[UREG_I6] & 0xffffffffUL;
1448         do {
1449                 struct sparc_stackf32 *usf, sf;
1450                 unsigned long pc;
1451
1452                 usf = (struct sparc_stackf32 *) ufp;
1453                 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1454                         break;
1455
1456                 pc = sf.callers_pc;
1457                 ufp = (unsigned long)sf.fp;
1458                 perf_callchain_store(entry, pc);
1459         } while (entry->nr < PERF_MAX_STACK_DEPTH);
1460 }
1461
1462 void
1463 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1464 {
1465         perf_callchain_store(entry, regs->tpc);
1466
1467         if (!current->mm)
1468                 return;
1469
1470         flushw_user();
1471         if (test_thread_flag(TIF_32BIT))
1472                 perf_callchain_user_32(entry, regs);
1473         else
1474                 perf_callchain_user_64(entry, regs);
1475 }